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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 193:31151fcc3cb7
prev191:df4441cf3128
next197:f65ff8c8320d
author nkeynes
date Fri Aug 04 01:38:30 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add more tile list limit tests
Implement tile list limits in the ta core.
Rename TA_TILEEND to TA_LISTEND
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     1 /**
     2  * $Id: pvr2.c,v 1.30 2006-08-04 01:38:27 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "display.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2/pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2/pvr2mmio.h"
    29 char *video_base;
    31 static void pvr2_init( void );
    32 static void pvr2_reset( void );
    33 static uint32_t pvr2_run_slice( uint32_t );
    34 static void pvr2_save_state( FILE *f );
    35 static int pvr2_load_state( FILE *f );
    37 void pvr2_display_frame( void );
    39 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
    41 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    42 					pvr2_run_slice, NULL,
    43 					pvr2_save_state, pvr2_load_state };
    46 display_driver_t display_driver = NULL;
    48 struct video_timing {
    49     int fields_per_second;
    50     int total_lines;
    51     int retrace_lines;
    52     int line_time_ns;
    53 };
    55 struct video_timing pal_timing = { 50, 625, 65, 32000 };
    56 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    58 struct pvr2_state {
    59     uint32_t frame_count;
    60     uint32_t line_count;
    61     uint32_t line_remainder;
    62     uint32_t irq_vpos1;
    63     uint32_t irq_vpos2;
    64     gboolean retrace;
    65     struct video_timing timing;
    66 } pvr2_state;
    68 struct video_buffer video_buffer[2];
    69 int video_buffer_idx = 0;
    71 static void pvr2_init( void )
    72 {
    73     register_io_region( &mmio_region_PVR2 );
    74     register_io_region( &mmio_region_PVR2PAL );
    75     register_io_region( &mmio_region_PVR2TA );
    76     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    77     texcache_init();
    78     pvr2_reset();
    79 }
    81 static void pvr2_reset( void )
    82 {
    83     pvr2_state.line_count = 0;
    84     pvr2_state.line_remainder = 0;
    85     pvr2_state.irq_vpos1 = 0;
    86     pvr2_state.irq_vpos2 = 0;
    87     pvr2_state.retrace = FALSE;
    88     pvr2_state.timing = ntsc_timing;
    89     video_buffer_idx = 0;
    91     pvr2_ta_init();
    92     pvr2_render_init();
    93     texcache_flush();
    94 }
    96 static void pvr2_save_state( FILE *f )
    97 {
    98     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
    99     pvr2_ta_save_state( f );
   100 }
   102 static int pvr2_load_state( FILE *f )
   103 {
   104     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   105 	return 1;
   106     return pvr2_ta_load_state(f);
   107 }
   109 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   110 {
   111     pvr2_state.line_remainder += nanosecs;
   112     while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
   113 	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
   115 	pvr2_state.line_count++;
   116 	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
   117 	    asic_event( EVENT_RETRACE );
   118 	    pvr2_state.line_count = 0;
   119 	    pvr2_state.retrace = TRUE;
   120 	}
   122 	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
   123 	    asic_event( EVENT_SCANLINE1 );
   124 	} 
   125 	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
   126 	    asic_event( EVENT_SCANLINE2 );
   127 	}
   129 	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
   130 	    if( pvr2_state.retrace ) {
   131 		pvr2_display_frame();
   132 		pvr2_state.retrace = FALSE;
   133 	    }
   134 	}
   135     }
   136     return nanosecs;
   137 }
   139 int pvr2_get_frame_count() 
   140 {
   141     return pvr2_state.frame_count;
   142 }
   144 /**
   145  * Display the next frame, copying the current contents of video ram to
   146  * the window. If the video configuration has changed, first recompute the
   147  * new frame size/depth.
   148  */
   149 void pvr2_display_frame( void )
   150 {
   151     uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
   153     int dispsize = MMIO_READ( PVR2, DISPSIZE );
   154     int dispmode = MMIO_READ( PVR2, DISPMODE );
   155     int vidcfg = MMIO_READ( PVR2, DISPCFG );
   156     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   157     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   158     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   159     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   160     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   161     video_buffer_t buffer = &video_buffer[video_buffer_idx];
   162     video_buffer_idx = !video_buffer_idx;
   163     video_buffer_t last = &video_buffer[video_buffer_idx];
   164     buffer->rowstride = (vid_ppl + vid_stride) << 2;
   165     buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
   166     buffer->vres = vid_lpf;
   167     if( interlaced ) buffer->vres <<= 1;
   168     switch( (dispmode & DISPMODE_COL) >> 2 ) {
   169     case 0: 
   170 	buffer->colour_format = COLFMT_ARGB1555;
   171 	buffer->hres = vid_ppl << 1; 
   172 	break;
   173     case 1: 
   174 	buffer->colour_format = COLFMT_RGB565;
   175 	buffer->hres = vid_ppl << 1; 
   176 	break;
   177     case 2:
   178 	buffer->colour_format = COLFMT_RGB888;
   179 	buffer->hres = (vid_ppl << 2) / 3; 
   180 	break;
   181     case 3: 
   182 	buffer->colour_format = COLFMT_ARGB8888;
   183 	buffer->hres = vid_ppl; 
   184 	break;
   185     }
   187     if( buffer->hres <=8 )
   188 	buffer->hres = 640;
   189     if( buffer->vres <=8 )
   190 	buffer->vres = 480;
   191     if( display_driver != NULL ) {
   192 	if( buffer->hres != last->hres ||
   193 	    buffer->vres != last->vres ||
   194 	    buffer->colour_format != last->colour_format) {
   195 	    display_driver->set_display_format( buffer->hres, buffer->vres,
   196 						buffer->colour_format );
   197 	}
   198 	if( !bEnabled ) {
   199 	    display_driver->display_blank_frame( 0 );
   200 	} else if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
   201 	    uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
   202 	    display_driver->display_blank_frame( colour );
   203 	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   204 	    display_driver->display_frame( buffer );
   205 	}
   206     }
   207     pvr2_state.frame_count++;
   208 }
   210 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   211 {
   212     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   213         MMIO_WRITE( PVR2, reg, val );
   214         /* I don't want to hear about these */
   215         return;
   216     }
   218     switch(reg) {
   219     case PVRID:
   220     case PVRVER:
   221     case GUNPOS:
   222     case TA_POLYPOS:
   223     case TA_LISTPOS:
   224 	/* Readonly registers */
   225 	break;
   226     case RENDER_START:
   227 	if( val == 0xFFFFFFFF )
   228 	    pvr2_render_scene();
   229 	break;
   230     case PVRUNK1:
   231     	MMIO_WRITE( PVR2, reg, val&0x000007FF );
   232     	break;
   233     case RENDER_POLYBASE:
   234     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   235     	break;
   236     case RENDER_TSPCFG:
   237     	MMIO_WRITE( PVR2, reg, val&0x00010101 );
   238     	break;
   239     case DISPBORDER:
   240     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   241     	break;
   242     case DISPMODE:
   243     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   244     	break;
   245     case RENDER_MODE:
   246     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   247     	break;
   248     case RENDER_SIZE:
   249     	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   250     	break;
   251     case DISPADDR1:
   252 	val &= 0x00FFFFFC;
   253 	MMIO_WRITE( PVR2, reg, val );
   254 	if( pvr2_state.retrace ) {
   255 	    pvr2_display_frame();
   256 	    pvr2_state.retrace = FALSE;
   257 	}
   258 	break;
   259     case DISPADDR2:
   260     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   261     	break;
   262     case DISPSIZE:
   263     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   264     	break;
   265     case RENDER_ADDR1:
   266     case RENDER_ADDR2:
   267     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   268     	break;
   269     case RENDER_HCLIP:
   270 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   271 	break;
   272     case RENDER_VCLIP:
   273 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   274 	break;
   275     case HPOS_IRQ:
   276 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   277 	break;
   278     case VPOS_IRQ:
   279 	val = val & 0x03FF03FF;
   280 	pvr2_state.irq_vpos1 = (val >> 16);
   281 	pvr2_state.irq_vpos2 = val & 0x03FF;
   282 	MMIO_WRITE( PVR2, reg, val );
   283 	break;
   284     case RENDER_SHADOW:
   285 	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   286 	break;
   287     case RENDER_OBJCFG:
   288     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   289     	break;
   290     case RENDER_TSPCLIP:
   291     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   292     	break;
   293     case RENDER_BGPLANE:
   294     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   295     	break;
   296     case RENDER_ISPCFG:
   297     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   298     	break;
   299     case TA_TILEBASE:
   300     case TA_LISTEND:
   301     case TA_LISTBASE:
   302 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   303 	break;
   304     case RENDER_TILEBASE:
   305     case TA_POLYBASE:
   306     case TA_POLYEND:
   307 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   308 	break;
   309     case TA_TILESIZE:
   310 	MMIO_WRITE( PVR2, reg, val&0x000F003F );
   311 	break;
   312     case TA_TILECFG:
   313 	MMIO_WRITE( PVR2, reg, val&0x00133333 );
   314 	break;
   315     case TA_INIT:
   316 	if( val & 0x80000000 )
   317 	    pvr2_ta_init();
   318 	break;
   320     /* Nonexistent registers (as far as we know, anyway) */
   321     case 0x01C:
   322     case 0x024:
   323     case 0x028:
   324     case 0x058:
   325     	break;
   326     default:
   327 	MMIO_WRITE( PVR2, reg, val );
   328     }
   329 }
   331 MMIO_REGION_READ_FN( PVR2, reg )
   332 {
   333     switch( reg ) {
   334         case BEAMPOS:
   335             return sh4r.icount&0x20 ? 0x2000 : 1;
   336         default:
   337             return MMIO_READ( PVR2, reg );
   338     }
   339 }
   341 MMIO_REGION_DEFFNS( PVR2PAL )
   343 void pvr2_set_base_address( uint32_t base ) 
   344 {
   345     mmio_region_PVR2_write( DISPADDR1, base );
   346 }
   351 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   352 {
   353     return 0xFFFFFFFF;
   354 }
   356 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   357 {
   358     pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
   359 }
   362 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
   363 {
   364     int bank_flag = (destaddr & 0x04) >> 2;
   365     uint32_t *banks[2];
   366     uint32_t *dwsrc;
   367     int i;
   369     destaddr = destaddr & 0x7FFFFF;
   370     if( destaddr + length > 0x800000 ) {
   371 	length = 0x800000 - destaddr;
   372     }
   374     for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
   375 	texcache_invalidate_page( i );
   376     }
   378     banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
   379     banks[1] = banks[0] + 0x100000;
   380     if( bank_flag ) 
   381 	banks[0]++;
   383     /* Handle non-aligned start of source */
   384     if( destaddr & 0x03 ) {
   385 	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
   386 	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   387 	    *dest++ = *src++;
   388 	}
   389 	bank_flag = !bank_flag;
   390     }
   392     dwsrc = (uint32_t *)src;
   393     while( length >= 4 ) {
   394 	*banks[bank_flag]++ = *dwsrc++;
   395 	bank_flag = !bank_flag;
   396 	length -= 4;
   397     }
   399     /* Handle non-aligned end of source */
   400     if( length ) {
   401 	src = (char *)dwsrc;
   402 	char *dest = (char *)banks[bank_flag];
   403 	while( length-- > 0 ) {
   404 	    *dest++ = *src++;
   405 	}
   406     }  
   408 }
   410 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
   411 {
   412     int bank_flag = (srcaddr & 0x04) >> 2;
   413     uint32_t *banks[2];
   414     uint32_t *dwdest;
   415     int i;
   417     srcaddr = srcaddr & 0x7FFFFF;
   418     if( srcaddr + length > 0x800000 )
   419 	length = 0x800000 - srcaddr;
   421     banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
   422     banks[1] = banks[0] + 0x100000;
   423     if( bank_flag )
   424 	banks[0]++;
   426     /* Handle non-aligned start of source */
   427     if( srcaddr & 0x03 ) {
   428 	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
   429 	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   430 	    *dest++ = *src++;
   431 	}
   432 	bank_flag = !bank_flag;
   433     }
   435     dwdest = (uint32_t *)dest;
   436     while( length >= 4 ) {
   437 	*dwdest++ = *banks[bank_flag]++;
   438 	bank_flag = !bank_flag;
   439 	length -= 4;
   440     }
   442     /* Handle non-aligned end of source */
   443     if( length ) {
   444 	dest = (char *)dwdest;
   445 	char *src = (char *)banks[bank_flag];
   446 	while( length-- > 0 ) {
   447 	    *dest++ = *src++;
   448 	}
   449     }
   450 }
   452 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
   453 {
   454     char tmp[length];
   455     pvr2_vram64_read( tmp, addr, length );
   456     fwrite_dump( tmp, length, f );
   457 }
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