lxdream.org :: lxdream/src/sh4/sh4core.c r671:a530ea88eebd

tree revision 706:3135a0770e19

filename	src/sh4/sh4core.c
changeset	671:a530ea88eebd
prev	669:ab344e42bca9
next	732:f05753bbe723
author	nkeynes
date	Wed Jun 25 10:03:28 2008 +0000 (15 years ago)
permissions	-rw-r--r--
last change	Add sh4_dump_region convenience function

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     1 /**

     2  * $Id$

     3  *

     4  * SH4 emulation core, and parent module for all the SH4 peripheral

     5  * modules.

     6  *

     7  * Copyright (c) 2005 Nathan Keynes.

     8  *

     9  * This program is free software; you can redistribute it and/or modify

    10  * it under the terms of the GNU General Public License as published by

    11  * the Free Software Foundation; either version 2 of the License, or

    12  * (at your option) any later version.

    13  *

    14  * This program is distributed in the hope that it will be useful,

    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  * GNU General Public License for more details.

    18  */

    20 #define MODULE sh4_module

    21 #include <assert.h>

    22 #include <math.h>

    23 #include "dream.h"

    24 #include "dreamcast.h"

    25 #include "eventq.h"

    26 #include "mem.h"

    27 #include "clock.h"

    28 #include "syscall.h"

    29 #include "sh4/sh4core.h"

    30 #include "sh4/sh4mmio.h"

    31 #include "sh4/sh4stat.h"

    32 #include "sh4/intc.h"

    34 #define SH4_CALLTRACE 1

    36 #define MAX_INT 0x7FFFFFFF

    37 #define MIN_INT 0x80000000

    38 #define MAX_INTF 2147483647.0

    39 #define MIN_INTF -2147483648.0

    41 /********************** SH4 Module Definition ****************************/

    43 uint32_t sh4_run_slice( uint32_t nanosecs )

    44 {

    45     int i;

    46     sh4r.slice_cycle = 0;

    48     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {

    49 	sh4_sleep_run_slice(nanosecs);

    50     }

    52     if( sh4_breakpoint_count == 0 ) {

    53 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

    54 	    if( SH4_EVENT_PENDING() ) {

    55 		if( sh4r.event_types & PENDING_EVENT ) {

    56 		    event_execute();

    57 		}

    58 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

    59 		if( sh4r.event_types & PENDING_IRQ ) {

    60 		    sh4_accept_interrupt();

    61 		}

    62 	    }

    63 	    if( !sh4_execute_instruction() ) {

    64 		break;

    65 	    }

    66 	}

    67     } else {

    68 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

    69 	    if( SH4_EVENT_PENDING() ) {

    70 		if( sh4r.event_types & PENDING_EVENT ) {

    71 		    event_execute();

    72 		}

    73 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

    74 		if( sh4r.event_types & PENDING_IRQ ) {

    75 		    sh4_accept_interrupt();

    76 		}

    77 	    }

    79 	    if( !sh4_execute_instruction() )

    80 		break;

    81 #ifdef ENABLE_DEBUG_MODE

    82 	    for( i=0; i<sh4_breakpoint_count; i++ ) {

    83 		if( sh4_breakpoints[i].address == sh4r.pc ) {

    84 		    break;

    85 		}

    86 	    }

    87 	    if( i != sh4_breakpoint_count ) {

    88 		dreamcast_stop();

    89 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )

    90 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );

    91 		break;

    92 	    }

    93 #endif

    94 	}

    95     }

    97     /* If we aborted early, but the cpu is still technically running,

    98      * we're doing a hard abort - cut the timeslice back to what we

    99      * actually executed

   100      */

   101     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {

   102 	nanosecs = sh4r.slice_cycle;

   103     }

   104     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {

   105 	TMU_run_slice( nanosecs );

   106 	SCIF_run_slice( nanosecs );

   107     }

   108     return nanosecs;

   109 }

   111 /********************** SH4 emulation core  ****************************/

   113 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)

   114 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)

   116 #if(SH4_CALLTRACE == 1)

   117 #define MAX_CALLSTACK 32

   118 static struct call_stack {

   119     sh4addr_t call_addr;

   120     sh4addr_t target_addr;

   121     sh4addr_t stack_pointer;

   122 } call_stack[MAX_CALLSTACK];

   124 static int call_stack_depth = 0;

   125 int sh4_call_trace_on = 0;

   127 static inline void trace_call( sh4addr_t source, sh4addr_t dest )

   128 {

   129     if( call_stack_depth < MAX_CALLSTACK ) {

   130 	call_stack[call_stack_depth].call_addr = source;

   131 	call_stack[call_stack_depth].target_addr = dest;

   132 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];

   133     }

   134     call_stack_depth++;

   135 }

   137 static inline void trace_return( sh4addr_t source, sh4addr_t dest )

   138 {

   139     if( call_stack_depth > 0 ) {

   140 	call_stack_depth--;

   141     }

   142 }

   144 void fprint_stack_trace( FILE *f )

   145 {

   146     int i = call_stack_depth -1;

   147     if( i >= MAX_CALLSTACK )

   148 	i = MAX_CALLSTACK - 1;

   149     for( ; i >= 0; i-- ) {

   150 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",

   151 		 (call_stack_depth - i), call_stack[i].call_addr,

   152 		 call_stack[i].target_addr, call_stack[i].stack_pointer );

   153     }

   154 }

   156 #define TRACE_CALL( source, dest ) trace_call(source, dest)

   157 #define TRACE_RETURN( source, dest ) trace_return(source, dest)

   158 #else

   159 #define TRACE_CALL( dest, rts )

   160 #define TRACE_RETURN( source, dest )

   161 #endif

   163 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }

   164 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }

   165 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }

   166 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }

   167 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }

   168 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }

   170 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)

   172 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );

   173 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );

   175 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )

   176 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

   177 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

   178 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

   179 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

   181 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }

   182 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }

   183 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)

   185 static void sh4_write_float( uint32_t addr, int reg )

   186 {

   187     if( IS_FPU_DOUBLESIZE() ) {

   188 	if( reg & 1 ) {

   189 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );

   190 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );

   191 	} else {

   192 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) );

   193 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );

   194 	}

   195     } else {

   196 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );

   197     }

   198 }

   200 static void sh4_read_float( uint32_t addr, int reg )

   201 {

   202     if( IS_FPU_DOUBLESIZE() ) {

   203 	if( reg & 1 ) {

   204 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);

   205 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);

   206 	} else {

   207 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);

   208 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);

   209 	}

   210     } else {

   211 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);

   212     }

   213 }

   215 gboolean sh4_execute_instruction( void )

   216 {

   217     uint32_t pc;

   218     unsigned short ir;

   219     uint32_t tmp;

   220     float ftmp;

   221     double dtmp;

   222     int64_t memtmp; // temporary holder for memory reads

   224 #define R0 sh4r.r[0]

   225     pc = sh4r.pc;

   226     if( pc > 0xFFFFFF00 ) {

   227 	/* SYSCALL Magic */

   228 	syscall_invoke( pc );

   229 	sh4r.in_delay_slot = 0;

   230 	pc = sh4r.pc = sh4r.pr;

   231 	sh4r.new_pc = sh4r.pc + 2;

   232         return TRUE;

   233     }

   234     CHECKRALIGN16(pc);

   236 #ifdef ENABLE_SH4STATS

   237     sh4_stats_add_by_pc(sh4r.pc);

   238 #endif

   240     /* Read instruction */

   241     if( !IS_IN_ICACHE(pc) ) {

   242 	if( !mmu_update_icache(pc) ) {

   243 	    // Fault - look for the fault handler

   244 	    if( !mmu_update_icache(sh4r.pc) ) {

   245 		// double fault - halt

   246 		ERROR( "Double fault - halting" );

   247 		dreamcast_stop();

   248 		return FALSE;

   249 	    }

   250 	}

   251 	pc = sh4r.pc;

   252     }

   253     assert( IS_IN_ICACHE(pc) );

   254     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);

   255         switch( (ir&0xF000) >> 12 ) {

   256             case 0x0:

   257                 switch( ir&0xF ) {

   258                     case 0x2:

   259                         switch( (ir&0x80) >> 7 ) {

   260                             case 0x0:

   261                                 switch( (ir&0x70) >> 4 ) {

   262                                     case 0x0:

   263                                         { /* STC SR, Rn */

   264                                         uint32_t Rn = ((ir>>8)&0xF);

   265                                         CHECKPRIV();

   266                                         sh4r.r[Rn] = sh4_read_sr();

   267                                         }

   268                                         break;

   269                                     case 0x1:

   270                                         { /* STC GBR, Rn */

   271                                         uint32_t Rn = ((ir>>8)&0xF);

   272                                         sh4r.r[Rn] = sh4r.gbr;

   273                                         }

   274                                         break;

   275                                     case 0x2:

   276                                         { /* STC VBR, Rn */

   277                                         uint32_t Rn = ((ir>>8)&0xF);

   278                                         CHECKPRIV();

   279                                         sh4r.r[Rn] = sh4r.vbr;

   280                                         }

   281                                         break;

   282                                     case 0x3:

   283                                         { /* STC SSR, Rn */

   284                                         uint32_t Rn = ((ir>>8)&0xF);

   285                                         CHECKPRIV();

   286                                         sh4r.r[Rn] = sh4r.ssr;

   287                                         }

   288                                         break;

   289                                     case 0x4:

   290                                         { /* STC SPC, Rn */

   291                                         uint32_t Rn = ((ir>>8)&0xF);

   292                                         CHECKPRIV();

   293                                         sh4r.r[Rn] = sh4r.spc;

   294                                         }

   295                                         break;

   296                                     default:

   297                                         UNDEF();

   298                                         break;

   299                                 }

   300                                 break;

   301                             case 0x1:

   302                                 { /* STC Rm_BANK, Rn */

   303                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   304                                 CHECKPRIV();

   305                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];

   306                                 }

   307                                 break;

   308                         }

   309                         break;

   310                     case 0x3:

   311                         switch( (ir&0xF0) >> 4 ) {

   312                             case 0x0:

   313                                 { /* BSRF Rn */

   314                                 uint32_t Rn = ((ir>>8)&0xF);

   315                                 CHECKSLOTILLEGAL();

   316                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );

   317                                 sh4r.in_delay_slot = 1;

   318                                 sh4r.pr = sh4r.pc + 4;

   319                                 sh4r.pc = sh4r.new_pc;

   320                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];

   321                                 TRACE_CALL( pc, sh4r.new_pc );

   322                                 return TRUE;

   323                                 }

   324                                 break;

   325                             case 0x2:

   326                                 { /* BRAF Rn */

   327                                 uint32_t Rn = ((ir>>8)&0xF);

   328                                 CHECKSLOTILLEGAL();

   329                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );

   330                                 sh4r.in_delay_slot = 1;

   331                                 sh4r.pc = sh4r.new_pc;

   332                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];

   333                                 return TRUE;

   334                                 }

   335                                 break;

   336                             case 0x8:

   337                                 { /* PREF @Rn */

   338                                 uint32_t Rn = ((ir>>8)&0xF);

   339                                 tmp = sh4r.r[Rn];

   340                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {

   341                            	 sh4_flush_store_queue(tmp);

   342                                 }

   343                                 }

   344                                 break;

   345                             case 0x9:

   346                                 { /* OCBI @Rn */

   347                                 uint32_t Rn = ((ir>>8)&0xF);

   348                                 }

   349                                 break;

   350                             case 0xA:

   351                                 { /* OCBP @Rn */

   352                                 uint32_t Rn = ((ir>>8)&0xF);

   353                                 }

   354                                 break;

   355                             case 0xB:

   356                                 { /* OCBWB @Rn */

   357                                 uint32_t Rn = ((ir>>8)&0xF);

   358                                 }

   359                                 break;

   360                             case 0xC:

   361                                 { /* MOVCA.L R0, @Rn */

   362                                 uint32_t Rn = ((ir>>8)&0xF);

   363                                 tmp = sh4r.r[Rn];

   364                                 CHECKWALIGN32(tmp);

   365                                 MEM_WRITE_LONG( tmp, R0 );

   366                                 }

   367                                 break;

   368                             default:

   369                                 UNDEF();

   370                                 break;

   371                         }

   372                         break;

   373                     case 0x4:

   374                         { /* MOV.B Rm, @(R0, Rn) */

   375                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   376                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   377                         }

   378                         break;

   379                     case 0x5:

   380                         { /* MOV.W Rm, @(R0, Rn) */

   381                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   382                         CHECKWALIGN16( R0 + sh4r.r[Rn] );

   383                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   384                         }

   385                         break;

   386                     case 0x6:

   387                         { /* MOV.L Rm, @(R0, Rn) */

   388                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   389                         CHECKWALIGN32( R0 + sh4r.r[Rn] );

   390                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   391                         }

   392                         break;

   393                     case 0x7:

   394                         { /* MUL.L Rm, Rn */

   395                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   396                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   397                                                (sh4r.r[Rm] * sh4r.r[Rn]);

   398                         }

   399                         break;

   400                     case 0x8:

   401                         switch( (ir&0xFF0) >> 4 ) {

   402                             case 0x0:

   403                                 { /* CLRT */

   404                                 sh4r.t = 0;

   405                                 }

   406                                 break;

   407                             case 0x1:

   408                                 { /* SETT */

   409                                 sh4r.t = 1;

   410                                 }

   411                                 break;

   412                             case 0x2:

   413                                 { /* CLRMAC */

   414                                 sh4r.mac = 0;

   415                                 }

   416                                 break;

   417                             case 0x3:

   418                                 { /* LDTLB */

   419                                 MMU_ldtlb();

   420                                 }

   421                                 break;

   422                             case 0x4:

   423                                 { /* CLRS */

   424                                 sh4r.s = 0;

   425                                 }

   426                                 break;

   427                             case 0x5:

   428                                 { /* SETS */

   429                                 sh4r.s = 1;

   430                                 }

   431                                 break;

   432                             default:

   433                                 UNDEF();

   434                                 break;

   435                         }

   436                         break;

   437                     case 0x9:

   438                         switch( (ir&0xF0) >> 4 ) {

   439                             case 0x0:

   440                                 { /* NOP */

   441                                 /* NOP */

   442                                 }

   443                                 break;

   444                             case 0x1:

   445                                 { /* DIV0U */

   446                                 sh4r.m = sh4r.q = sh4r.t = 0;

   447                                 }

   448                                 break;

   449                             case 0x2:

   450                                 { /* MOVT Rn */

   451                                 uint32_t Rn = ((ir>>8)&0xF);

   452                                 sh4r.r[Rn] = sh4r.t;

   453                                 }

   454                                 break;

   455                             default:

   456                                 UNDEF();

   457                                 break;

   458                         }

   459                         break;

   460                     case 0xA:

   461                         switch( (ir&0xF0) >> 4 ) {

   462                             case 0x0:

   463                                 { /* STS MACH, Rn */

   464                                 uint32_t Rn = ((ir>>8)&0xF);

   465                                 sh4r.r[Rn] = (sh4r.mac>>32);

   466                                 }

   467                                 break;

   468                             case 0x1:

   469                                 { /* STS MACL, Rn */

   470                                 uint32_t Rn = ((ir>>8)&0xF);

   471                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;

   472                                 }

   473                                 break;

   474                             case 0x2:

   475                                 { /* STS PR, Rn */

   476                                 uint32_t Rn = ((ir>>8)&0xF);

   477                                 sh4r.r[Rn] = sh4r.pr;

   478                                 }

   479                                 break;

   480                             case 0x3:

   481                                 { /* STC SGR, Rn */

   482                                 uint32_t Rn = ((ir>>8)&0xF);

   483                                 CHECKPRIV();

   484                                 sh4r.r[Rn] = sh4r.sgr;

   485                                 }

   486                                 break;

   487                             case 0x5:

   488                                 { /* STS FPUL, Rn */

   489                                 uint32_t Rn = ((ir>>8)&0xF);

   490                                 CHECKFPUEN();

   491                                 sh4r.r[Rn] = FPULi;

   492                                 }

   493                                 break;

   494                             case 0x6:

   495                                 { /* STS FPSCR, Rn */

   496                                 uint32_t Rn = ((ir>>8)&0xF);

   497                                 CHECKFPUEN();

   498                                 sh4r.r[Rn] = sh4r.fpscr;

   499                                 }

   500                                 break;

   501                             case 0xF:

   502                                 { /* STC DBR, Rn */

   503                                 uint32_t Rn = ((ir>>8)&0xF);

   504                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;

   505                                 }

   506                                 break;

   507                             default:

   508                                 UNDEF();

   509                                 break;

   510                         }

   511                         break;

   512                     case 0xB:

   513                         switch( (ir&0xFF0) >> 4 ) {

   514                             case 0x0:

   515                                 { /* RTS */

   516                                 CHECKSLOTILLEGAL();

   517                                 CHECKDEST( sh4r.pr );

   518                                 sh4r.in_delay_slot = 1;

   519                                 sh4r.pc = sh4r.new_pc;

   520                                 sh4r.new_pc = sh4r.pr;

   521                                 TRACE_RETURN( pc, sh4r.new_pc );

   522                                 return TRUE;

   523                                 }

   524                                 break;

   525                             case 0x1:

   526                                 { /* SLEEP */

   527                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {

   528                             	sh4r.sh4_state = SH4_STATE_STANDBY;

   529                                 } else {

   530                             	sh4r.sh4_state = SH4_STATE_SLEEP;

   531                                 }

   532                                 return FALSE; /* Halt CPU */

   533                                 }

   534                                 break;

   535                             case 0x2:

   536                                 { /* RTE */

   537                                 CHECKPRIV();

   538                                 CHECKDEST( sh4r.spc );

   539                                 CHECKSLOTILLEGAL();

   540                                 sh4r.in_delay_slot = 1;

   541                                 sh4r.pc = sh4r.new_pc;

   542                                 sh4r.new_pc = sh4r.spc;

   543                                 sh4_write_sr( sh4r.ssr );

   544                                 return TRUE;

   545                                 }

   546                                 break;

   547                             default:

   548                                 UNDEF();

   549                                 break;

   550                         }

   551                         break;

   552                     case 0xC:

   553                         { /* MOV.B @(R0, Rm), Rn */

   554                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   555                         MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   556                         }

   557                         break;

   558                     case 0xD:

   559                         { /* MOV.W @(R0, Rm), Rn */

   560                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   561                         CHECKRALIGN16( R0 + sh4r.r[Rm] );

   562                            MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   563                         }

   564                         break;

   565                     case 0xE:

   566                         { /* MOV.L @(R0, Rm), Rn */

   567                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   568                         CHECKRALIGN32( R0 + sh4r.r[Rm] );

   569                            MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   570                         }

   571                         break;

   572                     case 0xF:

   573                         { /* MAC.L @Rm+, @Rn+ */

   574                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   575                         int64_t tmpl;

   576                         if( Rm == Rn ) {

   577                     	CHECKRALIGN32( sh4r.r[Rn] );

   578                     	MEM_READ_LONG(sh4r.r[Rn], tmp);

   579                     	tmpl = SIGNEXT32(tmp);

   580                     	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);

   581                     	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;

   582                     	sh4r.r[Rn] += 8;

   583                         } else {

   584                     	CHECKRALIGN32( sh4r.r[Rm] );

   585                     	CHECKRALIGN32( sh4r.r[Rn] );

   586                     	MEM_READ_LONG(sh4r.r[Rn], tmp);

   587                     	tmpl = SIGNEXT32(tmp);

   588                     	MEM_READ_LONG(sh4r.r[Rm], tmp);

   589                     	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;

   590                     	sh4r.r[Rn] += 4;

   591                     	sh4r.r[Rm] += 4;

   592                         }

   593                         if( sh4r.s ) {

   594                             /* 48-bit Saturation. Yuch */

   595                             if( tmpl < (int64_t)0xFFFF800000000000LL )

   596                                 tmpl = 0xFFFF800000000000LL;

   597                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )

   598                                 tmpl = 0x00007FFFFFFFFFFFLL;

   599                         }

   600                         sh4r.mac = tmpl;

   601                         }

   602                         break;

   603                     default:

   604                         UNDEF();

   605                         break;

   606                 }

   607                 break;

   608             case 0x1:

   609                 { /* MOV.L Rm, @(disp, Rn) */

   610                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

   611                 tmp = sh4r.r[Rn] + disp;

   612                 CHECKWALIGN32( tmp );

   613                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );

   614                 }

   615                 break;

   616             case 0x2:

   617                 switch( ir&0xF ) {

   618                     case 0x0:

   619                         { /* MOV.B Rm, @Rn */

   620                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   621                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );

   622                         }

   623                         break;

   624                     case 0x1:

   625                         { /* MOV.W Rm, @Rn */

   626                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   627                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );

   628                         }

   629                         break;

   630                     case 0x2:

   631                         { /* MOV.L Rm, @Rn */

   632                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   633                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );

   634                         }

   635                         break;

   636                     case 0x4:

   637                         { /* MOV.B Rm, @-Rn */

   638                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   639                         MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--;

   640                         }

   641                         break;

   642                     case 0x5:

   643                         { /* MOV.W Rm, @-Rn */

   644                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   645                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2;

   646                         }

   647                         break;

   648                     case 0x6:

   649                         { /* MOV.L Rm, @-Rn */

   650                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   651                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4;

   652                         }

   653                         break;

   654                     case 0x7:

   655                         { /* DIV0S Rm, Rn */

   656                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   657                         sh4r.q = sh4r.r[Rn]>>31;

   658                         sh4r.m = sh4r.r[Rm]>>31;

   659                         sh4r.t = sh4r.q ^ sh4r.m;

   660                         }

   661                         break;

   662                     case 0x8:

   663                         { /* TST Rm, Rn */

   664                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   665                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);

   666                         }

   667                         break;

   668                     case 0x9:

   669                         { /* AND Rm, Rn */

   670                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   671                         sh4r.r[Rn] &= sh4r.r[Rm];

   672                         }

   673                         break;

   674                     case 0xA:

   675                         { /* XOR Rm, Rn */

   676                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   677                         sh4r.r[Rn] ^= sh4r.r[Rm];

   678                         }

   679                         break;

   680                     case 0xB:

   681                         { /* OR Rm, Rn */

   682                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   683                         sh4r.r[Rn] |= sh4r.r[Rm];

   684                         }

   685                         break;

   686                     case 0xC:

   687                         { /* CMP/STR Rm, Rn */

   688                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   689                         /* set T = 1 if any byte in RM & RN is the same */

   690                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];

   691                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||

   692                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;

   693                         }

   694                         break;

   695                     case 0xD:

   696                         { /* XTRCT Rm, Rn */

   697                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   698                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);

   699                         }

   700                         break;

   701                     case 0xE:

   702                         { /* MULU.W Rm, Rn */

   703                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   704                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   705                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));

   706                         }

   707                         break;

   708                     case 0xF:

   709                         { /* MULS.W Rm, Rn */

   710                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   711                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   712                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));

   713                         }

   714                         break;

   715                     default:

   716                         UNDEF();

   717                         break;

   718                 }

   719                 break;

   720             case 0x3:

   721                 switch( ir&0xF ) {

   722                     case 0x0:

   723                         { /* CMP/EQ Rm, Rn */

   724                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   725                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );

   726                         }

   727                         break;

   728                     case 0x2:

   729                         { /* CMP/HS Rm, Rn */

   730                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   731                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );

   732                         }

   733                         break;

   734                     case 0x3:

   735                         { /* CMP/GE Rm, Rn */

   736                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   737                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

   738                         }

   739                         break;

   740                     case 0x4:

   741                         { /* DIV1 Rm, Rn */

   742                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   743                         /* This is derived from the sh4 manual with some simplifications */

   744                         uint32_t tmp0, tmp1, tmp2, dir;

   746                         dir = sh4r.q ^ sh4r.m;

   747                         sh4r.q = (sh4r.r[Rn] >> 31);

   748                         tmp2 = sh4r.r[Rm];

   749                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;

   750                         tmp0 = sh4r.r[Rn];

   751                         if( dir ) {

   752                              sh4r.r[Rn] += tmp2;

   753                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );

   754                         } else {

   755                              sh4r.r[Rn] -= tmp2;

   756                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );

   757                         }

   758                         sh4r.q ^= sh4r.m ^ tmp1;

   759                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );

   760                         }

   761                         break;

   762                     case 0x5:

   763                         { /* DMULU.L Rm, Rn */

   764                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   765                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);

   766                         }

   767                         break;

   768                     case 0x6:

   769                         { /* CMP/HI Rm, Rn */

   770                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   771                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );

   772                         }

   773                         break;

   774                     case 0x7:

   775                         { /* CMP/GT Rm, Rn */

   776                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   777                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

   778                         }

   779                         break;

   780                     case 0x8:

   781                         { /* SUB Rm, Rn */

   782                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   783                         sh4r.r[Rn] -= sh4r.r[Rm];

   784                         }

   785                         break;

   786                     case 0xA:

   787                         { /* SUBC Rm, Rn */

   788                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   789                         tmp = sh4r.r[Rn];

   790                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;

   791                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));

   792                         }

   793                         break;

   794                     case 0xB:

   795                         UNIMP(ir); /* SUBV Rm, Rn */

   796                         break;

   797                     case 0xC:

   798                         { /* ADD Rm, Rn */

   799                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   800                         sh4r.r[Rn] += sh4r.r[Rm];

   801                         }

   802                         break;

   803                     case 0xD:

   804                         { /* DMULS.L Rm, Rn */

   805                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   806                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);

   807                         }

   808                         break;

   809                     case 0xE:

   810                         { /* ADDC Rm, Rn */

   811                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   812                         tmp = sh4r.r[Rn];

   813                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;

   814                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );

   815                         }

   816                         break;

   817                     case 0xF:

   818                         { /* ADDV Rm, Rn */

   819                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   820                         tmp = sh4r.r[Rn] + sh4r.r[Rm];

   821                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );

   822                         sh4r.r[Rn] = tmp;

   823                         }

   824                         break;

   825                     default:

   826                         UNDEF();

   827                         break;

   828                 }

   829                 break;

   830             case 0x4:

   831                 switch( ir&0xF ) {

   832                     case 0x0:

   833                         switch( (ir&0xF0) >> 4 ) {

   834                             case 0x0:

   835                                 { /* SHLL Rn */

   836                                 uint32_t Rn = ((ir>>8)&0xF);

   837                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;

   838                                 }

   839                                 break;

   840                             case 0x1:

   841                                 { /* DT Rn */

   842                                 uint32_t Rn = ((ir>>8)&0xF);

   843                                 sh4r.r[Rn] --;

   844                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );

   845                                 }

   846                                 break;

   847                             case 0x2:

   848                                 { /* SHAL Rn */

   849                                 uint32_t Rn = ((ir>>8)&0xF);

   850                                 sh4r.t = sh4r.r[Rn] >> 31;

   851                                 sh4r.r[Rn] <<= 1;

   852                                 }

   853                                 break;

   854                             default:

   855                                 UNDEF();

   856                                 break;

   857                         }

   858                         break;

   859                     case 0x1:

   860                         switch( (ir&0xF0) >> 4 ) {

   861                             case 0x0:

   862                                 { /* SHLR Rn */

   863                                 uint32_t Rn = ((ir>>8)&0xF);

   864                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;

   865                                 }

   866                                 break;

   867                             case 0x1:

   868                                 { /* CMP/PZ Rn */

   869                                 uint32_t Rn = ((ir>>8)&0xF);

   870                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );

   871                                 }

   872                                 break;

   873                             case 0x2:

   874                                 { /* SHAR Rn */

   875                                 uint32_t Rn = ((ir>>8)&0xF);

   876                                 sh4r.t = sh4r.r[Rn] & 0x00000001;

   877                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;

   878                                 }

   879                                 break;

   880                             default:

   881                                 UNDEF();

   882                                 break;

   883                         }

   884                         break;

   885                     case 0x2:

   886                         switch( (ir&0xF0) >> 4 ) {

   887                             case 0x0:

   888                                 { /* STS.L MACH, @-Rn */

   889                                 uint32_t Rn = ((ir>>8)&0xF);

   890                                 CHECKWALIGN32( sh4r.r[Rn] );

   891                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );

   892                                 sh4r.r[Rn] -= 4;

   893                                 }

   894                                 break;

   895                             case 0x1:

   896                                 { /* STS.L MACL, @-Rn */

   897                                 uint32_t Rn = ((ir>>8)&0xF);

   898                                 CHECKWALIGN32( sh4r.r[Rn] );

   899                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );

   900                                 sh4r.r[Rn] -= 4;

   901                                 }

   902                                 break;

   903                             case 0x2:

   904                                 { /* STS.L PR, @-Rn */

   905                                 uint32_t Rn = ((ir>>8)&0xF);

   906                                 CHECKWALIGN32( sh4r.r[Rn] );

   907                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );

   908                                 sh4r.r[Rn] -= 4;

   909                                 }

   910                                 break;

   911                             case 0x3:

   912                                 { /* STC.L SGR, @-Rn */

   913                                 uint32_t Rn = ((ir>>8)&0xF);

   914                                 CHECKPRIV();

   915                                 CHECKWALIGN32( sh4r.r[Rn] );

   916                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );

   917                                 sh4r.r[Rn] -= 4;

   918                                 }

   919                                 break;

   920                             case 0x5:

   921                                 { /* STS.L FPUL, @-Rn */

   922                                 uint32_t Rn = ((ir>>8)&0xF);

   923                                 CHECKFPUEN();

   924                                 CHECKWALIGN32( sh4r.r[Rn] );

   925                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );

   926                                 sh4r.r[Rn] -= 4;

   927                                 }

   928                                 break;

   929                             case 0x6:

   930                                 { /* STS.L FPSCR, @-Rn */

   931                                 uint32_t Rn = ((ir>>8)&0xF);

   932                                 CHECKFPUEN();

   933                                 CHECKWALIGN32( sh4r.r[Rn] );

   934                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );

   935                                 sh4r.r[Rn] -= 4;

   936                                 }

   937                                 break;

   938                             case 0xF:

   939                                 { /* STC.L DBR, @-Rn */

   940                                 uint32_t Rn = ((ir>>8)&0xF);

   941                                 CHECKPRIV();

   942                                 CHECKWALIGN32( sh4r.r[Rn] );

   943                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );

   944                                 sh4r.r[Rn] -= 4;

   945                                 }

   946                                 break;

   947                             default:

   948                                 UNDEF();

   949                                 break;

   950                         }

   951                         break;

   952                     case 0x3:

   953                         switch( (ir&0x80) >> 7 ) {

   954                             case 0x0:

   955                                 switch( (ir&0x70) >> 4 ) {

   956                                     case 0x0:

   957                                         { /* STC.L SR, @-Rn */

   958                                         uint32_t Rn = ((ir>>8)&0xF);

   959                                         CHECKPRIV();

   960                                         CHECKWALIGN32( sh4r.r[Rn] );

   961                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );

   962                                         sh4r.r[Rn] -= 4;

   963                                         }

   964                                         break;

   965                                     case 0x1:

   966                                         { /* STC.L GBR, @-Rn */

   967                                         uint32_t Rn = ((ir>>8)&0xF);

   968                                         CHECKWALIGN32( sh4r.r[Rn] );

   969                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );

   970                                         sh4r.r[Rn] -= 4;

   971                                         }

   972                                         break;

   973                                     case 0x2:

   974                                         { /* STC.L VBR, @-Rn */

   975                                         uint32_t Rn = ((ir>>8)&0xF);

   976                                         CHECKPRIV();

   977                                         CHECKWALIGN32( sh4r.r[Rn] );

   978                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );

   979                                         sh4r.r[Rn] -= 4;

   980                                         }

   981                                         break;

   982                                     case 0x3:

   983                                         { /* STC.L SSR, @-Rn */

   984                                         uint32_t Rn = ((ir>>8)&0xF);

   985                                         CHECKPRIV();

   986                                         CHECKWALIGN32( sh4r.r[Rn] );

   987                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );

   988                                         sh4r.r[Rn] -= 4;

   989                                         }

   990                                         break;

   991                                     case 0x4:

   992                                         { /* STC.L SPC, @-Rn */

   993                                         uint32_t Rn = ((ir>>8)&0xF);

   994                                         CHECKPRIV();

   995                                         CHECKWALIGN32( sh4r.r[Rn] );

   996                                         MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );

   997                                         sh4r.r[Rn] -= 4;

   998                                         }

   999                                         break;

  1000                                     default:

  1001                                         UNDEF();

  1002                                         break;

  1003                                 }

  1004                                 break;

  1005                             case 0x1:

  1006                                 { /* STC.L Rm_BANK, @-Rn */

  1007                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

  1008                                 CHECKPRIV();

  1009                                 CHECKWALIGN32( sh4r.r[Rn] );

  1010                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );

  1011                                 sh4r.r[Rn] -= 4;

  1012                                 }

  1013                                 break;

  1014                         }

  1015                         break;

  1016                     case 0x4:

  1017                         switch( (ir&0xF0) >> 4 ) {

  1018                             case 0x0:

  1019                                 { /* ROTL Rn */

  1020                                 uint32_t Rn = ((ir>>8)&0xF);

  1021                                 sh4r.t = sh4r.r[Rn] >> 31;

  1022                                 sh4r.r[Rn] <<= 1;

  1023                                 sh4r.r[Rn] |= sh4r.t;

  1024                                 }

  1025                                 break;

  1026                             case 0x2:

  1027                                 { /* ROTCL Rn */

  1028                                 uint32_t Rn = ((ir>>8)&0xF);

  1029                                 tmp = sh4r.r[Rn] >> 31;

  1030                                 sh4r.r[Rn] <<= 1;

  1031                                 sh4r.r[Rn] |= sh4r.t;

  1032                                 sh4r.t = tmp;

  1033                                 }

  1034                                 break;

  1035                             default:

  1036                                 UNDEF();

  1037                                 break;

  1038                         }

  1039                         break;

  1040                     case 0x5:

  1041                         switch( (ir&0xF0) >> 4 ) {

  1042                             case 0x0:

  1043                                 { /* ROTR Rn */

  1044                                 uint32_t Rn = ((ir>>8)&0xF);

  1045                                 sh4r.t = sh4r.r[Rn] & 0x00000001;

  1046                                 sh4r.r[Rn] >>= 1;

  1047                                 sh4r.r[Rn] |= (sh4r.t << 31);

  1048                                 }

  1049                                 break;

  1050                             case 0x1:

  1051                                 { /* CMP/PL Rn */

  1052                                 uint32_t Rn = ((ir>>8)&0xF);

  1053                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );

  1054                                 }

  1055                                 break;

  1056                             case 0x2:

  1057                                 { /* ROTCR Rn */

  1058                                 uint32_t Rn = ((ir>>8)&0xF);

  1059                                 tmp = sh4r.r[Rn] & 0x00000001;

  1060                                 sh4r.r[Rn] >>= 1;

  1061                                 sh4r.r[Rn] |= (sh4r.t << 31 );

  1062                                 sh4r.t = tmp;

  1063                                 }

  1064                                 break;

  1065                             default:

  1066                                 UNDEF();

  1067                                 break;

  1068                         }

  1069                         break;

  1070                     case 0x6:

  1071                         switch( (ir&0xF0) >> 4 ) {

  1072                             case 0x0:

  1073                                 { /* LDS.L @Rm+, MACH */

  1074                                 uint32_t Rm = ((ir>>8)&0xF);

  1075                                 CHECKRALIGN32( sh4r.r[Rm] );

  1076                                 MEM_READ_LONG(sh4r.r[Rm], tmp);

  1077                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

  1078                             	(((uint64_t)tmp)<<32);

  1079                                 sh4r.r[Rm] += 4;

  1080                                 }

  1081                                 break;

  1082                             case 0x1:

  1083                                 { /* LDS.L @Rm+, MACL */

  1084                                 uint32_t Rm = ((ir>>8)&0xF);

  1085                                 CHECKRALIGN32( sh4r.r[Rm] );

  1086                                 MEM_READ_LONG(sh4r.r[Rm], tmp);

  1087                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1088                                            (uint64_t)((uint32_t)tmp);

  1089                                 sh4r.r[Rm] += 4;

  1090                                 }

  1091                                 break;

  1092                             case 0x2:

  1093                                 { /* LDS.L @Rm+, PR */

  1094                                 uint32_t Rm = ((ir>>8)&0xF);

  1095                                 CHECKRALIGN32( sh4r.r[Rm] );

  1096                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );

  1097                                 sh4r.r[Rm] += 4;

  1098                                 }

  1099                                 break;

  1100                             case 0x3:

  1101                                 { /* LDC.L @Rm+, SGR */

  1102                                 uint32_t Rm = ((ir>>8)&0xF);

  1103                                 CHECKPRIV();

  1104                                 CHECKRALIGN32( sh4r.r[Rm] );

  1105                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);

  1106                                 sh4r.r[Rm] +=4;

  1107                                 }

  1108                                 break;

  1109                             case 0x5:

  1110                                 { /* LDS.L @Rm+, FPUL */

  1111                                 uint32_t Rm = ((ir>>8)&0xF);

  1112                                 CHECKFPUEN();

  1113                                 CHECKRALIGN32( sh4r.r[Rm] );

  1114                                 MEM_READ_LONG(sh4r.r[Rm], FPULi);

  1115                                 sh4r.r[Rm] +=4;

  1116                                 }

  1117                                 break;

  1118                             case 0x6:

  1119                                 { /* LDS.L @Rm+, FPSCR */

  1120                                 uint32_t Rm = ((ir>>8)&0xF);

  1121                                 CHECKFPUEN();

  1122                                 CHECKRALIGN32( sh4r.r[Rm] );

  1123                                 MEM_READ_LONG(sh4r.r[Rm], tmp);

  1124                                 sh4r.r[Rm] +=4;

  1125                                 sh4_write_fpscr( tmp );

  1126                                 }

  1127                                 break;

  1128                             case 0xF:

  1129                                 { /* LDC.L @Rm+, DBR */

  1130                                 uint32_t Rm = ((ir>>8)&0xF);

  1131                                 CHECKPRIV();

  1132                                 CHECKRALIGN32( sh4r.r[Rm] );

  1133                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);

  1134                                 sh4r.r[Rm] +=4;

  1135                                 }

  1136                                 break;

  1137                             default:

  1138                                 UNDEF();

  1139                                 break;

  1140                         }

  1141                         break;

  1142                     case 0x7:

  1143                         switch( (ir&0x80) >> 7 ) {

  1144                             case 0x0:

  1145                                 switch( (ir&0x70) >> 4 ) {

  1146                                     case 0x0:

  1147                                         { /* LDC.L @Rm+, SR */

  1148                                         uint32_t Rm = ((ir>>8)&0xF);

  1149                                         CHECKSLOTILLEGAL();

  1150                                         CHECKPRIV();

  1151                                         CHECKWALIGN32( sh4r.r[Rm] );

  1152                                         MEM_READ_LONG(sh4r.r[Rm], tmp);

  1153                                         sh4_write_sr( tmp );

  1154                                         sh4r.r[Rm] +=4;

  1155                                         }

  1156                                         break;

  1157                                     case 0x1:

  1158                                         { /* LDC.L @Rm+, GBR */

  1159                                         uint32_t Rm = ((ir>>8)&0xF);

  1160                                         CHECKRALIGN32( sh4r.r[Rm] );

  1161                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);

  1162                                         sh4r.r[Rm] +=4;

  1163                                         }

  1164                                         break;

  1165                                     case 0x2:

  1166                                         { /* LDC.L @Rm+, VBR */

  1167                                         uint32_t Rm = ((ir>>8)&0xF);

  1168                                         CHECKPRIV();

  1169                                         CHECKRALIGN32( sh4r.r[Rm] );

  1170                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);

  1171                                         sh4r.r[Rm] +=4;

  1172                                         }

  1173                                         break;

  1174                                     case 0x3:

  1175                                         { /* LDC.L @Rm+, SSR */

  1176                                         uint32_t Rm = ((ir>>8)&0xF);

  1177                                         CHECKPRIV();

  1178                                         CHECKRALIGN32( sh4r.r[Rm] );

  1179                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);

  1180                                         sh4r.r[Rm] +=4;

  1181                                         }

  1182                                         break;

  1183                                     case 0x4:

  1184                                         { /* LDC.L @Rm+, SPC */

  1185                                         uint32_t Rm = ((ir>>8)&0xF);

  1186                                         CHECKPRIV();

  1187                                         CHECKRALIGN32( sh4r.r[Rm] );

  1188                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);

  1189                                         sh4r.r[Rm] +=4;

  1190                                         }

  1191                                         break;

  1192                                     default:

  1193                                         UNDEF();

  1194                                         break;

  1195                                 }

  1196                                 break;

  1197                             case 0x1:

  1198                                 { /* LDC.L @Rm+, Rn_BANK */

  1199                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1200                                 CHECKPRIV();

  1201                                 CHECKRALIGN32( sh4r.r[Rm] );

  1202                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );

  1203                                 sh4r.r[Rm] += 4;

  1204                                 }

  1205                                 break;

  1206                         }

  1207                         break;

  1208                     case 0x8:

  1209                         switch( (ir&0xF0) >> 4 ) {

  1210                             case 0x0:

  1211                                 { /* SHLL2 Rn */

  1212                                 uint32_t Rn = ((ir>>8)&0xF);

  1213                                 sh4r.r[Rn] <<= 2;

  1214                                 }

  1215                                 break;

  1216                             case 0x1:

  1217                                 { /* SHLL8 Rn */

  1218                                 uint32_t Rn = ((ir>>8)&0xF);

  1219                                 sh4r.r[Rn] <<= 8;

  1220                                 }

  1221                                 break;

  1222                             case 0x2:

  1223                                 { /* SHLL16 Rn */

  1224                                 uint32_t Rn = ((ir>>8)&0xF);

  1225                                 sh4r.r[Rn] <<= 16;

  1226                                 }

  1227                                 break;

  1228                             default:

  1229                                 UNDEF();

  1230                                 break;

  1231                         }

  1232                         break;

  1233                     case 0x9:

  1234                         switch( (ir&0xF0) >> 4 ) {

  1235                             case 0x0:

  1236                                 { /* SHLR2 Rn */

  1237                                 uint32_t Rn = ((ir>>8)&0xF);

  1238                                 sh4r.r[Rn] >>= 2;

  1239                                 }

  1240                                 break;

  1241                             case 0x1:

  1242                                 { /* SHLR8 Rn */

  1243                                 uint32_t Rn = ((ir>>8)&0xF);

  1244                                 sh4r.r[Rn] >>= 8;

  1245                                 }

  1246                                 break;

  1247                             case 0x2:

  1248                                 { /* SHLR16 Rn */

  1249                                 uint32_t Rn = ((ir>>8)&0xF);

  1250                                 sh4r.r[Rn] >>= 16;

  1251                                 }

  1252                                 break;

  1253                             default:

  1254                                 UNDEF();

  1255                                 break;

  1256                         }

  1257                         break;

  1258                     case 0xA:

  1259                         switch( (ir&0xF0) >> 4 ) {

  1260                             case 0x0:

  1261                                 { /* LDS Rm, MACH */

  1262                                 uint32_t Rm = ((ir>>8)&0xF);

  1263                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

  1264                                            (((uint64_t)sh4r.r[Rm])<<32);

  1265                                 }

  1266                                 break;

  1267                             case 0x1:

  1268                                 { /* LDS Rm, MACL */

  1269                                 uint32_t Rm = ((ir>>8)&0xF);

  1270                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1271                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));

  1272                                 }

  1273                                 break;

  1274                             case 0x2:

  1275                                 { /* LDS Rm, PR */

  1276                                 uint32_t Rm = ((ir>>8)&0xF);

  1277                                 sh4r.pr = sh4r.r[Rm];

  1278                                 }

  1279                                 break;

  1280                             case 0x3:

  1281                                 { /* LDC Rm, SGR */

  1282                                 uint32_t Rm = ((ir>>8)&0xF);

  1283                                 CHECKPRIV();

  1284                                 sh4r.sgr = sh4r.r[Rm];

  1285                                 }

  1286                                 break;

  1287                             case 0x5:

  1288                                 { /* LDS Rm, FPUL */

  1289                                 uint32_t Rm = ((ir>>8)&0xF);

  1290                                 CHECKFPUEN();

  1291                                 FPULi = sh4r.r[Rm];

  1292                                 }

  1293                                 break;

  1294                             case 0x6:

  1295                                 { /* LDS Rm, FPSCR */

  1296                                 uint32_t Rm = ((ir>>8)&0xF);

  1297                                 CHECKFPUEN();

  1298                                 sh4_write_fpscr( sh4r.r[Rm] );

  1299                                 }

  1300                                 break;

  1301                             case 0xF:

  1302                                 { /* LDC Rm, DBR */

  1303                                 uint32_t Rm = ((ir>>8)&0xF);

  1304                                 CHECKPRIV();

  1305                                 sh4r.dbr = sh4r.r[Rm];

  1306                                 }

  1307                                 break;

  1308                             default:

  1309                                 UNDEF();

  1310                                 break;

  1311                         }

  1312                         break;

  1313                     case 0xB:

  1314                         switch( (ir&0xF0) >> 4 ) {

  1315                             case 0x0:

  1316                                 { /* JSR @Rn */

  1317                                 uint32_t Rn = ((ir>>8)&0xF);

  1318                                 CHECKDEST( sh4r.r[Rn] );

  1319                                 CHECKSLOTILLEGAL();

  1320                                 sh4r.in_delay_slot = 1;

  1321                                 sh4r.pc = sh4r.new_pc;

  1322                                 sh4r.new_pc = sh4r.r[Rn];

  1323                                 sh4r.pr = pc + 4;

  1324                                 TRACE_CALL( pc, sh4r.new_pc );

  1325                                 return TRUE;

  1326                                 }

  1327                                 break;

  1328                             case 0x1:

  1329                                 { /* TAS.B @Rn */

  1330                                 uint32_t Rn = ((ir>>8)&0xF);

  1331                                 MEM_READ_BYTE( sh4r.r[Rn], tmp );

  1332                                 sh4r.t = ( tmp == 0 ? 1 : 0 );

  1333                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );

  1334                                 }

  1335                                 break;

  1336                             case 0x2:

  1337                                 { /* JMP @Rn */

  1338                                 uint32_t Rn = ((ir>>8)&0xF);

  1339                                 CHECKDEST( sh4r.r[Rn] );

  1340                                 CHECKSLOTILLEGAL();

  1341                                 sh4r.in_delay_slot = 1;

  1342                                 sh4r.pc = sh4r.new_pc;

  1343                                 sh4r.new_pc = sh4r.r[Rn];

  1344                                 return TRUE;

  1345                                 }

  1346                                 break;

  1347                             default:

  1348                                 UNDEF();

  1349                                 break;

  1350                         }

  1351                         break;

  1352                     case 0xC:

  1353                         { /* SHAD Rm, Rn */

  1354                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1355                         tmp = sh4r.r[Rm];

  1356                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

  1357                         else if( (tmp & 0x1F) == 0 )

  1358                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;

  1359                         else

  1360                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);

  1361                         }

  1362                         break;

  1363                     case 0xD:

  1364                         { /* SHLD Rm, Rn */

  1365                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1366                         tmp = sh4r.r[Rm];

  1367                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

  1368                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;

  1369                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);

  1370                         }

  1371                         break;

  1372                     case 0xE:

  1373                         switch( (ir&0x80) >> 7 ) {

  1374                             case 0x0:

  1375                                 switch( (ir&0x70) >> 4 ) {

  1376                                     case 0x0:

  1377                                         { /* LDC Rm, SR */

  1378                                         uint32_t Rm = ((ir>>8)&0xF);

  1379                                         CHECKSLOTILLEGAL();

  1380                                         CHECKPRIV();

  1381                                         sh4_write_sr( sh4r.r[Rm] );

  1382                                         }

  1383                                         break;

  1384                                     case 0x1:

  1385                                         { /* LDC Rm, GBR */

  1386                                         uint32_t Rm = ((ir>>8)&0xF);

  1387                                         sh4r.gbr = sh4r.r[Rm];

  1388                                         }

  1389                                         break;

  1390                                     case 0x2:

  1391                                         { /* LDC Rm, VBR */

  1392                                         uint32_t Rm = ((ir>>8)&0xF);

  1393                                         CHECKPRIV();

  1394                                         sh4r.vbr = sh4r.r[Rm];

  1395                                         }

  1396                                         break;

  1397                                     case 0x3:

  1398                                         { /* LDC Rm, SSR */

  1399                                         uint32_t Rm = ((ir>>8)&0xF);

  1400                                         CHECKPRIV();

  1401                                         sh4r.ssr = sh4r.r[Rm];

  1402                                         }

  1403                                         break;

  1404                                     case 0x4:

  1405                                         { /* LDC Rm, SPC */

  1406                                         uint32_t Rm = ((ir>>8)&0xF);

  1407                                         CHECKPRIV();

  1408                                         sh4r.spc = sh4r.r[Rm];

  1409                                         }

  1410                                         break;

  1411                                     default:

  1412                                         UNDEF();

  1413                                         break;

  1414                                 }

  1415                                 break;

  1416                             case 0x1:

  1417                                 { /* LDC Rm, Rn_BANK */

  1418                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1419                                 CHECKPRIV();

  1420                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];

  1421                                 }

  1422                                 break;

  1423                         }

  1424                         break;

  1425                     case 0xF:

  1426                         { /* MAC.W @Rm+, @Rn+ */

  1427                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1428                         int32_t stmp;

  1429                         if( Rm == Rn ) {

  1430                     	CHECKRALIGN16(sh4r.r[Rn]);

  1431                     	MEM_READ_WORD( sh4r.r[Rn], tmp );

  1432                     	stmp = SIGNEXT16(tmp);

  1433                     	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );

  1434                     	stmp *= SIGNEXT16(tmp);

  1435                     	sh4r.r[Rn] += 4;

  1436                         } else {

  1437                     	CHECKRALIGN16( sh4r.r[Rn] );

  1438                     	CHECKRALIGN16( sh4r.r[Rm] );

  1439                     	MEM_READ_WORD(sh4r.r[Rn], tmp);

  1440                     	stmp = SIGNEXT16(tmp);

  1441                     	MEM_READ_WORD(sh4r.r[Rm], tmp);

  1442                     	stmp = stmp * SIGNEXT16(tmp);

  1443                     	sh4r.r[Rn] += 2;

  1444                     	sh4r.r[Rm] += 2;

  1445                         }

  1446                         if( sh4r.s ) {

  1447                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;

  1448                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {

  1449                     	    sh4r.mac = 0x000000017FFFFFFFLL;

  1450                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {

  1451                     	    sh4r.mac = 0x0000000180000000LL;

  1452                     	} else {

  1453                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1454                     		((uint32_t)(sh4r.mac + stmp));

  1455                     	}

  1456                         } else {

  1457                     	sh4r.mac += SIGNEXT32(stmp);

  1458                         }

  1459                         }

  1460                         break;

  1461                 }

  1462                 break;

  1463             case 0x5:

  1464                 { /* MOV.L @(disp, Rm), Rn */

  1465                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

  1466                 tmp = sh4r.r[Rm] + disp;

  1467                 CHECKRALIGN32( tmp );

  1468                 MEM_READ_LONG( tmp, sh4r.r[Rn] );

  1469                 }

  1470                 break;

  1471             case 0x6:

  1472                 switch( ir&0xF ) {

  1473                     case 0x0:

  1474                         { /* MOV.B @Rm, Rn */

  1475                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1476                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] );

  1477                         }

  1478                         break;

  1479                     case 0x1:

  1480                         { /* MOV.W @Rm, Rn */

  1481                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1482                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] );

  1483                         }

  1484                         break;

  1485                     case 0x2:

  1486                         { /* MOV.L @Rm, Rn */

  1487                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1488                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] );

  1489                         }

  1490                         break;

  1491                     case 0x3:

  1492                         { /* MOV Rm, Rn */

  1493                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1494                         sh4r.r[Rn] = sh4r.r[Rm];

  1495                         }

  1496                         break;

  1497                     case 0x4:

  1498                         { /* MOV.B @Rm+, Rn */

  1499                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1500                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++;

  1501                         }

  1502                         break;

  1503                     case 0x5:

  1504                         { /* MOV.W @Rm+, Rn */

  1505                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1506                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2;

  1507                         }

  1508                         break;

  1509                     case 0x6:

  1510                         { /* MOV.L @Rm+, Rn */

  1511                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1512                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4;

  1513                         }

  1514                         break;

  1515                     case 0x7:

  1516                         { /* NOT Rm, Rn */

  1517                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1518                         sh4r.r[Rn] = ~sh4r.r[Rm];

  1519                         }

  1520                         break;

  1521                     case 0x8:

  1522                         { /* SWAP.B Rm, Rn */

  1523                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1524                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);

  1525                         }

  1526                         break;

  1527                     case 0x9:

  1528                         { /* SWAP.W Rm, Rn */

  1529                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1530                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);

  1531                         }

  1532                         break;

  1533                     case 0xA:

  1534                         { /* NEGC Rm, Rn */

  1535                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1536                         tmp = 0 - sh4r.r[Rm];

  1537                         sh4r.r[Rn] = tmp - sh4r.t;

  1538                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );

  1539                         }

  1540                         break;

  1541                     case 0xB:

  1542                         { /* NEG Rm, Rn */

  1543                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1544                         sh4r.r[Rn] = 0 - sh4r.r[Rm];

  1545                         }

  1546                         break;

  1547                     case 0xC:

  1548                         { /* EXTU.B Rm, Rn */

  1549                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1550                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;

  1551                         }

  1552                         break;

  1553                     case 0xD:

  1554                         { /* EXTU.W Rm, Rn */

  1555                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1556                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;

  1557                         }

  1558                         break;

  1559                     case 0xE:

  1560                         { /* EXTS.B Rm, Rn */

  1561                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1562                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );

  1563                         }

  1564                         break;

  1565                     case 0xF:

  1566                         { /* EXTS.W Rm, Rn */

  1567                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1568                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );

  1569                         }

  1570                         break;

  1571                 }

  1572                 break;

  1573             case 0x7:

  1574                 { /* ADD #imm, Rn */

  1575                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1576                 sh4r.r[Rn] += imm;

  1577                 }

  1578                 break;

  1579             case 0x8:

  1580                 switch( (ir&0xF00) >> 8 ) {

  1581                     case 0x0:

  1582                         { /* MOV.B R0, @(disp, Rn) */

  1583                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1584                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );

  1585                         }

  1586                         break;

  1587                     case 0x1:

  1588                         { /* MOV.W R0, @(disp, Rn) */

  1589                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1590                         tmp = sh4r.r[Rn] + disp;

  1591                         CHECKWALIGN16( tmp );

  1592                         MEM_WRITE_WORD( tmp, R0 );

  1593                         }

  1594                         break;

  1595                     case 0x4:

  1596                         { /* MOV.B @(disp, Rm), R0 */

  1597                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1598                         MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 );

  1599                         }

  1600                         break;

  1601                     case 0x5:

  1602                         { /* MOV.W @(disp, Rm), R0 */

  1603                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1604                         tmp = sh4r.r[Rm] + disp;

  1605                         CHECKRALIGN16( tmp );

  1606                         MEM_READ_WORD( tmp, R0 );

  1607                         }

  1608                         break;

  1609                     case 0x8:

  1610                         { /* CMP/EQ #imm, R0 */

  1611                         int32_t imm = SIGNEXT8(ir&0xFF);

  1612                         sh4r.t = ( R0 == imm ? 1 : 0 );

  1613                         }

  1614                         break;

  1615                     case 0x9:

  1616                         { /* BT disp */

  1617                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1618                         CHECKSLOTILLEGAL();

  1619                         if( sh4r.t ) {

  1620                             CHECKDEST( sh4r.pc + disp + 4 )

  1621                             sh4r.pc += disp + 4;

  1622                             sh4r.new_pc = sh4r.pc + 2;

  1623                             return TRUE;

  1624                         }

  1625                         }

  1626                         break;

  1627                     case 0xB:

  1628                         { /* BF disp */

  1629                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1630                         CHECKSLOTILLEGAL();

  1631                         if( !sh4r.t ) {

  1632                             CHECKDEST( sh4r.pc + disp + 4 )

  1633                             sh4r.pc += disp + 4;

  1634                             sh4r.new_pc = sh4r.pc + 2;

  1635                             return TRUE;

  1636                         }

  1637                         }

  1638                         break;

  1639                     case 0xD:

  1640                         { /* BT/S disp */

  1641                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1642                         CHECKSLOTILLEGAL();

  1643                         if( sh4r.t ) {

  1644                             CHECKDEST( sh4r.pc + disp + 4 )

  1645                             sh4r.in_delay_slot = 1;

  1646                             sh4r.pc = sh4r.new_pc;

  1647                             sh4r.new_pc = pc + disp + 4;

  1648                             sh4r.in_delay_slot = 1;

  1649                             return TRUE;

  1650                         }

  1651                         }

  1652                         break;

  1653                     case 0xF:

  1654                         { /* BF/S disp */

  1655                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1656                         CHECKSLOTILLEGAL();

  1657                         if( !sh4r.t ) {

  1658                             CHECKDEST( sh4r.pc + disp + 4 )

  1659                             sh4r.in_delay_slot = 1;

  1660                             sh4r.pc = sh4r.new_pc;

  1661                             sh4r.new_pc = pc + disp + 4;

  1662                             return TRUE;

  1663                         }

  1664                         }

  1665                         break;

  1666                     default:

  1667                         UNDEF();

  1668                         break;

  1669                 }

  1670                 break;

  1671             case 0x9:

  1672                 { /* MOV.W @(disp, PC), Rn */

  1673                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;

  1674                 CHECKSLOTILLEGAL();

  1675                 tmp = pc + 4 + disp;

  1676                 MEM_READ_WORD( tmp, sh4r.r[Rn] );

  1677                 }

  1678                 break;

  1679             case 0xA:

  1680                 { /* BRA disp */

  1681                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1682                 CHECKSLOTILLEGAL();

  1683                 CHECKDEST( sh4r.pc + disp + 4 );

  1684                 sh4r.in_delay_slot = 1;

  1685                 sh4r.pc = sh4r.new_pc;

  1686                 sh4r.new_pc = pc + 4 + disp;

  1687                 return TRUE;

  1688                 }

  1689                 break;

  1690             case 0xB:

  1691                 { /* BSR disp */

  1692                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1693                 CHECKDEST( sh4r.pc + disp + 4 );

  1694                 CHECKSLOTILLEGAL();

  1695                 sh4r.in_delay_slot = 1;

  1696                 sh4r.pr = pc + 4;

  1697                 sh4r.pc = sh4r.new_pc;

  1698                 sh4r.new_pc = pc + 4 + disp;

  1699                 TRACE_CALL( pc, sh4r.new_pc );

  1700                 return TRUE;

  1701                 }

  1702                 break;

  1703             case 0xC:

  1704                 switch( (ir&0xF00) >> 8 ) {

  1705                     case 0x0:

  1706                         { /* MOV.B R0, @(disp, GBR) */

  1707                         uint32_t disp = (ir&0xFF);

  1708                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );

  1709                         }

  1710                         break;

  1711                     case 0x1:

  1712                         { /* MOV.W R0, @(disp, GBR) */

  1713                         uint32_t disp = (ir&0xFF)<<1;

  1714                         tmp = sh4r.gbr + disp;

  1715                         CHECKWALIGN16( tmp );

  1716                         MEM_WRITE_WORD( tmp, R0 );

  1717                         }

  1718                         break;

  1719                     case 0x2:

  1720                         { /* MOV.L R0, @(disp, GBR) */

  1721                         uint32_t disp = (ir&0xFF)<<2;

  1722                         tmp = sh4r.gbr + disp;

  1723                         CHECKWALIGN32( tmp );

  1724                         MEM_WRITE_LONG( tmp, R0 );

  1725                         }

  1726                         break;

  1727                     case 0x3:

  1728                         { /* TRAPA #imm */

  1729                         uint32_t imm = (ir&0xFF);

  1730                         CHECKSLOTILLEGAL();

  1731                         sh4r.pc += 2;

  1732                         sh4_raise_trap( imm );

  1733                         return TRUE;

  1734                         }

  1735                         break;

  1736                     case 0x4:

  1737                         { /* MOV.B @(disp, GBR), R0 */

  1738                         uint32_t disp = (ir&0xFF);

  1739                         MEM_READ_BYTE( sh4r.gbr + disp, R0 );

  1740                         }

  1741                         break;

  1742                     case 0x5:

  1743                         { /* MOV.W @(disp, GBR), R0 */

  1744                         uint32_t disp = (ir&0xFF)<<1;

  1745                         tmp = sh4r.gbr + disp;

  1746                         CHECKRALIGN16( tmp );

  1747                         MEM_READ_WORD( tmp, R0 );

  1748                         }

  1749                         break;

  1750                     case 0x6:

  1751                         { /* MOV.L @(disp, GBR), R0 */

  1752                         uint32_t disp = (ir&0xFF)<<2;

  1753                         tmp = sh4r.gbr + disp;

  1754                         CHECKRALIGN32( tmp );

  1755                         MEM_READ_LONG( tmp, R0 );

  1756                         }

  1757                         break;

  1758                     case 0x7:

  1759                         { /* MOVA @(disp, PC), R0 */

  1760                         uint32_t disp = (ir&0xFF)<<2;

  1761                         CHECKSLOTILLEGAL();

  1762                         R0 = (pc&0xFFFFFFFC) + disp + 4;

  1763                         }

  1764                         break;

  1765                     case 0x8:

  1766                         { /* TST #imm, R0 */

  1767                         uint32_t imm = (ir&0xFF);

  1768                         sh4r.t = (R0 & imm ? 0 : 1);

  1769                         }

  1770                         break;

  1771                     case 0x9:

  1772                         { /* AND #imm, R0 */

  1773                         uint32_t imm = (ir&0xFF);

  1774                         R0 &= imm;

  1775                         }

  1776                         break;

  1777                     case 0xA:

  1778                         { /* XOR #imm, R0 */

  1779                         uint32_t imm = (ir&0xFF);

  1780                         R0 ^= imm;

  1781                         }

  1782                         break;

  1783                     case 0xB:

  1784                         { /* OR #imm, R0 */

  1785                         uint32_t imm = (ir&0xFF);

  1786                         R0 |= imm;

  1787                         }

  1788                         break;

  1789                     case 0xC:

  1790                         { /* TST.B #imm, @(R0, GBR) */

  1791                         uint32_t imm = (ir&0xFF);

  1792                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 );

  1793                         }

  1794                         break;

  1795                     case 0xD:

  1796                         { /* AND.B #imm, @(R0, GBR) */

  1797                         uint32_t imm = (ir&0xFF);

  1798                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp );

  1799                         }

  1800                         break;

  1801                     case 0xE:

  1802                         { /* XOR.B #imm, @(R0, GBR) */

  1803                         uint32_t imm = (ir&0xFF);

  1804                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp );

  1805                         }

  1806                         break;

  1807                     case 0xF:

  1808                         { /* OR.B #imm, @(R0, GBR) */

  1809                         uint32_t imm = (ir&0xFF);

  1810                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp );

  1811                         }

  1812                         break;

  1813                 }

  1814                 break;

  1815             case 0xD:

  1816                 { /* MOV.L @(disp, PC), Rn */

  1817                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;

  1818                 CHECKSLOTILLEGAL();

  1819                 tmp = (pc&0xFFFFFFFC) + disp + 4;

  1820                 MEM_READ_LONG( tmp, sh4r.r[Rn] );

  1821                 }

  1822                 break;

  1823             case 0xE:

  1824                 { /* MOV #imm, Rn */

  1825                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1826                 sh4r.r[Rn] = imm;

  1827                 }

  1828                 break;

  1829             case 0xF:

  1830                 switch( ir&0xF ) {

  1831                     case 0x0:

  1832                         { /* FADD FRm, FRn */

  1833                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1834                         CHECKFPUEN();

  1835                         if( IS_FPU_DOUBLEPREC() ) {

  1836                     	DR(FRn) += DR(FRm);

  1837                         } else {

  1838                     	FR(FRn) += FR(FRm);

  1839                         }

  1840                         }

  1841                         break;

  1842                     case 0x1:

  1843                         { /* FSUB FRm, FRn */

  1844                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1845                         CHECKFPUEN();

  1846                         if( IS_FPU_DOUBLEPREC() ) {

  1847                     	DR(FRn) -= DR(FRm);

  1848                         } else {

  1849                     	FR(FRn) -= FR(FRm);

  1850                         }

  1851                         }

  1852                         break;

  1853                     case 0x2:

  1854                         { /* FMUL FRm, FRn */

  1855                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1856                         CHECKFPUEN();

  1857                         if( IS_FPU_DOUBLEPREC() ) {

  1858                     	DR(FRn) *= DR(FRm);

  1859                         } else {

  1860                     	FR(FRn) *= FR(FRm);

  1861                         }

  1862                         }

  1863                         break;

  1864                     case 0x3:

  1865                         { /* FDIV FRm, FRn */

  1866                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1867                         CHECKFPUEN();

  1868                         if( IS_FPU_DOUBLEPREC() ) {

  1869                     	DR(FRn) /= DR(FRm);

  1870                         } else {

  1871                     	FR(FRn) /= FR(FRm);

  1872                         }

  1873                         }

  1874                         break;

  1875                     case 0x4:

  1876                         { /* FCMP/EQ FRm, FRn */

  1877                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1878                         CHECKFPUEN();

  1879                         if( IS_FPU_DOUBLEPREC() ) {

  1880                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );

  1881                         } else {

  1882                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );

  1883                         }

  1884                         }

  1885                         break;

  1886                     case 0x5:

  1887                         { /* FCMP/GT FRm, FRn */

  1888                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1889                         CHECKFPUEN();

  1890                         if( IS_FPU_DOUBLEPREC() ) {

  1891                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );

  1892                         } else {

  1893                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );

  1894                         }

  1895                         }

  1896                         break;

  1897                     case 0x6:

  1898                         { /* FMOV @(R0, Rm), FRn */

  1899                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1900                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );

  1901                         }

  1902                         break;

  1903                     case 0x7:

  1904                         { /* FMOV FRm, @(R0, Rn) */

  1905                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1906                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );

  1907                         }

  1908                         break;

  1909                     case 0x8:

  1910                         { /* FMOV @Rm, FRn */

  1911                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1912                         MEM_FP_READ( sh4r.r[Rm], FRn );

  1913                         }

  1914                         break;

  1915                     case 0x9:

  1916                         { /* FMOV @Rm+, FRn */

  1917                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1918                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;

  1919                         }

  1920                         break;

  1921                     case 0xA:

  1922                         { /* FMOV FRm, @Rn */

  1923                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1924                         MEM_FP_WRITE( sh4r.r[Rn], FRm );

  1925                         }

  1926                         break;

  1927                     case 0xB:

  1928                         { /* FMOV FRm, @-Rn */

  1929                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1930                         MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH;

  1931                         }

  1932                         break;

  1933                     case 0xC:

  1934                         { /* FMOV FRm, FRn */

  1935                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1936                         if( IS_FPU_DOUBLESIZE() )

  1937                     	DR(FRn) = DR(FRm);

  1938                         else

  1939                     	FR(FRn) = FR(FRm);

  1940                         }

  1941                         break;

  1942                     case 0xD:

  1943                         switch( (ir&0xF0) >> 4 ) {

  1944                             case 0x0:

  1945                                 { /* FSTS FPUL, FRn */

  1946                                 uint32_t FRn = ((ir>>8)&0xF);

  1947                                 CHECKFPUEN(); FR(FRn) = FPULf;

  1948                                 }

  1949                                 break;

  1950                             case 0x1:

  1951                                 { /* FLDS FRm, FPUL */

  1952                                 uint32_t FRm = ((ir>>8)&0xF);

  1953                                 CHECKFPUEN(); FPULf = FR(FRm);

  1954                                 }

  1955                                 break;

  1956                             case 0x2:

  1957                                 { /* FLOAT FPUL, FRn */

  1958                                 uint32_t FRn = ((ir>>8)&0xF);

  1959                                 CHECKFPUEN();

  1960                                 if( IS_FPU_DOUBLEPREC() ) {

  1961                             	if( FRn&1 ) { // No, really...

  1962                             	    dtmp = (double)FPULi;

  1963                             	    FR(FRn) = *(((float *)&dtmp)+1);

  1964                             	} else {

  1965                             	    DRF(FRn>>1) = (double)FPULi;

  1966                             	}

  1967                                 } else {

  1968                             	FR(FRn) = (float)FPULi;

  1969                                 }

  1970                                 }

  1971                                 break;

  1972                             case 0x3:

  1973                                 { /* FTRC FRm, FPUL */

  1974                                 uint32_t FRm = ((ir>>8)&0xF);

  1975                                 CHECKFPUEN();

  1976                                 if( IS_FPU_DOUBLEPREC() ) {

  1977                             	if( FRm&1 ) {

  1978                             	    dtmp = 0;

  1979                             	    *(((float *)&dtmp)+1) = FR(FRm);

  1980                             	} else {

  1981                             	    dtmp = DRF(FRm>>1);

  1982                             	}

  1983                                     if( dtmp >= MAX_INTF )

  1984                                         FPULi = MAX_INT;

  1985                                     else if( dtmp <= MIN_INTF )

  1986                                         FPULi = MIN_INT;

  1987                                     else

  1988                                         FPULi = (int32_t)dtmp;

  1989                                 } else {

  1990                             	ftmp = FR(FRm);

  1991                             	if( ftmp >= MAX_INTF )

  1992                             	    FPULi = MAX_INT;

  1993                             	else if( ftmp <= MIN_INTF )

  1994                             	    FPULi = MIN_INT;

  1995                             	else

  1996                             	    FPULi = (int32_t)ftmp;

  1997                                 }

  1998                                 }

  1999                                 break;

  2000                             case 0x4:

  2001                                 { /* FNEG FRn */

  2002                                 uint32_t FRn = ((ir>>8)&0xF);

  2003                                 CHECKFPUEN();

  2004                                 if( IS_FPU_DOUBLEPREC() ) {

  2005                             	DR(FRn) = -DR(FRn);

  2006                                 } else {

  2007                                     FR(FRn) = -FR(FRn);

  2008                                 }

  2009                                 }

  2010                                 break;

  2011                             case 0x5:

  2012                                 { /* FABS FRn */

  2013                                 uint32_t FRn = ((ir>>8)&0xF);

  2014                                 CHECKFPUEN();

  2015                                 if( IS_FPU_DOUBLEPREC() ) {

  2016                             	DR(FRn) = fabs(DR(FRn));

  2017                                 } else {

  2018                                     FR(FRn) = fabsf(FR(FRn));

  2019                                 }

  2020                                 }

  2021                                 break;

  2022                             case 0x6:

  2023                                 { /* FSQRT FRn */

  2024                                 uint32_t FRn = ((ir>>8)&0xF);

  2025                                 CHECKFPUEN();

  2026                                 if( IS_FPU_DOUBLEPREC() ) {

  2027                             	DR(FRn) = sqrt(DR(FRn));

  2028                                 } else {

  2029                                     FR(FRn) = sqrtf(FR(FRn));

  2030                                 }

  2031                                 }

  2032                                 break;

  2033                             case 0x7:

  2034                                 { /* FSRRA FRn */

  2035                                 uint32_t FRn = ((ir>>8)&0xF);

  2036                                 CHECKFPUEN();

  2037                                 if( !IS_FPU_DOUBLEPREC() ) {

  2038                             	FR(FRn) = 1.0/sqrtf(FR(FRn));

  2039                                 }

  2040                                 }

  2041                                 break;

  2042                             case 0x8:

  2043                                 { /* FLDI0 FRn */

  2044                                 uint32_t FRn = ((ir>>8)&0xF);

  2045                                 CHECKFPUEN();

  2046                                 if( IS_FPU_DOUBLEPREC() ) {

  2047                             	DR(FRn) = 0.0;

  2048                                 } else {

  2049                                     FR(FRn) = 0.0;

  2050                                 }

  2051                                 }

  2052                                 break;

  2053                             case 0x9:

  2054                                 { /* FLDI1 FRn */

  2055                                 uint32_t FRn = ((ir>>8)&0xF);

  2056                                 CHECKFPUEN();

  2057                                 if( IS_FPU_DOUBLEPREC() ) {

  2058                             	DR(FRn) = 1.0;

  2059                                 } else {

  2060                                     FR(FRn) = 1.0;

  2061                                 }

  2062                                 }

  2063                                 break;

  2064                             case 0xA:

  2065                                 { /* FCNVSD FPUL, FRn */

  2066                                 uint32_t FRn = ((ir>>8)&0xF);

  2067                                 CHECKFPUEN();

  2068                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

  2069                             	DR(FRn) = (double)FPULf;

  2070                                 }

  2071                                 }

  2072                                 break;

  2073                             case 0xB:

  2074                                 { /* FCNVDS FRm, FPUL */

  2075                                 uint32_t FRm = ((ir>>8)&0xF);

  2076                                 CHECKFPUEN();

  2077                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

  2078                             	FPULf = (float)DR(FRm);

  2079                                 }

  2080                                 }

  2081                                 break;

  2082                             case 0xE:

  2083                                 { /* FIPR FVm, FVn */

  2084                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);

  2085                                 CHECKFPUEN();

  2086                                 if( !IS_FPU_DOUBLEPREC() ) {

  2087                                     int tmp2 = FVn<<2;

  2088                                     tmp = FVm<<2;

  2089                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +

  2090                                         FR(tmp+1)*FR(tmp2+1) +

  2091                                         FR(tmp+2)*FR(tmp2+2) +

  2092                                         FR(tmp+3)*FR(tmp2+3);

  2093                                 }

  2094                                 }

  2095                                 break;

  2096                             case 0xF:

  2097                                 switch( (ir&0x100) >> 8 ) {

  2098                                     case 0x0:

  2099                                         { /* FSCA FPUL, FRn */

  2100                                         uint32_t FRn = ((ir>>9)&0x7)<<1;

  2101                                         CHECKFPUEN();

  2102                                         if( !IS_FPU_DOUBLEPREC() ) {

  2103                                     	sh4_fsca( FPULi, &(DRF(FRn>>1)) );

  2104                                     	/*

  2105                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;

  2106                                             FR(FRn) = sinf(angle);

  2107                                             FR((FRn)+1) = cosf(angle);

  2108                                     	*/

  2109                                         }

  2110                                         }

  2111                                         break;

  2112                                     case 0x1:

  2113                                         switch( (ir&0x200) >> 9 ) {

  2114                                             case 0x0:

  2115                                                 { /* FTRV XMTRX, FVn */

  2116                                                 uint32_t FVn = ((ir>>10)&0x3);

  2117                                                 CHECKFPUEN();

  2118                                                 if( !IS_FPU_DOUBLEPREC() ) {

  2119                                             	sh4_ftrv(&(DRF(FVn<<1)) );

  2120                                                 }

  2121                                                 }

  2122                                                 break;

  2123                                             case 0x1:

  2124                                                 switch( (ir&0xC00) >> 10 ) {

  2125                                                     case 0x0:

  2126                                                         { /* FSCHG */

  2127                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;

  2128                                                         }

  2129                                                         break;

  2130                                                     case 0x2:

  2131                                                         { /* FRCHG */

  2132                                                         CHECKFPUEN();

  2133                                                         sh4r.fpscr ^= FPSCR_FR;

  2134                                                         sh4_switch_fr_banks();

  2135                                                         }

  2136                                                         break;

  2137                                                     case 0x3:

  2138                                                         { /* UNDEF */

  2139                                                         UNDEF(ir);

  2140                                                         }

  2141                                                         break;

  2142                                                     default:

  2143                                                         UNDEF();

  2144                                                         break;

  2145                                                 }

  2146                                                 break;

  2147                                         }

  2148                                         break;

  2149                                 }

  2150                                 break;

  2151                             default:

  2152                                 UNDEF();

  2153                                 break;

  2154                         }

  2155                         break;

  2156                     case 0xE:

  2157                         { /* FMAC FR0, FRm, FRn */

  2158                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2159                         CHECKFPUEN();

  2160                         if( IS_FPU_DOUBLEPREC() ) {

  2161                             DR(FRn) += DR(FRm)*DR(0);

  2162                         } else {

  2163                     	FR(FRn) += FR(FRm)*FR(0);

  2164                         }

  2165                         }

  2166                         break;

  2167                     default:

  2168                         UNDEF();

  2169                         break;

  2170                 }

  2171                 break;

  2172         }

  2174     sh4r.pc = sh4r.new_pc;

  2175     sh4r.new_pc += 2;

  2176     sh4r.in_delay_slot = 0;

  2177     return TRUE;

  2178 }