lxdream 0.9.1| filename | test/interrupt.s |
| changeset | 815:866c103d72cd |
| prev | 233:f8333b94f503 |
| author | nkeynes |
| date | Wed Dec 02 10:36:49 2009 +1000 (14 years ago) |
| permissions | -rw-r--r-- |
| last change | Add missing SUBV instruction to the emulation core (translation core is ok), along with test cases. Thanks to D. Jeff Dionne for pointing this out. |
| view | annotate | diff | log | raw |
1 .section .text
2 .include "sh4/inc.s"
4 ! expect_interrupt( int intevt )
5 .global _expect_interrupt
6 _expect_interrupt:
7 stc sr, r3 ! Mask off interrupts
8 mov.l bl_mask, r0
9 or r3, r0
10 ldc r0, sr
11 mova expected_intevt, r0
12 mov.l r4, @r0
13 xor r1, r1
14 mova expected_expevt, r0
15 mov.l r1, @r0
16 mova _interrupt_count, r0
17 mov.l r1, @r0
18 mova _interrupt_pc, r0
19 mov.l r1, @r0
20 ldc r3, sr ! Restore old SR state
21 rts
22 nop
24 .global _expect_exception
25 _expect_exception:
26 stc sr, r3 ! Mask off interrupts
27 mov.l bl_mask, r0
28 or r3, r0
29 ldc r0, sr
30 mova expected_expevt, r0
31 mov.l r4, @r0
32 xor r1, r1
33 mova expected_intevt, r0
34 mov.l r1, @r0
35 mova _interrupt_count, r0
36 mov.l r1, @r0
37 mova _interrupt_pc, r0
38 mov.l r1, @r0
39 ldc r3, sr ! Restore old SR state
40 rts
41 nop
43 .align 4
44 .global _interrupt_count
45 _interrupt_count:
46 .long 0x00000000
47 .global _interrupt_pc
48 _interrupt_pc:
49 .long 0x00000000
50 bl_mask:
51 .long 0x10000000
53 .global _install_interrupt_handler
54 _install_interrupt_handler:
55 stc vbr, r1
56 mova old_vbr, r0
57 mov.l r1, @r0
58 mova __interrupt_handler, r0
59 ldc r0, vbr
60 rts
61 nop
63 .global _remove_interrupt_handler
64 _remove_interrupt_handler:
65 mov.l old_vbr, r1
66 ldc r1, vbr
67 rts
68 nop
69 .align 4
70 old_vbr:
71 .long 0x00000000
72 expected_intevt:
73 .long 0x00000000
74 expected_expevt:
75 .long 0x00000000
78 __interrupt_handler:
79 .skip 0x100
80 general_exception:
81 mov.l handler_stack_ptr_k, r15
82 mov.l @r15, r15
83 mov.l r0, @-r15
84 mov.l r1, @-r15
85 mov.l r2, @-r15
87 mov.l expevt_k, r0
88 mov.l @r0, r1
89 mov.l expected_expevt_k, r2
90 mov.l @r2, r2
91 cmp/eq r1, r2
92 bf general_not_expected
93 bra ex_expected
94 nop
95 general_not_expected:
96 bra ex_dontcare
97 nop
98 nop
99 expevt_k:
100 .long 0xFF000024
101 expected_expevt_k:
102 .long expected_expevt
103 handler_stack_ptr_k:
104 .long handler_stack_ptr
105 .skip 0x2D4 ! Pad up to 0x400
107 tlb_exception:
108 mov.l handler_stack_ptr, r15
109 mov.l r0, @-r15
110 mov.l r1, @-r15
111 mov.l r2, @-r15
113 mov.l expevt1_k, r0
114 mov.l @r0, r1
115 mov.l expected_expevt1_k, r2
116 mov.l @r2, r2
117 cmp/eq r1, r2
118 bf tlb_not_expected
119 bra ex_expected
120 nop
121 tlb_not_expected:
122 bra ex_dontcare
123 nop
124 expevt1_k:
125 .long 0xFF000024
126 expected_expevt1_k:
127 .long expected_expevt
129 .skip 0x1DC ! Pad up to 0x600
131 irq_raised:
132 mov.l handler_stack_ptr, r15
133 mov.l r0, @-r15
134 mov.l r1, @-r15
135 mov.l r2, @-r15
137 mov.l intevt_k, r0
138 mov.l @r0, r1
139 mov.l expected_intevt_k, r2
140 mov.l @r2, r2
141 cmp/eq r1, r2
142 bf ex_dontcare
144 ex_expected:
145 mov.l interrupt_count_k, r0
146 mov.l @r0, r2
147 add #1, r2
148 mov.l r2, @r0
149 stc spc, r2
150 mov.l interrupt_pc_k, r0
151 mov.l r2, @r0
153 ! For most instructions, spc = raising instruction, so add 2 to get the next
154 ! instruction. Exceptions are the slot illegals (need pc+4), and trapa/
155 ! user-break-after-instruction where the pc is already correct
156 mov.l slot_illegal_k, r0
157 cmp/eq r0, r1
158 bt ex_slot_spc
159 mov.l slot_fpu_disable_k, r0
160 cmp/eq r0, r1
161 bt ex_slot_spc
162 mov.l trapa_exc_k, r0
163 cmp/eq r0, r1
164 bt ex_nochain
165 mov.l break_after_k, r0
166 cmp/eq r0, r1
167 bt ex_nochain
168 ! For everything else, spc += 2
169 add #2, r2
170 ldc r2, spc
171 bra ex_nochain
172 nop
173 ex_slot_spc:
174 add #4, r2
175 ldc r2, spc
176 bra ex_nochain
177 nop
179 ex_dontcare: ! Not the event we were waiting for.
180 ! Check if its a trapa #42 ("Switch to system mode")
181 mov.l trapa_exc_k, r0
182 cmp/eq r0,r1
183 bf ex_chain
184 mov.l trapa_k, r0
185 mov.l @r0, r0
186 shlr2 r0
187 cmp/eq #42, r0
188 bf ex_chain
189 ! Yes, yes it is - update SSR and return without chaining
190 stc ssr, r0
191 mov #0x40, r1
192 mov #24, r2
193 shld r2, r1
194 or r0, r1
195 ldc r1, ssr
196 bra ex_nochain
197 nop
199 ex_chain:
200 mov.l old_vbr_k, r2
201 mov.l @r2, r2
202 xor r0, r0
203 cmp/eq r0, r2
204 bt ex_nochain
206 stc ssr, r0
207 mov.l r0, @-r15
208 stc spc, r0
209 mov.l r0, @-r15
210 stc sgr, r0
211 mov.l r0, @-r15
212 mov.l ex_chainreturn, r0
213 ldc r0, spc
214 mova handler_stack_ptr, r0
215 mov.l r15, @r0
216 braf r2 ! Chain on
217 nop
219 ex_chainreturn:
220 mov.l handler_stack_ptr, r15
221 mov.l @r15+, r0
222 ldc r0, sgr
223 mov.l @r15+, r0
224 ldc r0, spc
225 mov.l @r15+, r0
226 ldc r0, ssr
228 ex_nochain: ! No previous vbr to chain to
229 mova handler_stack_ptr, r0
230 mov r15, r1
231 add #12, r1
232 mov.l r1, @r0
233 mov.l @r15+, r2
234 mov.l @r15+, r1
235 mov.l @r15+, r0
236 stc sgr, r15
237 rte
238 nop
239 .align 4
240 expected_intevt_k:
241 .long expected_intevt
242 interrupt_count_k:
243 .long _interrupt_count
244 interrupt_pc_k:
245 .long _interrupt_pc
246 old_vbr_k:
247 .long old_vbr
248 trapa_k:
249 .long 0xFF000020
250 intevt_k:
251 .long 0xFF000028
253 slot_illegal_k:
254 .long 0x000001A0
255 slot_fpu_disable_k:
256 .long 0x00000820
257 trapa_exc_k:
258 .long 0x00000160
259 break_after_k:
260 .long 0x000001E0
262 handler_stack_ptr:
263 .long handler_stack_end
265 handler_stack:
266 .skip 0x200
267 handler_stack_end:
270 .globl _irq_disable
271 _irq_disable:
272 mov.l _irqd_and,r1
273 mov.l _irqd_or,r2
274 stc sr,r0
275 and r0,r1
276 or r2,r1
277 ldc r1,sr
278 rts
279 nop
281 .align 2
282 _irqd_and:
283 .long 0xefffff0f
284 _irqd_or:
285 .long 0x000000f0
288 .globl _irq_enable
289 _irq_enable:
290 mov.l _irqe_and,r1
291 stc sr,r0
292 and r0,r1
293 ldc r1,sr
294 rts
295 nop
297 .align 2
298 _irqe_and:
299 .long 0xefffff0f
.