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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 368:36fac4c42322
prev361:be3de4ecd954
next374:8f80a795513e
author nkeynes
date Tue Sep 04 08:40:23 2007 +0000 (15 years ago)
permissions -rw-r--r--
last change More translator WIP - blocks are approaching something sane
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     1 /**
     2  * $Id: sh4x86.c,v 1.3 2007-09-04 08:40:23 nkeynes Exp $
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4trans.h"
    25 #include "sh4/x86op.h"
    26 #include "clock.h"
    28 #define DEFAULT_BACKPATCH_SIZE 4096
    30 /** 
    31  * Struct to manage internal translation state. This state is not saved -
    32  * it is only valid between calls to sh4_translate_begin_block() and
    33  * sh4_translate_end_block()
    34  */
    35 struct sh4_x86_state {
    36     gboolean in_delay_slot;
    37     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    38     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    40     /* Allocated memory for the (block-wide) back-patch list */
    41     uint32_t **backpatch_list;
    42     uint32_t backpatch_posn;
    43     uint32_t backpatch_size;
    44 };
    46 #define EXIT_DATA_ADDR_READ 0
    47 #define EXIT_DATA_ADDR_WRITE 7
    48 #define EXIT_ILLEGAL 14
    49 #define EXIT_SLOT_ILLEGAL 21
    50 #define EXIT_FPU_DISABLED 28
    51 #define EXIT_SLOT_FPU_DISABLED 35
    53 static struct sh4_x86_state sh4_x86;
    55 void sh4_x86_init()
    56 {
    57     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
    58     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
    59 }
    62 static void sh4_x86_add_backpatch( uint8_t *ptr )
    63 {
    64     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
    65 	sh4_x86.backpatch_size <<= 1;
    66 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
    67 	assert( sh4_x86.backpatch_list != NULL );
    68     }
    69     sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
    70 }
    72 static void sh4_x86_do_backpatch( uint8_t *reloc_base )
    73 {
    74     unsigned int i;
    75     for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
    76 	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]));
    77     }
    78 }
    80 #ifndef NDEBUG
    81 #define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
    82 #define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
    83 #else
    84 #define MARK_JMP(x,n)
    85 #define CHECK_JMP(x)
    86 #endif
    89 /**
    90  * Emit an instruction to load an SH4 reg into a real register
    91  */
    92 static inline void load_reg( int x86reg, int sh4reg ) 
    93 {
    94     /* mov [bp+n], reg */
    95     OP(0x8B);
    96     OP(0x45 + (x86reg<<3));
    97     OP(REG_OFFSET(r[sh4reg]));
    98 }
   100 /**
   101  * Load the SR register into an x86 register
   102  */
   103 static inline void read_sr( int x86reg )
   104 {
   105     MOV_ebp_r32( R_M, x86reg );
   106     SHL1_r32( x86reg );
   107     OR_ebp_r32( R_Q, x86reg );
   108     SHL_imm8_r32( 7, x86reg );
   109     OR_ebp_r32( R_S, x86reg );
   110     SHL1_r32( x86reg );
   111     OR_ebp_r32( R_T, x86reg );
   112     OR_ebp_r32( R_SR, x86reg );
   113 }
   115 static inline void write_sr( int x86reg )
   116 {
   117     TEST_imm32_r32( SR_M, x86reg );
   118     SETNE_ebp(R_M);
   119     TEST_imm32_r32( SR_Q, x86reg );
   120     SETNE_ebp(R_Q);
   121     TEST_imm32_r32( SR_S, x86reg );
   122     SETNE_ebp(R_S);
   123     TEST_imm32_r32( SR_T, x86reg );
   124     SETNE_ebp(R_T);
   125     AND_imm32_r32( SR_MQSTMASK, x86reg );
   126     MOV_r32_ebp( x86reg, R_SR );
   127 }
   130 static inline void load_spreg( int x86reg, int regoffset )
   131 {
   132     /* mov [bp+n], reg */
   133     OP(0x8B);
   134     OP(0x45 + (x86reg<<3));
   135     OP(regoffset);
   136 }
   138 /**
   139  * Emit an instruction to load an immediate value into a register
   140  */
   141 static inline void load_imm32( int x86reg, uint32_t value ) {
   142     /* mov #value, reg */
   143     OP(0xB8 + x86reg);
   144     OP32(value);
   145 }
   147 /**
   148  * Emit an instruction to store an SH4 reg (RN)
   149  */
   150 void static inline store_reg( int x86reg, int sh4reg ) {
   151     /* mov reg, [bp+n] */
   152     OP(0x89);
   153     OP(0x45 + (x86reg<<3));
   154     OP(REG_OFFSET(r[sh4reg]));
   155 }
   156 void static inline store_spreg( int x86reg, int regoffset ) {
   157     /* mov reg, [bp+n] */
   158     OP(0x89);
   159     OP(0x45 + (x86reg<<3));
   160     OP(regoffset);
   161 }
   163 /**
   164  * Note: clobbers EAX to make the indirect call - this isn't usually
   165  * a problem since the callee will usually clobber it anyway.
   166  */
   167 static inline void call_func0( void *ptr )
   168 {
   169     load_imm32(R_EAX, (uint32_t)ptr);
   170     CALL_r32(R_EAX);
   171 }
   173 static inline void call_func1( void *ptr, int arg1 )
   174 {
   175     PUSH_r32(arg1);
   176     call_func0(ptr);
   177     ADD_imm8s_r32( -4, R_ESP );
   178 }
   180 static inline void call_func2( void *ptr, int arg1, int arg2 )
   181 {
   182     PUSH_r32(arg2);
   183     PUSH_r32(arg1);
   184     call_func0(ptr);
   185     ADD_imm8s_r32( -4, R_ESP );
   186 }
   188 /* Exception checks - Note that all exception checks will clobber EAX */
   189 static void check_priv( )
   190 {
   191     if( !sh4_x86.priv_checked ) {
   192 	sh4_x86.priv_checked = TRUE;
   193 	load_spreg( R_EAX, R_SR );
   194 	AND_imm32_r32( SR_MD, R_EAX );
   195 	if( sh4_x86.in_delay_slot ) {
   196 	    JE_exit( EXIT_SLOT_ILLEGAL );
   197 	} else {
   198 	    JE_exit( EXIT_ILLEGAL );
   199 	}
   200     }
   201 }
   203 static void check_fpuen( )
   204 {
   205     if( !sh4_x86.fpuen_checked ) {
   206 	sh4_x86.fpuen_checked = TRUE;
   207 	load_spreg( R_EAX, R_SR );
   208 	AND_imm32_r32( SR_FD, R_EAX );
   209 	if( sh4_x86.in_delay_slot ) {
   210 	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
   211 	} else {
   212 	    JNE_exit(EXIT_FPU_DISABLED);
   213 	}
   214     }
   215 }
   217 static void check_ralign16( int x86reg )
   218 {
   219     TEST_imm32_r32( 0x00000001, x86reg );
   220     JNE_exit(EXIT_DATA_ADDR_READ);
   221 }
   223 static void check_walign16( int x86reg )
   224 {
   225     TEST_imm32_r32( 0x00000001, x86reg );
   226     JNE_exit(EXIT_DATA_ADDR_WRITE);
   227 }
   229 static void check_ralign32( int x86reg )
   230 {
   231     TEST_imm32_r32( 0x00000003, x86reg );
   232     JNE_exit(EXIT_DATA_ADDR_READ);
   233 }
   234 static void check_walign32( int x86reg )
   235 {
   236     TEST_imm32_r32( 0x00000003, x86reg );
   237     JNE_exit(EXIT_DATA_ADDR_WRITE);
   238 }
   241 #define UNDEF()
   242 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   243 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
   244 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
   245 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
   246 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
   247 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
   248 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
   250 #define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
   251 #define CHECKSLOTILLEGAL() if(sh4_x86.in_delay_slot) RAISE_EXCEPTION(EXC_SLOT_ILLEGAL)
   255 /**
   256  * Emit the 'start of block' assembly. Sets up the stack frame and save
   257  * SI/DI as required
   258  */
   259 void sh4_translate_begin_block() 
   260 {
   261     PUSH_r32(R_EBP);
   262     PUSH_r32(R_ESI);
   263     /* mov &sh4r, ebp */
   264     load_imm32( R_EBP, (uint32_t)&sh4r );
   265     PUSH_r32(R_ESI);
   267     sh4_x86.in_delay_slot = FALSE;
   268     sh4_x86.priv_checked = FALSE;
   269     sh4_x86.fpuen_checked = FALSE;
   270     sh4_x86.backpatch_posn = 0;
   271 }
   273 /**
   274  * Exit the block early (ie branch out), conditionally or otherwise
   275  */
   276 void exit_block( uint32_t pc )
   277 {
   278     load_imm32( R_ECX, pc );
   279     store_spreg( R_ECX, REG_OFFSET(pc) );
   280     MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
   281     load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   282     MUL_r32( R_ESI );
   283     ADD_r32_r32( R_EAX, R_ECX );
   284     store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   285     XOR_r32_r32( R_EAX, R_EAX );
   286     RET();
   287 }
   289 /**
   290  * Flush any open regs back to memory, restore SI/DI/, update PC, etc
   291  */
   292 void sh4_translate_end_block( sh4addr_t pc ) {
   293     assert( !sh4_x86.in_delay_slot ); // should never stop here
   294     // Normal termination - save PC, cycle count
   295     exit_block( pc );
   297     uint8_t *end_ptr = xlat_output;
   298     // Exception termination. Jump block for various exception codes:
   299     PUSH_imm32( EXC_DATA_ADDR_READ );
   300     JMP_rel8( 33 );
   301     PUSH_imm32( EXC_DATA_ADDR_WRITE );
   302     JMP_rel8( 26 );
   303     PUSH_imm32( EXC_ILLEGAL );
   304     JMP_rel8( 19 );
   305     PUSH_imm32( EXC_SLOT_ILLEGAL ); 
   306     JMP_rel8( 12 );
   307     PUSH_imm32( EXC_FPU_DISABLED ); 
   308     JMP_rel8( 5 );                 
   309     PUSH_imm32( EXC_SLOT_FPU_DISABLED );
   310     // target
   311     load_spreg( R_ECX, REG_OFFSET(pc) );
   312     ADD_r32_r32( R_ESI, R_ECX );
   313     ADD_r32_r32( R_ESI, R_ECX );
   314     store_spreg( R_ECX, REG_OFFSET(pc) );
   315     MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
   316     load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   317     MUL_r32( R_ESI );
   318     ADD_r32_r32( R_EAX, R_ECX );
   319     store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   321     load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
   322     CALL_r32( R_EAX ); // 2
   323     POP_r32(R_EBP);
   324     RET();
   326     sh4_x86_do_backpatch( end_ptr );
   327 }
   329 /**
   330  * Translate a single instruction. Delayed branches are handled specially
   331  * by translating both branch and delayed instruction as a single unit (as
   332  * 
   333  *
   334  * @return true if the instruction marks the end of a basic block
   335  * (eg a branch or 
   336  */
   337 uint32_t sh4_x86_translate_instruction( uint32_t pc )
   338 {
   339     uint16_t ir = sh4_read_word( pc );
   341         switch( (ir&0xF000) >> 12 ) {
   342             case 0x0:
   343                 switch( ir&0xF ) {
   344                     case 0x2:
   345                         switch( (ir&0x80) >> 7 ) {
   346                             case 0x0:
   347                                 switch( (ir&0x70) >> 4 ) {
   348                                     case 0x0:
   349                                         { /* STC SR, Rn */
   350                                         uint32_t Rn = ((ir>>8)&0xF); 
   351                                         read_sr( R_EAX );
   352                                         store_reg( R_EAX, Rn );
   353                                         }
   354                                         break;
   355                                     case 0x1:
   356                                         { /* STC GBR, Rn */
   357                                         uint32_t Rn = ((ir>>8)&0xF); 
   358                                         load_spreg( R_EAX, R_GBR );
   359                                         store_reg( R_EAX, Rn );
   360                                         }
   361                                         break;
   362                                     case 0x2:
   363                                         { /* STC VBR, Rn */
   364                                         uint32_t Rn = ((ir>>8)&0xF); 
   365                                         load_spreg( R_EAX, R_VBR );
   366                                         store_reg( R_EAX, Rn );
   367                                         }
   368                                         break;
   369                                     case 0x3:
   370                                         { /* STC SSR, Rn */
   371                                         uint32_t Rn = ((ir>>8)&0xF); 
   372                                         load_spreg( R_EAX, R_SSR );
   373                                         store_reg( R_EAX, Rn );
   374                                         }
   375                                         break;
   376                                     case 0x4:
   377                                         { /* STC SPC, Rn */
   378                                         uint32_t Rn = ((ir>>8)&0xF); 
   379                                         load_spreg( R_EAX, R_SPC );
   380                                         store_reg( R_EAX, Rn );
   381                                         }
   382                                         break;
   383                                     default:
   384                                         UNDEF();
   385                                         break;
   386                                 }
   387                                 break;
   388                             case 0x1:
   389                                 { /* STC Rm_BANK, Rn */
   390                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   391                                 /* TODO */
   392                                 }
   393                                 break;
   394                         }
   395                         break;
   396                     case 0x3:
   397                         switch( (ir&0xF0) >> 4 ) {
   398                             case 0x0:
   399                                 { /* BSRF Rn */
   400                                 uint32_t Rn = ((ir>>8)&0xF); 
   401                                 }
   402                                 break;
   403                             case 0x2:
   404                                 { /* BRAF Rn */
   405                                 uint32_t Rn = ((ir>>8)&0xF); 
   406                                 }
   407                                 break;
   408                             case 0x8:
   409                                 { /* PREF @Rn */
   410                                 uint32_t Rn = ((ir>>8)&0xF); 
   411                                 }
   412                                 break;
   413                             case 0x9:
   414                                 { /* OCBI @Rn */
   415                                 uint32_t Rn = ((ir>>8)&0xF); 
   416                                 }
   417                                 break;
   418                             case 0xA:
   419                                 { /* OCBP @Rn */
   420                                 uint32_t Rn = ((ir>>8)&0xF); 
   421                                 }
   422                                 break;
   423                             case 0xB:
   424                                 { /* OCBWB @Rn */
   425                                 uint32_t Rn = ((ir>>8)&0xF); 
   426                                 }
   427                                 break;
   428                             case 0xC:
   429                                 { /* MOVCA.L R0, @Rn */
   430                                 uint32_t Rn = ((ir>>8)&0xF); 
   431                                 load_reg( R_EAX, 0 );
   432                                 load_reg( R_ECX, Rn );
   433                                 MEM_WRITE_LONG( R_ECX, R_EAX );
   434                                 }
   435                                 break;
   436                             default:
   437                                 UNDEF();
   438                                 break;
   439                         }
   440                         break;
   441                     case 0x4:
   442                         { /* MOV.B Rm, @(R0, Rn) */
   443                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   444                         load_reg( R_EAX, 0 );
   445                         load_reg( R_ECX, Rn );
   446                         ADD_r32_r32( R_EAX, R_ECX );
   447                         load_reg( R_EAX, Rm );
   448                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   449                         }
   450                         break;
   451                     case 0x5:
   452                         { /* MOV.W Rm, @(R0, Rn) */
   453                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   454                         load_reg( R_EAX, 0 );
   455                         load_reg( R_ECX, Rn );
   456                         ADD_r32_r32( R_EAX, R_ECX );
   457                         load_reg( R_EAX, Rm );
   458                         MEM_WRITE_WORD( R_ECX, R_EAX );
   459                         }
   460                         break;
   461                     case 0x6:
   462                         { /* MOV.L Rm, @(R0, Rn) */
   463                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   464                         load_reg( R_EAX, 0 );
   465                         load_reg( R_ECX, Rn );
   466                         ADD_r32_r32( R_EAX, R_ECX );
   467                         load_reg( R_EAX, Rm );
   468                         MEM_WRITE_LONG( R_ECX, R_EAX );
   469                         }
   470                         break;
   471                     case 0x7:
   472                         { /* MUL.L Rm, Rn */
   473                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   474                         load_reg( R_EAX, Rm );
   475                         load_reg( R_ECX, Rn );
   476                         MUL_r32( R_ECX );
   477                         store_spreg( R_EAX, R_MACL );
   478                         }
   479                         break;
   480                     case 0x8:
   481                         switch( (ir&0xFF0) >> 4 ) {
   482                             case 0x0:
   483                                 { /* CLRT */
   484                                 }
   485                                 break;
   486                             case 0x1:
   487                                 { /* SETT */
   488                                 }
   489                                 break;
   490                             case 0x2:
   491                                 { /* CLRMAC */
   492                                 }
   493                                 break;
   494                             case 0x3:
   495                                 { /* LDTLB */
   496                                 }
   497                                 break;
   498                             case 0x4:
   499                                 { /* CLRS */
   500                                 }
   501                                 break;
   502                             case 0x5:
   503                                 { /* SETS */
   504                                 }
   505                                 break;
   506                             default:
   507                                 UNDEF();
   508                                 break;
   509                         }
   510                         break;
   511                     case 0x9:
   512                         switch( (ir&0xF0) >> 4 ) {
   513                             case 0x0:
   514                                 { /* NOP */
   515                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   516                                 }
   517                                 break;
   518                             case 0x1:
   519                                 { /* DIV0U */
   520                                 XOR_r32_r32( R_EAX, R_EAX );
   521                                 store_spreg( R_EAX, R_Q );
   522                                 store_spreg( R_EAX, R_M );
   523                                 store_spreg( R_EAX, R_T );
   524                                 }
   525                                 break;
   526                             case 0x2:
   527                                 { /* MOVT Rn */
   528                                 uint32_t Rn = ((ir>>8)&0xF); 
   529                                 load_spreg( R_EAX, R_T );
   530                                 store_reg( R_EAX, Rn );
   531                                 }
   532                                 break;
   533                             default:
   534                                 UNDEF();
   535                                 break;
   536                         }
   537                         break;
   538                     case 0xA:
   539                         switch( (ir&0xF0) >> 4 ) {
   540                             case 0x0:
   541                                 { /* STS MACH, Rn */
   542                                 uint32_t Rn = ((ir>>8)&0xF); 
   543                                 load_spreg( R_EAX, R_MACH );
   544                                 store_reg( R_EAX, Rn );
   545                                 }
   546                                 break;
   547                             case 0x1:
   548                                 { /* STS MACL, Rn */
   549                                 uint32_t Rn = ((ir>>8)&0xF); 
   550                                 load_spreg( R_EAX, R_MACL );
   551                                 store_reg( R_EAX, Rn );
   552                                 }
   553                                 break;
   554                             case 0x2:
   555                                 { /* STS PR, Rn */
   556                                 uint32_t Rn = ((ir>>8)&0xF); 
   557                                 load_spreg( R_EAX, R_PR );
   558                                 store_reg( R_EAX, Rn );
   559                                 }
   560                                 break;
   561                             case 0x3:
   562                                 { /* STC SGR, Rn */
   563                                 uint32_t Rn = ((ir>>8)&0xF); 
   564                                 load_spreg( R_EAX, R_SGR );
   565                                 store_reg( R_EAX, Rn );
   566                                 }
   567                                 break;
   568                             case 0x5:
   569                                 { /* STS FPUL, Rn */
   570                                 uint32_t Rn = ((ir>>8)&0xF); 
   571                                 load_spreg( R_EAX, R_FPUL );
   572                                 store_reg( R_EAX, Rn );
   573                                 }
   574                                 break;
   575                             case 0x6:
   576                                 { /* STS FPSCR, Rn */
   577                                 uint32_t Rn = ((ir>>8)&0xF); 
   578                                 load_spreg( R_EAX, R_FPSCR );
   579                                 store_reg( R_EAX, Rn );
   580                                 }
   581                                 break;
   582                             case 0xF:
   583                                 { /* STC DBR, Rn */
   584                                 uint32_t Rn = ((ir>>8)&0xF); 
   585                                 load_spreg( R_EAX, R_DBR );
   586                                 store_reg( R_EAX, Rn );
   587                                 }
   588                                 break;
   589                             default:
   590                                 UNDEF();
   591                                 break;
   592                         }
   593                         break;
   594                     case 0xB:
   595                         switch( (ir&0xFF0) >> 4 ) {
   596                             case 0x0:
   597                                 { /* RTS */
   598                                 }
   599                                 break;
   600                             case 0x1:
   601                                 { /* SLEEP */
   602                                 }
   603                                 break;
   604                             case 0x2:
   605                                 { /* RTE */
   606                                 }
   607                                 break;
   608                             default:
   609                                 UNDEF();
   610                                 break;
   611                         }
   612                         break;
   613                     case 0xC:
   614                         { /* MOV.B @(R0, Rm), Rn */
   615                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   616                         load_reg( R_EAX, 0 );
   617                         load_reg( R_ECX, Rm );
   618                         ADD_r32_r32( R_EAX, R_ECX );
   619                         MEM_READ_BYTE( R_ECX, R_EAX );
   620                         store_reg( R_EAX, Rn );
   621                         }
   622                         break;
   623                     case 0xD:
   624                         { /* MOV.W @(R0, Rm), Rn */
   625                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   626                         load_reg( R_EAX, 0 );
   627                         load_reg( R_ECX, Rm );
   628                         ADD_r32_r32( R_EAX, R_ECX );
   629                         MEM_READ_WORD( R_ECX, R_EAX );
   630                         store_reg( R_EAX, Rn );
   631                         }
   632                         break;
   633                     case 0xE:
   634                         { /* MOV.L @(R0, Rm), Rn */
   635                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   636                         load_reg( R_EAX, 0 );
   637                         load_reg( R_ECX, Rm );
   638                         ADD_r32_r32( R_EAX, R_ECX );
   639                         MEM_READ_LONG( R_ECX, R_EAX );
   640                         store_reg( R_EAX, Rn );
   641                         }
   642                         break;
   643                     case 0xF:
   644                         { /* MAC.L @Rm+, @Rn+ */
   645                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   646                         }
   647                         break;
   648                     default:
   649                         UNDEF();
   650                         break;
   651                 }
   652                 break;
   653             case 0x1:
   654                 { /* MOV.L Rm, @(disp, Rn) */
   655                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   656                 load_reg( R_ECX, Rn );
   657                 load_reg( R_EAX, Rm );
   658                 ADD_imm32_r32( disp, R_ECX );
   659                 MEM_WRITE_LONG( R_ECX, R_EAX );
   660                 }
   661                 break;
   662             case 0x2:
   663                 switch( ir&0xF ) {
   664                     case 0x0:
   665                         { /* MOV.B Rm, @Rn */
   666                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   667                         load_reg( R_EAX, Rm );
   668                         load_reg( R_ECX, Rn );
   669                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   670                         }
   671                         break;
   672                     case 0x1:
   673                         { /* MOV.W Rm, @Rn */
   674                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   675                         load_reg( R_ECX, Rn );
   676                         MEM_READ_WORD( R_ECX, R_EAX );
   677                         store_reg( R_EAX, Rn );
   678                         }
   679                         break;
   680                     case 0x2:
   681                         { /* MOV.L Rm, @Rn */
   682                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   683                         load_reg( R_EAX, Rm );
   684                         load_reg( R_ECX, Rn );
   685                         MEM_WRITE_LONG( R_ECX, R_EAX );
   686                         }
   687                         break;
   688                     case 0x4:
   689                         { /* MOV.B Rm, @-Rn */
   690                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   691                         load_reg( R_EAX, Rm );
   692                         load_reg( R_ECX, Rn );
   693                         ADD_imm8s_r32( -1, Rn );
   694                         store_reg( R_ECX, Rn );
   695                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   696                         }
   697                         break;
   698                     case 0x5:
   699                         { /* MOV.W Rm, @-Rn */
   700                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   701                         load_reg( R_ECX, Rn );
   702                         load_reg( R_EAX, Rm );
   703                         ADD_imm8s_r32( -2, R_ECX );
   704                         MEM_WRITE_WORD( R_ECX, R_EAX );
   705                         }
   706                         break;
   707                     case 0x6:
   708                         { /* MOV.L Rm, @-Rn */
   709                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   710                         load_reg( R_EAX, Rm );
   711                         load_reg( R_ECX, Rn );
   712                         ADD_imm8s_r32( -4, R_ECX );
   713                         store_reg( R_ECX, Rn );
   714                         MEM_WRITE_LONG( R_ECX, R_EAX );
   715                         }
   716                         break;
   717                     case 0x7:
   718                         { /* DIV0S Rm, Rn */
   719                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   720                         load_reg( R_EAX, Rm );
   721                         load_reg( R_ECX, Rm );
   722                         SHR_imm8_r32( 31, R_EAX );
   723                         SHR_imm8_r32( 31, R_ECX );
   724                         store_spreg( R_EAX, R_M );
   725                         store_spreg( R_ECX, R_Q );
   726                         CMP_r32_r32( R_EAX, R_ECX );
   727                         SETE_t();
   728                         }
   729                         break;
   730                     case 0x8:
   731                         { /* TST Rm, Rn */
   732                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   733                         load_reg( R_EAX, Rm );
   734                         load_reg( R_ECX, Rn );
   735                         TEST_r32_r32( R_EAX, R_ECX );
   736                         SETE_t();
   737                         }
   738                         break;
   739                     case 0x9:
   740                         { /* AND Rm, Rn */
   741                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   742                         load_reg( R_EAX, Rm );
   743                         load_reg( R_ECX, Rn );
   744                         AND_r32_r32( R_EAX, R_ECX );
   745                         store_reg( R_ECX, Rn );
   746                         }
   747                         break;
   748                     case 0xA:
   749                         { /* XOR Rm, Rn */
   750                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   751                         load_reg( R_EAX, Rm );
   752                         load_reg( R_ECX, Rn );
   753                         XOR_r32_r32( R_EAX, R_ECX );
   754                         store_reg( R_ECX, Rn );
   755                         }
   756                         break;
   757                     case 0xB:
   758                         { /* OR Rm, Rn */
   759                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   760                         load_reg( R_EAX, Rm );
   761                         load_reg( R_ECX, Rn );
   762                         OR_r32_r32( R_EAX, R_ECX );
   763                         store_reg( R_ECX, Rn );
   764                         }
   765                         break;
   766                     case 0xC:
   767                         { /* CMP/STR Rm, Rn */
   768                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   769                         load_reg( R_EAX, Rm );
   770                         load_reg( R_ECX, Rn );
   771                         XOR_r32_r32( R_ECX, R_EAX );
   772                         TEST_r8_r8( R_AL, R_AL );
   773                         JE_rel8(13);
   774                         TEST_r8_r8( R_AH, R_AH ); // 2
   775                         JE_rel8(9);
   776                         SHR_imm8_r32( 16, R_EAX ); // 3
   777                         TEST_r8_r8( R_AL, R_AL ); // 2
   778                         JE_rel8(2);
   779                         TEST_r8_r8( R_AH, R_AH ); // 2
   780                         SETE_t();
   781                         }
   782                         break;
   783                     case 0xD:
   784                         { /* XTRCT Rm, Rn */
   785                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   786                         load_reg( R_EAX, Rm );
   787                         MOV_r32_r32( R_EAX, R_ECX );
   788                         SHR_imm8_r32( 16, R_EAX );
   789                         SHL_imm8_r32( 16, R_ECX );
   790                         OR_r32_r32( R_EAX, R_ECX );
   791                         store_reg( R_ECX, Rn );
   792                         }
   793                         break;
   794                     case 0xE:
   795                         { /* MULU.W Rm, Rn */
   796                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   797                         }
   798                         break;
   799                     case 0xF:
   800                         { /* MULS.W Rm, Rn */
   801                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   802                         }
   803                         break;
   804                     default:
   805                         UNDEF();
   806                         break;
   807                 }
   808                 break;
   809             case 0x3:
   810                 switch( ir&0xF ) {
   811                     case 0x0:
   812                         { /* CMP/EQ Rm, Rn */
   813                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   814                         load_reg( R_EAX, Rm );
   815                         load_reg( R_ECX, Rn );
   816                         CMP_r32_r32( R_EAX, R_ECX );
   817                         SETE_t();
   818                         }
   819                         break;
   820                     case 0x2:
   821                         { /* CMP/HS Rm, Rn */
   822                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   823                         load_reg( R_EAX, Rm );
   824                         load_reg( R_ECX, Rn );
   825                         CMP_r32_r32( R_EAX, R_ECX );
   826                         SETAE_t();
   827                         }
   828                         break;
   829                     case 0x3:
   830                         { /* CMP/GE Rm, Rn */
   831                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   832                         load_reg( R_EAX, Rm );
   833                         load_reg( R_ECX, Rn );
   834                         CMP_r32_r32( R_EAX, R_ECX );
   835                         SETGE_t();
   836                         }
   837                         break;
   838                     case 0x4:
   839                         { /* DIV1 Rm, Rn */
   840                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   841                         }
   842                         break;
   843                     case 0x5:
   844                         { /* DMULU.L Rm, Rn */
   845                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   846                         load_reg( R_EAX, Rm );
   847                         load_reg( R_ECX, Rn );
   848                         MUL_r32(R_ECX);
   849                         store_spreg( R_EDX, R_MACH );
   850                         store_spreg( R_EAX, R_MACL );
   851                         }
   852                         break;
   853                     case 0x6:
   854                         { /* CMP/HI Rm, Rn */
   855                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   856                         load_reg( R_EAX, Rm );
   857                         load_reg( R_ECX, Rn );
   858                         CMP_r32_r32( R_EAX, R_ECX );
   859                         SETA_t();
   860                         }
   861                         break;
   862                     case 0x7:
   863                         { /* CMP/GT Rm, Rn */
   864                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   865                         load_reg( R_EAX, Rm );
   866                         load_reg( R_ECX, Rn );
   867                         CMP_r32_r32( R_EAX, R_ECX );
   868                         SETG_t();
   869                         }
   870                         break;
   871                     case 0x8:
   872                         { /* SUB Rm, Rn */
   873                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   874                         load_reg( R_EAX, Rm );
   875                         load_reg( R_ECX, Rn );
   876                         SUB_r32_r32( R_EAX, R_ECX );
   877                         store_reg( R_ECX, Rn );
   878                         }
   879                         break;
   880                     case 0xA:
   881                         { /* SUBC Rm, Rn */
   882                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   883                         load_reg( R_EAX, Rm );
   884                         load_reg( R_ECX, Rn );
   885                         LDC_t();
   886                         SBB_r32_r32( R_EAX, R_ECX );
   887                         store_reg( R_ECX, Rn );
   888                         }
   889                         break;
   890                     case 0xB:
   891                         { /* SUBV Rm, Rn */
   892                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   893                         load_reg( R_EAX, Rm );
   894                         load_reg( R_ECX, Rn );
   895                         SUB_r32_r32( R_EAX, R_ECX );
   896                         store_reg( R_ECX, Rn );
   897                         SETO_t();
   898                         }
   899                         break;
   900                     case 0xC:
   901                         { /* ADD Rm, Rn */
   902                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   903                         load_reg( R_EAX, Rm );
   904                         load_reg( R_ECX, Rn );
   905                         ADD_r32_r32( R_EAX, R_ECX );
   906                         store_reg( R_ECX, Rn );
   907                         }
   908                         break;
   909                     case 0xD:
   910                         { /* DMULS.L Rm, Rn */
   911                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   912                         load_reg( R_EAX, Rm );
   913                         load_reg( R_ECX, Rn );
   914                         IMUL_r32(R_ECX);
   915                         store_spreg( R_EDX, R_MACH );
   916                         store_spreg( R_EAX, R_MACL );
   917                         }
   918                         break;
   919                     case 0xE:
   920                         { /* ADDC Rm, Rn */
   921                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   922                         load_reg( R_EAX, Rm );
   923                         load_reg( R_ECX, Rn );
   924                         LDC_t();
   925                         ADC_r32_r32( R_EAX, R_ECX );
   926                         store_reg( R_ECX, Rn );
   927                         SETC_t();
   928                         }
   929                         break;
   930                     case 0xF:
   931                         { /* ADDV Rm, Rn */
   932                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   933                         load_reg( R_EAX, Rm );
   934                         load_reg( R_ECX, Rn );
   935                         ADD_r32_r32( R_EAX, R_ECX );
   936                         store_reg( R_ECX, Rn );
   937                         SETO_t();
   938                         }
   939                         break;
   940                     default:
   941                         UNDEF();
   942                         break;
   943                 }
   944                 break;
   945             case 0x4:
   946                 switch( ir&0xF ) {
   947                     case 0x0:
   948                         switch( (ir&0xF0) >> 4 ) {
   949                             case 0x0:
   950                                 { /* SHLL Rn */
   951                                 uint32_t Rn = ((ir>>8)&0xF); 
   952                                 load_reg( R_EAX, Rn );
   953                                 SHL1_r32( R_EAX );
   954                                 store_reg( R_EAX, Rn );
   955                                 }
   956                                 break;
   957                             case 0x1:
   958                                 { /* DT Rn */
   959                                 uint32_t Rn = ((ir>>8)&0xF); 
   960                                 load_reg( R_EAX, Rn );
   961                                 ADD_imm8s_r32( -1, Rn );
   962                                 store_reg( R_EAX, Rn );
   963                                 SETE_t();
   964                                 }
   965                                 break;
   966                             case 0x2:
   967                                 { /* SHAL Rn */
   968                                 uint32_t Rn = ((ir>>8)&0xF); 
   969                                 load_reg( R_EAX, Rn );
   970                                 SHL1_r32( R_EAX );
   971                                 store_reg( R_EAX, Rn );
   972                                 }
   973                                 break;
   974                             default:
   975                                 UNDEF();
   976                                 break;
   977                         }
   978                         break;
   979                     case 0x1:
   980                         switch( (ir&0xF0) >> 4 ) {
   981                             case 0x0:
   982                                 { /* SHLR Rn */
   983                                 uint32_t Rn = ((ir>>8)&0xF); 
   984                                 load_reg( R_EAX, Rn );
   985                                 SHR1_r32( R_EAX );
   986                                 store_reg( R_EAX, Rn );
   987                                 }
   988                                 break;
   989                             case 0x1:
   990                                 { /* CMP/PZ Rn */
   991                                 uint32_t Rn = ((ir>>8)&0xF); 
   992                                 load_reg( R_EAX, Rn );
   993                                 CMP_imm8s_r32( 0, R_EAX );
   994                                 SETGE_t();
   995                                 }
   996                                 break;
   997                             case 0x2:
   998                                 { /* SHAR Rn */
   999                                 uint32_t Rn = ((ir>>8)&0xF); 
  1000                                 load_reg( R_EAX, Rn );
  1001                                 SAR1_r32( R_EAX );
  1002                                 store_reg( R_EAX, Rn );
  1004                                 break;
  1005                             default:
  1006                                 UNDEF();
  1007                                 break;
  1009                         break;
  1010                     case 0x2:
  1011                         switch( (ir&0xF0) >> 4 ) {
  1012                             case 0x0:
  1013                                 { /* STS.L MACH, @-Rn */
  1014                                 uint32_t Rn = ((ir>>8)&0xF); 
  1015                                 load_reg( R_ECX, Rn );
  1016                                 ADD_imm8s_r32( -4, Rn );
  1017                                 store_reg( R_ECX, Rn );
  1018                                 load_spreg( R_EAX, R_MACH );
  1019                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1021                                 break;
  1022                             case 0x1:
  1023                                 { /* STS.L MACL, @-Rn */
  1024                                 uint32_t Rn = ((ir>>8)&0xF); 
  1025                                 load_reg( R_ECX, Rn );
  1026                                 ADD_imm8s_r32( -4, Rn );
  1027                                 store_reg( R_ECX, Rn );
  1028                                 load_spreg( R_EAX, R_MACL );
  1029                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1031                                 break;
  1032                             case 0x2:
  1033                                 { /* STS.L PR, @-Rn */
  1034                                 uint32_t Rn = ((ir>>8)&0xF); 
  1035                                 load_reg( R_ECX, Rn );
  1036                                 ADD_imm8s_r32( -4, Rn );
  1037                                 store_reg( R_ECX, Rn );
  1038                                 load_spreg( R_EAX, R_PR );
  1039                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1041                                 break;
  1042                             case 0x3:
  1043                                 { /* STC.L SGR, @-Rn */
  1044                                 uint32_t Rn = ((ir>>8)&0xF); 
  1045                                 load_reg( R_ECX, Rn );
  1046                                 ADD_imm8s_r32( -4, Rn );
  1047                                 store_reg( R_ECX, Rn );
  1048                                 load_spreg( R_EAX, R_SGR );
  1049                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1051                                 break;
  1052                             case 0x5:
  1053                                 { /* STS.L FPUL, @-Rn */
  1054                                 uint32_t Rn = ((ir>>8)&0xF); 
  1055                                 load_reg( R_ECX, Rn );
  1056                                 ADD_imm8s_r32( -4, Rn );
  1057                                 store_reg( R_ECX, Rn );
  1058                                 load_spreg( R_EAX, R_FPUL );
  1059                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1061                                 break;
  1062                             case 0x6:
  1063                                 { /* STS.L FPSCR, @-Rn */
  1064                                 uint32_t Rn = ((ir>>8)&0xF); 
  1065                                 load_reg( R_ECX, Rn );
  1066                                 ADD_imm8s_r32( -4, Rn );
  1067                                 store_reg( R_ECX, Rn );
  1068                                 load_spreg( R_EAX, R_FPSCR );
  1069                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1071                                 break;
  1072                             case 0xF:
  1073                                 { /* STC.L DBR, @-Rn */
  1074                                 uint32_t Rn = ((ir>>8)&0xF); 
  1075                                 load_reg( R_ECX, Rn );
  1076                                 ADD_imm8s_r32( -4, Rn );
  1077                                 store_reg( R_ECX, Rn );
  1078                                 load_spreg( R_EAX, R_DBR );
  1079                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1081                                 break;
  1082                             default:
  1083                                 UNDEF();
  1084                                 break;
  1086                         break;
  1087                     case 0x3:
  1088                         switch( (ir&0x80) >> 7 ) {
  1089                             case 0x0:
  1090                                 switch( (ir&0x70) >> 4 ) {
  1091                                     case 0x0:
  1092                                         { /* STC.L SR, @-Rn */
  1093                                         uint32_t Rn = ((ir>>8)&0xF); 
  1094                                         /* TODO */
  1095                                           load_reg( R_ECX, Rn );
  1096                                           ADD_imm8s_r32( -4, Rn );
  1097                                           store_reg( R_ECX, Rn );
  1098                                           read_sr( R_EAX );
  1099                                           MEM_WRITE_LONG( R_ECX, R_EAX );
  1101                                         break;
  1102                                     case 0x1:
  1103                                         { /* STC.L GBR, @-Rn */
  1104                                         uint32_t Rn = ((ir>>8)&0xF); 
  1105                                         load_reg( R_ECX, Rn );
  1106                                         ADD_imm8s_r32( -4, Rn );
  1107                                         store_reg( R_ECX, Rn );
  1108                                         load_spreg( R_EAX, R_GBR );
  1109                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1111                                         break;
  1112                                     case 0x2:
  1113                                         { /* STC.L VBR, @-Rn */
  1114                                         uint32_t Rn = ((ir>>8)&0xF); 
  1115                                         load_reg( R_ECX, Rn );
  1116                                         ADD_imm8s_r32( -4, Rn );
  1117                                         store_reg( R_ECX, Rn );
  1118                                         load_spreg( R_EAX, R_VBR );
  1119                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1121                                         break;
  1122                                     case 0x3:
  1123                                         { /* STC.L SSR, @-Rn */
  1124                                         uint32_t Rn = ((ir>>8)&0xF); 
  1125                                         load_reg( R_ECX, Rn );
  1126                                         ADD_imm8s_r32( -4, Rn );
  1127                                         store_reg( R_ECX, Rn );
  1128                                         load_spreg( R_EAX, R_SSR );
  1129                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1131                                         break;
  1132                                     case 0x4:
  1133                                         { /* STC.L SPC, @-Rn */
  1134                                         uint32_t Rn = ((ir>>8)&0xF); 
  1135                                         load_reg( R_ECX, Rn );
  1136                                         ADD_imm8s_r32( -4, Rn );
  1137                                         store_reg( R_ECX, Rn );
  1138                                         load_spreg( R_EAX, R_SPC );
  1139                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1141                                         break;
  1142                                     default:
  1143                                         UNDEF();
  1144                                         break;
  1146                                 break;
  1147                             case 0x1:
  1148                                 { /* STC.L Rm_BANK, @-Rn */
  1149                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1151                                 break;
  1153                         break;
  1154                     case 0x4:
  1155                         switch( (ir&0xF0) >> 4 ) {
  1156                             case 0x0:
  1157                                 { /* ROTL Rn */
  1158                                 uint32_t Rn = ((ir>>8)&0xF); 
  1159                                 load_reg( R_EAX, Rn );
  1160                                 ROL1_r32( R_EAX );
  1161                                 store_reg( R_EAX, Rn );
  1162                                 SETC_t();
  1164                                 break;
  1165                             case 0x2:
  1166                                 { /* ROTCL Rn */
  1167                                 uint32_t Rn = ((ir>>8)&0xF); 
  1168                                 load_reg( R_EAX, Rn );
  1169                                 LDC_t();
  1170                                 RCL1_r32( R_EAX );
  1171                                 store_reg( R_EAX, Rn );
  1172                                 SETC_t();
  1174                                 break;
  1175                             default:
  1176                                 UNDEF();
  1177                                 break;
  1179                         break;
  1180                     case 0x5:
  1181                         switch( (ir&0xF0) >> 4 ) {
  1182                             case 0x0:
  1183                                 { /* ROTR Rn */
  1184                                 uint32_t Rn = ((ir>>8)&0xF); 
  1185                                 load_reg( R_EAX, Rn );
  1186                                 ROR1_r32( R_EAX );
  1187                                 store_reg( R_EAX, Rn );
  1188                                 SETC_t();
  1190                                 break;
  1191                             case 0x1:
  1192                                 { /* CMP/PL Rn */
  1193                                 uint32_t Rn = ((ir>>8)&0xF); 
  1194                                 load_reg( R_EAX, Rn );
  1195                                 CMP_imm8s_r32( 0, R_EAX );
  1196                                 SETG_t();
  1198                                 break;
  1199                             case 0x2:
  1200                                 { /* ROTCR Rn */
  1201                                 uint32_t Rn = ((ir>>8)&0xF); 
  1202                                 load_reg( R_EAX, Rn );
  1203                                 LDC_t();
  1204                                 RCR1_r32( R_EAX );
  1205                                 store_reg( R_EAX, Rn );
  1206                                 SETC_t();
  1208                                 break;
  1209                             default:
  1210                                 UNDEF();
  1211                                 break;
  1213                         break;
  1214                     case 0x6:
  1215                         switch( (ir&0xF0) >> 4 ) {
  1216                             case 0x0:
  1217                                 { /* LDS.L @Rm+, MACH */
  1218                                 uint32_t Rm = ((ir>>8)&0xF); 
  1219                                 load_reg( R_EAX, Rm );
  1220                                 MOV_r32_r32( R_EAX, R_ECX );
  1221                                 ADD_imm8s_r32( 4, R_EAX );
  1222                                 store_reg( R_EAX, Rm );
  1223                                 MEM_READ_LONG( R_ECX, R_EAX );
  1224                                 store_spreg( R_EAX, R_MACH );
  1226                                 break;
  1227                             case 0x1:
  1228                                 { /* LDS.L @Rm+, MACL */
  1229                                 uint32_t Rm = ((ir>>8)&0xF); 
  1230                                 load_reg( R_EAX, Rm );
  1231                                 MOV_r32_r32( R_EAX, R_ECX );
  1232                                 ADD_imm8s_r32( 4, R_EAX );
  1233                                 store_reg( R_EAX, Rm );
  1234                                 MEM_READ_LONG( R_ECX, R_EAX );
  1235                                 store_spreg( R_EAX, R_MACL );
  1237                                 break;
  1238                             case 0x2:
  1239                                 { /* LDS.L @Rm+, PR */
  1240                                 uint32_t Rm = ((ir>>8)&0xF); 
  1241                                 load_reg( R_EAX, Rm );
  1242                                 MOV_r32_r32( R_EAX, R_ECX );
  1243                                 ADD_imm8s_r32( 4, R_EAX );
  1244                                 store_reg( R_EAX, Rm );
  1245                                 MEM_READ_LONG( R_ECX, R_EAX );
  1246                                 store_spreg( R_EAX, R_PR );
  1248                                 break;
  1249                             case 0x3:
  1250                                 { /* LDC.L @Rm+, SGR */
  1251                                 uint32_t Rm = ((ir>>8)&0xF); 
  1252                                 load_reg( R_EAX, Rm );
  1253                                 MOV_r32_r32( R_EAX, R_ECX );
  1254                                 ADD_imm8s_r32( 4, R_EAX );
  1255                                 store_reg( R_EAX, Rm );
  1256                                 MEM_READ_LONG( R_ECX, R_EAX );
  1257                                 store_spreg( R_EAX, R_SGR );
  1259                                 break;
  1260                             case 0x5:
  1261                                 { /* LDS.L @Rm+, FPUL */
  1262                                 uint32_t Rm = ((ir>>8)&0xF); 
  1263                                 load_reg( R_EAX, Rm );
  1264                                 MOV_r32_r32( R_EAX, R_ECX );
  1265                                 ADD_imm8s_r32( 4, R_EAX );
  1266                                 store_reg( R_EAX, Rm );
  1267                                 MEM_READ_LONG( R_ECX, R_EAX );
  1268                                 store_spreg( R_EAX, R_FPUL );
  1270                                 break;
  1271                             case 0x6:
  1272                                 { /* LDS.L @Rm+, FPSCR */
  1273                                 uint32_t Rm = ((ir>>8)&0xF); 
  1274                                 load_reg( R_EAX, Rm );
  1275                                 MOV_r32_r32( R_EAX, R_ECX );
  1276                                 ADD_imm8s_r32( 4, R_EAX );
  1277                                 store_reg( R_EAX, Rm );
  1278                                 MEM_READ_LONG( R_ECX, R_EAX );
  1279                                 store_spreg( R_EAX, R_FPSCR );
  1281                                 break;
  1282                             case 0xF:
  1283                                 { /* LDC.L @Rm+, DBR */
  1284                                 uint32_t Rm = ((ir>>8)&0xF); 
  1285                                 load_reg( R_EAX, Rm );
  1286                                 MOV_r32_r32( R_EAX, R_ECX );
  1287                                 ADD_imm8s_r32( 4, R_EAX );
  1288                                 store_reg( R_EAX, Rm );
  1289                                 MEM_READ_LONG( R_ECX, R_EAX );
  1290                                 store_spreg( R_EAX, R_DBR );
  1292                                 break;
  1293                             default:
  1294                                 UNDEF();
  1295                                 break;
  1297                         break;
  1298                     case 0x7:
  1299                         switch( (ir&0x80) >> 7 ) {
  1300                             case 0x0:
  1301                                 switch( (ir&0x70) >> 4 ) {
  1302                                     case 0x0:
  1303                                         { /* LDC.L @Rm+, SR */
  1304                                         uint32_t Rm = ((ir>>8)&0xF); 
  1305                                         load_reg( R_EAX, Rm );
  1306                                         MOV_r32_r32( R_EAX, R_ECX );
  1307                                         ADD_imm8s_r32( 4, R_EAX );
  1308                                         store_reg( R_EAX, Rm );
  1309                                         MEM_READ_LONG( R_ECX, R_EAX );
  1310                                         write_sr( R_EAX );
  1312                                         break;
  1313                                     case 0x1:
  1314                                         { /* LDC.L @Rm+, GBR */
  1315                                         uint32_t Rm = ((ir>>8)&0xF); 
  1316                                         load_reg( R_EAX, Rm );
  1317                                         MOV_r32_r32( R_EAX, R_ECX );
  1318                                         ADD_imm8s_r32( 4, R_EAX );
  1319                                         store_reg( R_EAX, Rm );
  1320                                         MEM_READ_LONG( R_ECX, R_EAX );
  1321                                         store_spreg( R_EAX, R_GBR );
  1323                                         break;
  1324                                     case 0x2:
  1325                                         { /* LDC.L @Rm+, VBR */
  1326                                         uint32_t Rm = ((ir>>8)&0xF); 
  1327                                         load_reg( R_EAX, Rm );
  1328                                         MOV_r32_r32( R_EAX, R_ECX );
  1329                                         ADD_imm8s_r32( 4, R_EAX );
  1330                                         store_reg( R_EAX, Rm );
  1331                                         MEM_READ_LONG( R_ECX, R_EAX );
  1332                                         store_spreg( R_EAX, R_VBR );
  1334                                         break;
  1335                                     case 0x3:
  1336                                         { /* LDC.L @Rm+, SSR */
  1337                                         uint32_t Rm = ((ir>>8)&0xF); 
  1338                                         load_reg( R_EAX, Rm );
  1339                                         MOV_r32_r32( R_EAX, R_ECX );
  1340                                         ADD_imm8s_r32( 4, R_EAX );
  1341                                         store_reg( R_EAX, Rm );
  1342                                         MEM_READ_LONG( R_ECX, R_EAX );
  1343                                         store_spreg( R_EAX, R_SSR );
  1345                                         break;
  1346                                     case 0x4:
  1347                                         { /* LDC.L @Rm+, SPC */
  1348                                         uint32_t Rm = ((ir>>8)&0xF); 
  1349                                         load_reg( R_EAX, Rm );
  1350                                         MOV_r32_r32( R_EAX, R_ECX );
  1351                                         ADD_imm8s_r32( 4, R_EAX );
  1352                                         store_reg( R_EAX, Rm );
  1353                                         MEM_READ_LONG( R_ECX, R_EAX );
  1354                                         store_spreg( R_EAX, R_SPC );
  1356                                         break;
  1357                                     default:
  1358                                         UNDEF();
  1359                                         break;
  1361                                 break;
  1362                             case 0x1:
  1363                                 { /* LDC.L @Rm+, Rn_BANK */
  1364                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1366                                 break;
  1368                         break;
  1369                     case 0x8:
  1370                         switch( (ir&0xF0) >> 4 ) {
  1371                             case 0x0:
  1372                                 { /* SHLL2 Rn */
  1373                                 uint32_t Rn = ((ir>>8)&0xF); 
  1374                                 load_reg( R_EAX, Rn );
  1375                                 SHL_imm8_r32( 2, R_EAX );
  1376                                 store_reg( R_EAX, Rn );
  1378                                 break;
  1379                             case 0x1:
  1380                                 { /* SHLL8 Rn */
  1381                                 uint32_t Rn = ((ir>>8)&0xF); 
  1382                                 load_reg( R_EAX, Rn );
  1383                                 SHL_imm8_r32( 8, R_EAX );
  1384                                 store_reg( R_EAX, Rn );
  1386                                 break;
  1387                             case 0x2:
  1388                                 { /* SHLL16 Rn */
  1389                                 uint32_t Rn = ((ir>>8)&0xF); 
  1390                                 load_reg( R_EAX, Rn );
  1391                                 SHL_imm8_r32( 16, R_EAX );
  1392                                 store_reg( R_EAX, Rn );
  1394                                 break;
  1395                             default:
  1396                                 UNDEF();
  1397                                 break;
  1399                         break;
  1400                     case 0x9:
  1401                         switch( (ir&0xF0) >> 4 ) {
  1402                             case 0x0:
  1403                                 { /* SHLR2 Rn */
  1404                                 uint32_t Rn = ((ir>>8)&0xF); 
  1405                                 load_reg( R_EAX, Rn );
  1406                                 SHR_imm8_r32( 2, R_EAX );
  1407                                 store_reg( R_EAX, Rn );
  1409                                 break;
  1410                             case 0x1:
  1411                                 { /* SHLR8 Rn */
  1412                                 uint32_t Rn = ((ir>>8)&0xF); 
  1413                                 load_reg( R_EAX, Rn );
  1414                                 SHR_imm8_r32( 8, R_EAX );
  1415                                 store_reg( R_EAX, Rn );
  1417                                 break;
  1418                             case 0x2:
  1419                                 { /* SHLR16 Rn */
  1420                                 uint32_t Rn = ((ir>>8)&0xF); 
  1421                                 load_reg( R_EAX, Rn );
  1422                                 SHR_imm8_r32( 16, R_EAX );
  1423                                 store_reg( R_EAX, Rn );
  1425                                 break;
  1426                             default:
  1427                                 UNDEF();
  1428                                 break;
  1430                         break;
  1431                     case 0xA:
  1432                         switch( (ir&0xF0) >> 4 ) {
  1433                             case 0x0:
  1434                                 { /* LDS Rm, MACH */
  1435                                 uint32_t Rm = ((ir>>8)&0xF); 
  1436                                 load_reg( R_EAX, Rm );
  1437                                 store_spreg( R_EAX, R_MACH );
  1439                                 break;
  1440                             case 0x1:
  1441                                 { /* LDS Rm, MACL */
  1442                                 uint32_t Rm = ((ir>>8)&0xF); 
  1443                                 load_reg( R_EAX, Rm );
  1444                                 store_spreg( R_EAX, R_MACL );
  1446                                 break;
  1447                             case 0x2:
  1448                                 { /* LDS Rm, PR */
  1449                                 uint32_t Rm = ((ir>>8)&0xF); 
  1450                                 load_reg( R_EAX, Rm );
  1451                                 store_spreg( R_EAX, R_PR );
  1453                                 break;
  1454                             case 0x3:
  1455                                 { /* LDC Rm, SGR */
  1456                                 uint32_t Rm = ((ir>>8)&0xF); 
  1457                                 load_reg( R_EAX, Rm );
  1458                                 store_spreg( R_EAX, R_SGR );
  1460                                 break;
  1461                             case 0x5:
  1462                                 { /* LDS Rm, FPUL */
  1463                                 uint32_t Rm = ((ir>>8)&0xF); 
  1464                                 load_reg( R_EAX, Rm );
  1465                                 store_spreg( R_EAX, R_FPUL );
  1467                                 break;
  1468                             case 0x6:
  1469                                 { /* LDS Rm, FPSCR */
  1470                                 uint32_t Rm = ((ir>>8)&0xF); 
  1471                                 load_reg( R_EAX, Rm );
  1472                                 store_spreg( R_EAX, R_FPSCR );
  1474                                 break;
  1475                             case 0xF:
  1476                                 { /* LDC Rm, DBR */
  1477                                 uint32_t Rm = ((ir>>8)&0xF); 
  1478                                 load_reg( R_EAX, Rm );
  1479                                 store_spreg( R_EAX, R_DBR );
  1481                                 break;
  1482                             default:
  1483                                 UNDEF();
  1484                                 break;
  1486                         break;
  1487                     case 0xB:
  1488                         switch( (ir&0xF0) >> 4 ) {
  1489                             case 0x0:
  1490                                 { /* JSR @Rn */
  1491                                 uint32_t Rn = ((ir>>8)&0xF); 
  1493                                 break;
  1494                             case 0x1:
  1495                                 { /* TAS.B @Rn */
  1496                                 uint32_t Rn = ((ir>>8)&0xF); 
  1497                                 load_reg( R_ECX, Rn );
  1498                                 MEM_READ_BYTE( R_ECX, R_EAX );
  1499                                 TEST_r8_r8( R_AL, R_AL );
  1500                                 SETE_t();
  1501                                 OR_imm8_r8( 0x80, R_AL );
  1502                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  1504                                 break;
  1505                             case 0x2:
  1506                                 { /* JMP @Rn */
  1507                                 uint32_t Rn = ((ir>>8)&0xF); 
  1509                                 break;
  1510                             default:
  1511                                 UNDEF();
  1512                                 break;
  1514                         break;
  1515                     case 0xC:
  1516                         { /* SHAD Rm, Rn */
  1517                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1518                         /* Annoyingly enough, not directly convertible */
  1519                         load_reg( R_EAX, Rn );
  1520                         load_reg( R_ECX, Rm );
  1521                         CMP_imm32_r32( 0, R_ECX );
  1522                         JAE_rel8(9);
  1524                         NEG_r32( R_ECX );      // 2
  1525                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1526                         SAR_r32_CL( R_EAX );       // 2
  1527                         JMP_rel8(5);               // 2
  1529                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1530                         SHL_r32_CL( R_EAX );       // 2
  1532                         store_reg( R_EAX, Rn );
  1534                         break;
  1535                     case 0xD:
  1536                         { /* SHLD Rm, Rn */
  1537                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1538                         load_reg( R_EAX, Rn );
  1539                         load_reg( R_ECX, Rm );
  1541                         MOV_r32_r32( R_EAX, R_EDX );
  1542                         SHL_r32_CL( R_EAX );
  1543                         NEG_r32( R_ECX );
  1544                         SHR_r32_CL( R_EDX );
  1545                         CMP_imm8s_r32( 0, R_ECX );
  1546                         CMOVAE_r32_r32( R_EDX,  R_EAX );
  1547                         store_reg( R_EAX, Rn );
  1549                         break;
  1550                     case 0xE:
  1551                         switch( (ir&0x80) >> 7 ) {
  1552                             case 0x0:
  1553                                 switch( (ir&0x70) >> 4 ) {
  1554                                     case 0x0:
  1555                                         { /* LDC Rm, SR */
  1556                                         uint32_t Rm = ((ir>>8)&0xF); 
  1557                                         load_reg( R_EAX, Rm );
  1558                                         write_sr( R_EAX );
  1560                                         break;
  1561                                     case 0x1:
  1562                                         { /* LDC Rm, GBR */
  1563                                         uint32_t Rm = ((ir>>8)&0xF); 
  1564                                         load_reg( R_EAX, Rm );
  1565                                         store_spreg( R_EAX, R_GBR );
  1567                                         break;
  1568                                     case 0x2:
  1569                                         { /* LDC Rm, VBR */
  1570                                         uint32_t Rm = ((ir>>8)&0xF); 
  1571                                         load_reg( R_EAX, Rm );
  1572                                         store_spreg( R_EAX, R_VBR );
  1574                                         break;
  1575                                     case 0x3:
  1576                                         { /* LDC Rm, SSR */
  1577                                         uint32_t Rm = ((ir>>8)&0xF); 
  1578                                         load_reg( R_EAX, Rm );
  1579                                         store_spreg( R_EAX, R_SSR );
  1581                                         break;
  1582                                     case 0x4:
  1583                                         { /* LDC Rm, SPC */
  1584                                         uint32_t Rm = ((ir>>8)&0xF); 
  1585                                         load_reg( R_EAX, Rm );
  1586                                         store_spreg( R_EAX, R_SPC );
  1588                                         break;
  1589                                     default:
  1590                                         UNDEF();
  1591                                         break;
  1593                                 break;
  1594                             case 0x1:
  1595                                 { /* LDC Rm, Rn_BANK */
  1596                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1598                                 break;
  1600                         break;
  1601                     case 0xF:
  1602                         { /* MAC.W @Rm+, @Rn+ */
  1603                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1605                         break;
  1607                 break;
  1608             case 0x5:
  1609                 { /* MOV.L @(disp, Rm), Rn */
  1610                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  1611                 load_reg( R_ECX, Rm );
  1612                 ADD_imm8s_r32( disp, R_ECX );
  1613                 MEM_READ_LONG( R_ECX, R_EAX );
  1614                 store_reg( R_EAX, Rn );
  1616                 break;
  1617             case 0x6:
  1618                 switch( ir&0xF ) {
  1619                     case 0x0:
  1620                         { /* MOV.B @Rm, Rn */
  1621                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1622                         load_reg( R_ECX, Rm );
  1623                         MEM_READ_BYTE( R_ECX, R_EAX );
  1624                         store_reg( R_ECX, Rn );
  1626                         break;
  1627                     case 0x1:
  1628                         { /* MOV.W @Rm, Rn */
  1629                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1630                         load_reg( R_ECX, Rm );
  1631                         MEM_READ_WORD( R_ECX, R_EAX );
  1632                         store_reg( R_EAX, Rn );
  1634                         break;
  1635                     case 0x2:
  1636                         { /* MOV.L @Rm, Rn */
  1637                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1638                         load_reg( R_ECX, Rm );
  1639                         MEM_READ_LONG( R_ECX, R_EAX );
  1640                         store_reg( R_EAX, Rn );
  1642                         break;
  1643                     case 0x3:
  1644                         { /* MOV Rm, Rn */
  1645                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1646                         load_reg( R_EAX, Rm );
  1647                         store_reg( R_EAX, Rn );
  1649                         break;
  1650                     case 0x4:
  1651                         { /* MOV.B @Rm+, Rn */
  1652                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1653                         load_reg( R_ECX, Rm );
  1654                         MOV_r32_r32( R_ECX, R_EAX );
  1655                         ADD_imm8s_r32( 1, R_EAX );
  1656                         store_reg( R_EAX, Rm );
  1657                         MEM_READ_BYTE( R_ECX, R_EAX );
  1658                         store_reg( R_EAX, Rn );
  1660                         break;
  1661                     case 0x5:
  1662                         { /* MOV.W @Rm+, Rn */
  1663                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1664                         load_reg( R_EAX, Rm );
  1665                         MOV_r32_r32( R_EAX, R_ECX );
  1666                         ADD_imm8s_r32( 2, R_EAX );
  1667                         store_reg( R_EAX, Rm );
  1668                         MEM_READ_WORD( R_ECX, R_EAX );
  1669                         store_reg( R_EAX, Rn );
  1671                         break;
  1672                     case 0x6:
  1673                         { /* MOV.L @Rm+, Rn */
  1674                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1675                         load_reg( R_EAX, Rm );
  1676                         MOV_r32_r32( R_EAX, R_ECX );
  1677                         ADD_imm8s_r32( 4, R_EAX );
  1678                         store_reg( R_EAX, Rm );
  1679                         MEM_READ_LONG( R_ECX, R_EAX );
  1680                         store_reg( R_EAX, Rn );
  1682                         break;
  1683                     case 0x7:
  1684                         { /* NOT Rm, Rn */
  1685                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1686                         load_reg( R_EAX, Rm );
  1687                         NOT_r32( R_EAX );
  1688                         store_reg( R_EAX, Rn );
  1690                         break;
  1691                     case 0x8:
  1692                         { /* SWAP.B Rm, Rn */
  1693                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1694                         load_reg( R_EAX, Rm );
  1695                         XCHG_r8_r8( R_AL, R_AH );
  1696                         store_reg( R_EAX, Rn );
  1698                         break;
  1699                     case 0x9:
  1700                         { /* SWAP.W Rm, Rn */
  1701                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1702                         load_reg( R_EAX, Rm );
  1703                         MOV_r32_r32( R_EAX, R_ECX );
  1704                         SHL_imm8_r32( 16, R_ECX );
  1705                         SHR_imm8_r32( 16, R_EAX );
  1706                         OR_r32_r32( R_EAX, R_ECX );
  1707                         store_reg( R_ECX, Rn );
  1709                         break;
  1710                     case 0xA:
  1711                         { /* NEGC Rm, Rn */
  1712                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1713                         load_reg( R_EAX, Rm );
  1714                         XOR_r32_r32( R_ECX, R_ECX );
  1715                         LDC_t();
  1716                         SBB_r32_r32( R_EAX, R_ECX );
  1717                         store_reg( R_ECX, Rn );
  1718                         SETC_t();
  1720                         break;
  1721                     case 0xB:
  1722                         { /* NEG Rm, Rn */
  1723                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1724                         load_reg( R_EAX, Rm );
  1725                         NEG_r32( R_EAX );
  1726                         store_reg( R_EAX, Rn );
  1728                         break;
  1729                     case 0xC:
  1730                         { /* EXTU.B Rm, Rn */
  1731                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1732                         load_reg( R_EAX, Rm );
  1733                         MOVZX_r8_r32( R_EAX, R_EAX );
  1734                         store_reg( R_EAX, Rn );
  1736                         break;
  1737                     case 0xD:
  1738                         { /* EXTU.W Rm, Rn */
  1739                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1740                         load_reg( R_EAX, Rm );
  1741                         MOVZX_r16_r32( R_EAX, R_EAX );
  1742                         store_reg( R_EAX, Rn );
  1744                         break;
  1745                     case 0xE:
  1746                         { /* EXTS.B Rm, Rn */
  1747                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1748                         load_reg( R_EAX, Rm );
  1749                         MOVSX_r8_r32( R_EAX, R_EAX );
  1750                         store_reg( R_EAX, Rn );
  1752                         break;
  1753                     case 0xF:
  1754                         { /* EXTS.W Rm, Rn */
  1755                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1756                         load_reg( R_EAX, Rm );
  1757                         MOVSX_r16_r32( R_EAX, R_EAX );
  1758                         store_reg( R_EAX, Rn );
  1760                         break;
  1762                 break;
  1763             case 0x7:
  1764                 { /* ADD #imm, Rn */
  1765                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1766                 load_reg( R_EAX, Rn );
  1767                 ADD_imm8s_r32( imm, R_EAX );
  1768                 store_reg( R_EAX, Rn );
  1770                 break;
  1771             case 0x8:
  1772                 switch( (ir&0xF00) >> 8 ) {
  1773                     case 0x0:
  1774                         { /* MOV.B R0, @(disp, Rn) */
  1775                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1776                         load_reg( R_EAX, 0 );
  1777                         load_reg( R_ECX, Rn );
  1778                         ADD_imm32_r32( disp, R_ECX );
  1779                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  1781                         break;
  1782                     case 0x1:
  1783                         { /* MOV.W R0, @(disp, Rn) */
  1784                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1785                         load_reg( R_ECX, Rn );
  1786                         load_reg( R_EAX, 0 );
  1787                         ADD_imm32_r32( disp, R_ECX );
  1788                         MEM_WRITE_WORD( R_ECX, R_EAX );
  1790                         break;
  1791                     case 0x4:
  1792                         { /* MOV.B @(disp, Rm), R0 */
  1793                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1794                         load_reg( R_ECX, Rm );
  1795                         ADD_imm32_r32( disp, R_ECX );
  1796                         MEM_READ_BYTE( R_ECX, R_EAX );
  1797                         store_reg( R_EAX, 0 );
  1799                         break;
  1800                     case 0x5:
  1801                         { /* MOV.W @(disp, Rm), R0 */
  1802                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1803                         load_reg( R_ECX, Rm );
  1804                         ADD_imm32_r32( disp, R_ECX );
  1805                         MEM_READ_WORD( R_ECX, R_EAX );
  1806                         store_reg( R_EAX, 0 );
  1808                         break;
  1809                     case 0x8:
  1810                         { /* CMP/EQ #imm, R0 */
  1811                         int32_t imm = SIGNEXT8(ir&0xFF); 
  1812                         load_reg( R_EAX, 0 );
  1813                         CMP_imm8s_r32(imm, R_EAX);
  1814                         SETE_t();
  1816                         break;
  1817                     case 0x9:
  1818                         { /* BT disp */
  1819                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1820                         /* If true, result PC += 4 + disp. else result PC = pc+2 */
  1821                           return pc + 2;
  1823                         break;
  1824                     case 0xB:
  1825                         { /* BF disp */
  1826                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1827                         CMP_imm8s_ebp( 0, R_T );
  1828                         JNE_rel8( 1 );
  1829                         exit_block( disp + pc + 4 );
  1830                         return 1;
  1832                         break;
  1833                     case 0xD:
  1834                         { /* BT/S disp */
  1835                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1836                         return pc + 4;
  1838                         break;
  1839                     case 0xF:
  1840                         { /* BF/S disp */
  1841                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1842                         CMP_imm8s_ebp( 0, R_T );
  1843                         JNE_rel8( 1 );
  1844                         exit_block( disp + pc + 4 );
  1845                         sh4_x86.in_delay_slot = TRUE;
  1847                         break;
  1848                     default:
  1849                         UNDEF();
  1850                         break;
  1852                 break;
  1853             case 0x9:
  1854                 { /* MOV.W @(disp, PC), Rn */
  1855                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  1856                 load_imm32( R_ECX, pc + disp + 4 );
  1857                 MEM_READ_WORD( R_ECX, R_EAX );
  1858                 store_reg( R_EAX, Rn );
  1860                 break;
  1861             case 0xA:
  1862                 { /* BRA disp */
  1863                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1864                 exit_block( disp + pc + 4 );
  1866                 break;
  1867             case 0xB:
  1868                 { /* BSR disp */
  1869                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1871                 break;
  1872             case 0xC:
  1873                 switch( (ir&0xF00) >> 8 ) {
  1874                     case 0x0:
  1875                         { /* MOV.B R0, @(disp, GBR) */
  1876                         uint32_t disp = (ir&0xFF); 
  1877                         load_reg( R_EAX, 0 );
  1878                         load_spreg( R_ECX, R_GBR );
  1879                         ADD_imm32_r32( disp, R_ECX );
  1880                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  1882                         break;
  1883                     case 0x1:
  1884                         { /* MOV.W R0, @(disp, GBR) */
  1885                         uint32_t disp = (ir&0xFF)<<1; 
  1886                         load_spreg( R_ECX, R_GBR );
  1887                         load_reg( R_EAX, 0 );
  1888                         ADD_imm32_r32( disp, R_ECX );
  1889                         MEM_WRITE_WORD( R_ECX, R_EAX );
  1891                         break;
  1892                     case 0x2:
  1893                         { /* MOV.L R0, @(disp, GBR) */
  1894                         uint32_t disp = (ir&0xFF)<<2; 
  1895                         load_spreg( R_ECX, R_GBR );
  1896                         load_reg( R_EAX, 0 );
  1897                         ADD_imm32_r32( disp, R_ECX );
  1898                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1900                         break;
  1901                     case 0x3:
  1902                         { /* TRAPA #imm */
  1903                         uint32_t imm = (ir&0xFF); 
  1905                         break;
  1906                     case 0x4:
  1907                         { /* MOV.B @(disp, GBR), R0 */
  1908                         uint32_t disp = (ir&0xFF); 
  1909                         load_spreg( R_ECX, R_GBR );
  1910                         ADD_imm32_r32( disp, R_ECX );
  1911                         MEM_READ_BYTE( R_ECX, R_EAX );
  1912                         store_reg( R_EAX, 0 );
  1914                         break;
  1915                     case 0x5:
  1916                         { /* MOV.W @(disp, GBR), R0 */
  1917                         uint32_t disp = (ir&0xFF)<<1; 
  1918                         load_spreg( R_ECX, R_GBR );
  1919                         ADD_imm32_r32( disp, R_ECX );
  1920                         MEM_READ_WORD( R_ECX, R_EAX );
  1921                         store_reg( R_EAX, 0 );
  1923                         break;
  1924                     case 0x6:
  1925                         { /* MOV.L @(disp, GBR), R0 */
  1926                         uint32_t disp = (ir&0xFF)<<2; 
  1927                         load_spreg( R_ECX, R_GBR );
  1928                         ADD_imm32_r32( disp, R_ECX );
  1929                         MEM_READ_LONG( R_ECX, R_EAX );
  1930                         store_reg( R_EAX, 0 );
  1932                         break;
  1933                     case 0x7:
  1934                         { /* MOVA @(disp, PC), R0 */
  1935                         uint32_t disp = (ir&0xFF)<<2; 
  1936                         load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
  1937                         store_reg( R_ECX, 0 );
  1939                         break;
  1940                     case 0x8:
  1941                         { /* TST #imm, R0 */
  1942                         uint32_t imm = (ir&0xFF); 
  1943                         load_reg( R_EAX, 0 );
  1944                         TEST_imm32_r32( imm, R_EAX );
  1945                         SETE_t();
  1947                         break;
  1948                     case 0x9:
  1949                         { /* AND #imm, R0 */
  1950                         uint32_t imm = (ir&0xFF); 
  1951                         load_reg( R_EAX, 0 );
  1952                         AND_imm32_r32(imm, R_EAX); 
  1953                         store_reg( R_EAX, 0 );
  1955                         break;
  1956                     case 0xA:
  1957                         { /* XOR #imm, R0 */
  1958                         uint32_t imm = (ir&0xFF); 
  1959                         load_reg( R_EAX, 0 );
  1960                         XOR_imm32_r32( imm, R_EAX );
  1961                         store_reg( R_EAX, 0 );
  1963                         break;
  1964                     case 0xB:
  1965                         { /* OR #imm, R0 */
  1966                         uint32_t imm = (ir&0xFF); 
  1967                         load_reg( R_EAX, 0 );
  1968                         OR_imm32_r32(imm, R_EAX);
  1969                         store_reg( R_EAX, 0 );
  1971                         break;
  1972                     case 0xC:
  1973                         { /* TST.B #imm, @(R0, GBR) */
  1974                         uint32_t imm = (ir&0xFF); 
  1975                         load_reg( R_EAX, 0);
  1976                         load_reg( R_ECX, R_GBR);
  1977                         ADD_r32_r32( R_EAX, R_ECX );
  1978                         MEM_READ_BYTE( R_ECX, R_EAX );
  1979                         TEST_imm8_r8( imm, R_EAX );
  1980                         SETE_t();
  1982                         break;
  1983                     case 0xD:
  1984                         { /* AND.B #imm, @(R0, GBR) */
  1985                         uint32_t imm = (ir&0xFF); 
  1986                         load_reg( R_EAX, 0 );
  1987                         load_spreg( R_ECX, R_GBR );
  1988                         ADD_r32_r32( R_EAX, R_EBX );
  1989                         MEM_READ_BYTE( R_ECX, R_EAX );
  1990                         AND_imm32_r32(imm, R_ECX );
  1991                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  1993                         break;
  1994                     case 0xE:
  1995                         { /* XOR.B #imm, @(R0, GBR) */
  1996                         uint32_t imm = (ir&0xFF); 
  1997                         load_reg( R_EAX, 0 );
  1998                         load_spreg( R_ECX, R_GBR );
  1999                         ADD_r32_r32( R_EAX, R_ECX );
  2000                         MEM_READ_BYTE( R_ECX, R_EAX );
  2001                         XOR_imm32_r32( imm, R_EAX );
  2002                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2004                         break;
  2005                     case 0xF:
  2006                         { /* OR.B #imm, @(R0, GBR) */
  2007                         uint32_t imm = (ir&0xFF); 
  2009                         break;
  2011                 break;
  2012             case 0xD:
  2013                 { /* MOV.L @(disp, PC), Rn */
  2014                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2015                 load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
  2016                 MEM_READ_LONG( R_ECX, R_EAX );
  2017                 store_reg( R_EAX, 0 );
  2019                 break;
  2020             case 0xE:
  2021                 { /* MOV #imm, Rn */
  2022                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2023                 load_imm32( R_EAX, imm );
  2024                 store_reg( R_EAX, Rn );
  2026                 break;
  2027             case 0xF:
  2028                 switch( ir&0xF ) {
  2029                     case 0x0:
  2030                         { /* FADD FRm, FRn */
  2031                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2033                         break;
  2034                     case 0x1:
  2035                         { /* FSUB FRm, FRn */
  2036                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2038                         break;
  2039                     case 0x2:
  2040                         { /* FMUL FRm, FRn */
  2041                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2043                         break;
  2044                     case 0x3:
  2045                         { /* FDIV FRm, FRn */
  2046                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2048                         break;
  2049                     case 0x4:
  2050                         { /* FCMP/EQ FRm, FRn */
  2051                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2053                         break;
  2054                     case 0x5:
  2055                         { /* FCMP/GT FRm, FRn */
  2056                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2058                         break;
  2059                     case 0x6:
  2060                         { /* FMOV @(R0, Rm), FRn */
  2061                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2063                         break;
  2064                     case 0x7:
  2065                         { /* FMOV FRm, @(R0, Rn) */
  2066                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2068                         break;
  2069                     case 0x8:
  2070                         { /* FMOV @Rm, FRn */
  2071                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2073                         break;
  2074                     case 0x9:
  2075                         { /* FMOV @Rm+, FRn */
  2076                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2078                         break;
  2079                     case 0xA:
  2080                         { /* FMOV FRm, @Rn */
  2081                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2083                         break;
  2084                     case 0xB:
  2085                         { /* FMOV FRm, @-Rn */
  2086                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2088                         break;
  2089                     case 0xC:
  2090                         { /* FMOV FRm, FRn */
  2091                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2093                         break;
  2094                     case 0xD:
  2095                         switch( (ir&0xF0) >> 4 ) {
  2096                             case 0x0:
  2097                                 { /* FSTS FPUL, FRn */
  2098                                 uint32_t FRn = ((ir>>8)&0xF); 
  2100                                 break;
  2101                             case 0x1:
  2102                                 { /* FLDS FRm, FPUL */
  2103                                 uint32_t FRm = ((ir>>8)&0xF); 
  2105                                 break;
  2106                             case 0x2:
  2107                                 { /* FLOAT FPUL, FRn */
  2108                                 uint32_t FRn = ((ir>>8)&0xF); 
  2110                                 break;
  2111                             case 0x3:
  2112                                 { /* FTRC FRm, FPUL */
  2113                                 uint32_t FRm = ((ir>>8)&0xF); 
  2115                                 break;
  2116                             case 0x4:
  2117                                 { /* FNEG FRn */
  2118                                 uint32_t FRn = ((ir>>8)&0xF); 
  2120                                 break;
  2121                             case 0x5:
  2122                                 { /* FABS FRn */
  2123                                 uint32_t FRn = ((ir>>8)&0xF); 
  2125                                 break;
  2126                             case 0x6:
  2127                                 { /* FSQRT FRn */
  2128                                 uint32_t FRn = ((ir>>8)&0xF); 
  2130                                 break;
  2131                             case 0x7:
  2132                                 { /* FSRRA FRn */
  2133                                 uint32_t FRn = ((ir>>8)&0xF); 
  2135                                 break;
  2136                             case 0x8:
  2137                                 { /* FLDI0 FRn */
  2138                                 uint32_t FRn = ((ir>>8)&0xF); 
  2140                                 break;
  2141                             case 0x9:
  2142                                 { /* FLDI1 FRn */
  2143                                 uint32_t FRn = ((ir>>8)&0xF); 
  2145                                 break;
  2146                             case 0xA:
  2147                                 { /* FCNVSD FPUL, FRn */
  2148                                 uint32_t FRn = ((ir>>8)&0xF); 
  2150                                 break;
  2151                             case 0xB:
  2152                                 { /* FCNVDS FRm, FPUL */
  2153                                 uint32_t FRm = ((ir>>8)&0xF); 
  2155                                 break;
  2156                             case 0xE:
  2157                                 { /* FIPR FVm, FVn */
  2158                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  2160                                 break;
  2161                             case 0xF:
  2162                                 switch( (ir&0x100) >> 8 ) {
  2163                                     case 0x0:
  2164                                         { /* FSCA FPUL, FRn */
  2165                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  2167                                         break;
  2168                                     case 0x1:
  2169                                         switch( (ir&0x200) >> 9 ) {
  2170                                             case 0x0:
  2171                                                 { /* FTRV XMTRX, FVn */
  2172                                                 uint32_t FVn = ((ir>>10)&0x3); 
  2174                                                 break;
  2175                                             case 0x1:
  2176                                                 switch( (ir&0xC00) >> 10 ) {
  2177                                                     case 0x0:
  2178                                                         { /* FSCHG */
  2180                                                         break;
  2181                                                     case 0x2:
  2182                                                         { /* FRCHG */
  2184                                                         break;
  2185                                                     case 0x3:
  2186                                                         { /* UNDEF */
  2188                                                         break;
  2189                                                     default:
  2190                                                         UNDEF();
  2191                                                         break;
  2193                                                 break;
  2195                                         break;
  2197                                 break;
  2198                             default:
  2199                                 UNDEF();
  2200                                 break;
  2202                         break;
  2203                     case 0xE:
  2204                         { /* FMAC FR0, FRm, FRn */
  2205                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2207                         break;
  2208                     default:
  2209                         UNDEF();
  2210                         break;
  2212                 break;
  2215     INC_r32(R_ESI);
  2217     return 0;
.