lxdream.org :: lxdream/src/pvr2/pvr2.c r674:377d987db8f2

tree revision 674:377d987db8f2

filename	src/pvr2/pvr2.c
changeset	674:377d987db8f2
prev	669:ab344e42bca9
next	677:3ee62740ff8f
author	nkeynes
date	Mon May 26 10:42:18 2008 +0000 (15 years ago)
permissions	-rw-r--r--
last change	Fix save states for x86-64, and ensure compatibility between 32-bit and 64-bit versions

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     1 /**

     2  * $Id$

     3  *

     4  * PVR2 (Video) Core module implementation and MMIO registers.

     5  *

     6  * Copyright (c) 2005 Nathan Keynes.

     7  *

     8  * This program is free software; you can redistribute it and/or modify

     9  * it under the terms of the GNU General Public License as published by

    10  * the Free Software Foundation; either version 2 of the License, or

    11  * (at your option) any later version.

    12  *

    13  * This program is distributed in the hope that it will be useful,

    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    16  * GNU General Public License for more details.

    17  */

    18 #define MODULE pvr2_module

    20 #include <assert.h>

    21 #include "dream.h"

    22 #include "eventq.h"

    23 #include "display.h"

    24 #include "mem.h"

    25 #include "asic.h"

    26 #include "clock.h"

    27 #include "pvr2/pvr2.h"

    28 #include "pvr2/scene.h"

    29 #include "sh4/sh4.h"

    30 #define MMIO_IMPL

    31 #include "pvr2/pvr2mmio.h"

    33 unsigned char *video_base;

    35 #define MAX_RENDER_BUFFERS 4

    37 #define HPOS_PER_FRAME 0

    38 #define HPOS_PER_LINECOUNT 1

    40 static void pvr2_init( void );

    41 static void pvr2_reset( void );

    42 static uint32_t pvr2_run_slice( uint32_t );

    43 static void pvr2_save_state( FILE *f );

    44 static int pvr2_load_state( FILE *f );

    45 static void pvr2_update_raster_posn( uint32_t nanosecs );

    46 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );

    47 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );

    48 static render_buffer_t pvr2_next_render_buffer( );

    49 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );

    50 uint32_t pvr2_get_sync_status();

    52 void pvr2_display_frame( void );

    54 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };

    56 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,

    57 					pvr2_run_slice, NULL,

    58 					pvr2_save_state, pvr2_load_state };

    61 display_driver_t display_driver = NULL;

    63 struct pvr2_state {

    64     uint32_t frame_count;

    65     uint32_t line_count;

    66     uint32_t line_remainder;

    67     uint32_t cycles_run; /* Cycles already executed prior to main time slice */

    68     uint32_t irq_hpos_line;

    69     uint32_t irq_hpos_line_count;

    70     uint32_t irq_hpos_mode;

    71     uint32_t irq_hpos_time_ns; /* Time within the line */

    72     uint32_t irq_vpos1;

    73     uint32_t irq_vpos2;

    74     uint32_t odd_even_field; /* 1 = odd, 0 = even */

    75     int32_t palette_changed; /* TRUE if palette has changed since last render */

    76     uint32_t padding; /* FIXME: Remove in next DST version */

    77     /* timing */

    78     uint32_t dot_clock;

    79     uint32_t total_lines;

    80     uint32_t line_size;

    81     uint32_t line_time_ns;

    82     uint32_t vsync_lines;

    83     uint32_t hsync_width_ns;

    84     uint32_t front_porch_ns;

    85     uint32_t back_porch_ns;

    86     uint32_t retrace_start_line;

    87     uint32_t retrace_end_line;

    88     int32_t interlaced;

    89 } pvr2_state;

    91 static gchar *save_next_render_filename;

    92 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];

    93 static uint32_t render_buffer_count = 0;

    94 static render_buffer_t displayed_render_buffer = NULL;

    95 static uint32_t displayed_border_colour = 0;

    97 /**

    98  * Event handler for the hpos callback

    99  */

   100 static void pvr2_hpos_callback( int eventid ) {

   101     asic_event( eventid );

   102     pvr2_update_raster_posn(sh4r.slice_cycle);

   103     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {

   104 	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;

   105 	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   106 	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   107 	}

   108     }

   109     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,

   110 				  pvr2_state.irq_hpos_time_ns );

   111 }

   113 /**

   114  * Event handler for the scanline callbacks. Fires the corresponding

   115  * ASIC event, and resets the timer for the next field.

   116  */

   117 static void pvr2_scanline_callback( int eventid ) {

   118     asic_event( eventid );

   119     pvr2_update_raster_posn(sh4r.slice_cycle);

   120     if( eventid == EVENT_SCANLINE1 ) {

   121 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );

   122     } else {

   123 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );

   124     }

   125 }

   127 static void pvr2_init( void )

   128 {

   129     int i;

   130     register_io_region( &mmio_region_PVR2 );

   131     register_io_region( &mmio_region_PVR2PAL );

   132     register_io_region( &mmio_region_PVR2TA );

   133     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );

   134     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );

   135     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );

   136     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );

   137     texcache_init();

   138     pvr2_reset();

   139     pvr2_ta_reset();

   140     save_next_render_filename = NULL;

   141     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {

   142 	render_buffers[i] = NULL;

   143     }

   144     render_buffer_count = 0;

   145     displayed_render_buffer = NULL;

   146     displayed_border_colour = 0;

   147 }

   149 static void pvr2_reset( void )

   150 {

   151     int i;

   152     pvr2_state.line_count = 0;

   153     pvr2_state.line_remainder = 0;

   154     pvr2_state.cycles_run = 0;

   155     pvr2_state.irq_vpos1 = 0;

   156     pvr2_state.irq_vpos2 = 0;

   157     pvr2_state.dot_clock = PVR2_DOT_CLOCK;

   158     pvr2_state.back_porch_ns = 4000;

   159     pvr2_state.palette_changed = FALSE;

   160     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );

   161     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );

   162     mmio_region_PVR2_write( YUV_ADDR, 0 );

   163     mmio_region_PVR2_write( YUV_CFG, 0 );

   165     pvr2_ta_init();

   166     texcache_flush();

   167     if( display_driver ) {

   168 	display_driver->display_blank(0);

   169 	for( i=0; i<render_buffer_count; i++ ) {

   170 	    display_driver->destroy_render_buffer(render_buffers[i]);

   171 	    render_buffers[i] = NULL;

   172 	}

   173 	render_buffer_count = 0;

   174     }

   175 }

   177 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )

   178 {

   179     struct frame_buffer fbuf;

   181     fbuf.width = buffer->width;

   182     fbuf.height = buffer->height;

   183     fbuf.rowstride = fbuf.width*3;

   184     fbuf.colour_format = COLFMT_BGR888;

   185     fbuf.inverted = buffer->inverted;

   186     fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );

   188     display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );

   189     write_png_to_stream( f, &fbuf );

   190     g_free( fbuf.data );

   192     fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );

   193     fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );

   194     fwrite( &buffer->address, sizeof(buffer->address), 1, f );

   195     fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );

   196     int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency

   197     fwrite( &flushed, sizeof(flushed), 1, f );

   199 }

   201 render_buffer_t pvr2_load_render_buffer( FILE *f )

   202 {

   203     frame_buffer_t frame = read_png_from_stream( f );

   204     if( frame == NULL ) {

   205 	return NULL;

   206     }

   208     render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);

   209     if( buffer != NULL ) {

   210         int32_t flushed;

   211 	fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );

   212 	fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );

   213 	fread( &buffer->address, sizeof(buffer->address), 1, f );

   214 	fread( &buffer->scale, sizeof(buffer->scale), 1, f );

   215 	fread( &flushed, sizeof(flushed), 1, f );

   216 	buffer->flushed = (gboolean)flushed;

   217     } else {

   218 	fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+

   219 	       sizeof(buffer->address)+sizeof(buffer->scale)+

   220 	       sizeof(int32_t), SEEK_CUR );

   221     }

   222     return buffer;

   223 }

   228 void pvr2_save_render_buffers( FILE *f )

   229 {

   230     int i;

   231     uint32_t has_frontbuffer;

   232     fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );

   233     if( displayed_render_buffer != NULL ) {

   234 	has_frontbuffer = 1;

   235 	fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );

   236 	pvr2_save_render_buffer( f, displayed_render_buffer );

   237     } else {

   238 	has_frontbuffer = 0;

   239 	fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );

   240     }

   242     for( i=0; i<render_buffer_count; i++ ) {

   243 	if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {

   244 	    pvr2_save_render_buffer( f, render_buffers[i] );

   245 	}

   246     }

   247 }

   249 gboolean pvr2_load_render_buffers( FILE *f )

   250 {

   251     uint32_t count, has_frontbuffer;

   252     int i;

   254     fread( &count, sizeof(count), 1, f );

   255     if( count > MAX_RENDER_BUFFERS ) {

   256 	return FALSE;

   257     }

   258     fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );

   259     for( i=0; i<render_buffer_count; i++ ) {

   260 	display_driver->destroy_render_buffer(render_buffers[i]);

   261 	render_buffers[i] = NULL;

   262     }

   263     render_buffer_count = 0;

   265     if( has_frontbuffer ) {

   266 	displayed_render_buffer = pvr2_load_render_buffer(f);

   267 	display_driver->display_render_buffer( displayed_render_buffer );

   268 	count--;

   269     }

   271     for( i=0; i<count; i++ ) {

   272 	pvr2_load_render_buffer( f );

   273     }

   274     return TRUE;

   275 }

   278 static void pvr2_save_state( FILE *f )

   279 {

   280     pvr2_save_render_buffers( f );

   281     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );

   282     pvr2_ta_save_state( f );

   283     pvr2_yuv_save_state( f );

   284 }

   286 static int pvr2_load_state( FILE *f )

   287 {

   288     if( !pvr2_load_render_buffers(f) )

   289 	return 1;

   290     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )

   291 	return 1;

   292     if( pvr2_ta_load_state(f) ) {

   293 	return 1;

   294     }

   295     return pvr2_yuv_load_state(f);

   296 }

   298 /**

   299  * Update the current raster position to the given number of nanoseconds,

   300  * relative to the last time slice. (ie the raster will be adjusted forward

   301  * by nanosecs - nanosecs_already_run_this_timeslice)

   302  */

   303 static void pvr2_update_raster_posn( uint32_t nanosecs )

   304 {

   305     uint32_t old_line_count = pvr2_state.line_count;

   306     if( pvr2_state.line_time_ns == 0 ) {

   307 	return; /* do nothing */

   308     }

   309     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);

   310     pvr2_state.cycles_run = nanosecs;

   311     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {

   312 	pvr2_state.line_count ++;

   313 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;

   314     }

   316     if( pvr2_state.line_count >= pvr2_state.total_lines ) {

   317 	pvr2_state.line_count -= pvr2_state.total_lines;

   318 	if( pvr2_state.interlaced ) {

   319 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;

   320 	}

   321     }

   322     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&

   323 	(old_line_count < pvr2_state.retrace_end_line ||

   324 	 old_line_count > pvr2_state.line_count) ) {

   325 	pvr2_state.frame_count++;

   326 	pvr2_display_frame();

   327     }

   328 }

   330 static uint32_t pvr2_run_slice( uint32_t nanosecs )

   331 {

   332     pvr2_update_raster_posn( nanosecs );

   333     pvr2_state.cycles_run = 0;

   334     return nanosecs;

   335 }

   337 int pvr2_get_frame_count()

   338 {

   339     return pvr2_state.frame_count;

   340 }

   342 render_buffer_t pvr2_get_front_buffer()

   343 {

   344     return displayed_render_buffer;

   345 }

   347 uint32_t pvr2_get_border_colour()

   348 {

   349     return displayed_border_colour;

   350 }

   352 gboolean pvr2_save_next_scene( const gchar *filename )

   353 {

   354     if( save_next_render_filename != NULL ) {

   355 	g_free( save_next_render_filename );

   356     }

   357     save_next_render_filename = g_strdup(filename);

   358     return TRUE;

   359 }

   363 /**

   364  * Display the next frame, copying the current contents of video ram to

   365  * the window. If the video configuration has changed, first recompute the

   366  * new frame size/depth.

   367  */

   368 void pvr2_display_frame( void )

   369 {

   370     int dispmode = MMIO_READ( PVR2, DISP_MODE );

   371     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );

   372     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;

   374     if( display_driver == NULL ) {

   375 	return; /* can't really do anything much */

   376     } else if( !bEnabled ) {

   377 	/* Output disabled == black */

   378 	displayed_render_buffer = NULL;

   379 	displayed_border_colour = 0;

   380 	display_driver->display_blank( 0 );

   381     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {

   382 	/* Enabled but blanked - border colour */

   383 	displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );

   384 	displayed_render_buffer = NULL;

   385 	display_driver->display_blank( displayed_border_colour );

   386     } else {

   387 	/* Real output - determine dimensions etc */

   388 	struct frame_buffer fbuf;

   389 	uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );

   390 	int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);

   391 	int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;

   393 	fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];

   394 	fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;

   395 	fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;

   396 	fbuf.size = vid_ppl << 2 * fbuf.height;

   397 	fbuf.rowstride = (vid_ppl + vid_stride) << 2;

   399 	/* Determine the field to display, and deinterlace if possible */

   400 	if( pvr2_state.interlaced ) {

   401 	    if( vid_ppl == vid_stride ) { /* Magic deinterlace */

   402 		fbuf.height = fbuf.height << 1;

   403 		fbuf.rowstride = vid_ppl << 2;

   404 		fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   405 	    } else {

   406 		/* Just display the field as is, folks. This is slightly tricky -

   407 		 * we pick the field based on which frame is about to come through,

   408 		 * which may not be the same as the odd_even_field.

   409 		 */

   410 		gboolean oddfield = pvr2_state.odd_even_field;

   411 		if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {

   412 		    oddfield = !oddfield;

   413 		}

   414 		if( oddfield ) {

   415 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   416 		} else {

   417 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );

   418 		}

   419 	    }

   420 	} else {

   421 	    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );

   422 	}

   423 	fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;

   424 	fbuf.inverted = FALSE;

   425 	fbuf.data = video_base + (fbuf.address&0x00FFFFFF);

   427 	render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );

   428 	if( rbuf == NULL ) {

   429 	    rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );

   430 	}

   431 	displayed_render_buffer = rbuf;

   432 	if( rbuf != NULL ) {

   433 	    display_driver->display_render_buffer( rbuf );

   434 	}

   435     }

   436 }

   438 /**

   439  * This has to handle every single register individually as they all get masked

   440  * off differently (and its easier to do it at write time)

   441  */

   442 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )

   443 {

   444     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */

   445         MMIO_WRITE( PVR2, reg, val );

   446         return;

   447     }

   449     switch(reg) {

   450     case PVRID:

   451     case PVRVER:

   452     case GUNPOS: /* Read only registers */

   453 	break;

   454     case PVRRESET:

   455 	val &= 0x00000007; /* Do stuff? */

   456 	MMIO_WRITE( PVR2, reg, val );

   457 	break;

   458     case RENDER_START: /* Don't really care what value */

   459 	if( save_next_render_filename != NULL ) {

   460 	    if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {

   461 		INFO( "Saved scene to %s", save_next_render_filename);

   462 	    }

   463 	    g_free( save_next_render_filename );

   464 	    save_next_render_filename = NULL;

   465 	}

   466 	pvr2_scene_read();

   467 	render_buffer_t buffer = pvr2_next_render_buffer();

   468 	if( buffer != NULL ) {

   469 	    pvr2_scene_render( buffer );

   470 	}

   471 	asic_event( EVENT_PVR_RENDER_DONE );

   472 	break;

   473     case RENDER_POLYBASE:

   474     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );

   475     	break;

   476     case RENDER_TSPCFG:

   477     	MMIO_WRITE( PVR2, reg, val&0x00010101 );

   478     	break;

   479     case DISP_BORDER:

   480     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );

   481     	break;

   482     case DISP_MODE:

   483     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );

   484     	break;

   485     case RENDER_MODE:

   486     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );

   487     	break;

   488     case RENDER_SIZE:

   489     	MMIO_WRITE( PVR2, reg, val&0x000001FF );

   490     	break;

   491     case DISP_ADDR1:

   492 	val &= 0x00FFFFFC;

   493 	MMIO_WRITE( PVR2, reg, val );

   494 	pvr2_update_raster_posn(sh4r.slice_cycle);

   495 	break;

   496     case DISP_ADDR2:

   497     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   498 	pvr2_update_raster_posn(sh4r.slice_cycle);

   499     	break;

   500     case DISP_SIZE:

   501     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );

   502     	break;

   503     case RENDER_ADDR1:

   504     case RENDER_ADDR2:

   505     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );

   506     	break;

   507     case RENDER_HCLIP:

   508 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );

   509 	break;

   510     case RENDER_VCLIP:

   511 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   512 	break;

   513     case DISP_HPOSIRQ:

   514 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );

   515 	pvr2_state.irq_hpos_line = val & 0x03FF;

   516 	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;

   517 	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;

   518 	switch( pvr2_state.irq_hpos_mode ) {

   519 	case 3: /* Reserved - treat as 0 */

   520 	case 0: /* Once per frame at specified line */

   521 	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;

   522 	    break;

   523 	case 2: /* Once per line - as per-line-count */

   524 	    pvr2_state.irq_hpos_line = 1;

   525 	    pvr2_state.irq_hpos_mode = 1;

   526 	case 1: /* Once per N lines */

   527 	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;

   528 	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +

   529 		pvr2_state.irq_hpos_line_count;

   530 	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   531 		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   532 	    }

   533 	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;

   534 	}

   535 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   536 					  pvr2_state.irq_hpos_time_ns );

   537 	break;

   538     case DISP_VPOSIRQ:

   539 	val = val & 0x03FF03FF;

   540 	pvr2_state.irq_vpos1 = (val >> 16);

   541 	pvr2_state.irq_vpos2 = val & 0x03FF;

   542 	pvr2_update_raster_posn(sh4r.slice_cycle);

   543 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   544 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   545 	MMIO_WRITE( PVR2, reg, val );

   546 	break;

   547     case RENDER_NEARCLIP:

   548 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );

   549 	break;

   550     case RENDER_SHADOW:

   551 	MMIO_WRITE( PVR2, reg, val&0x000001FF );

   552 	break;

   553     case RENDER_OBJCFG:

   554     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   555     	break;

   556     case RENDER_TSPCLIP:

   557     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );

   558     	break;

   559     case RENDER_FARCLIP:

   560 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );

   561 	break;

   562     case RENDER_BGPLANE:

   563     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   564     	break;

   565     case RENDER_ISPCFG:

   566     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );

   567     	break;

   568     case VRAM_CFG1:

   569 	MMIO_WRITE( PVR2, reg, val&0x000000FF );

   570 	break;

   571     case VRAM_CFG2:

   572 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   573 	break;

   574     case VRAM_CFG3:

   575 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   576 	break;

   577     case RENDER_FOGTBLCOL:

   578     case RENDER_FOGVRTCOL:

   579 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );

   580 	break;

   581     case RENDER_FOGCOEFF:

   582 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   583 	break;

   584     case RENDER_CLAMPHI:

   585     case RENDER_CLAMPLO:

   586 	MMIO_WRITE( PVR2, reg, val );

   587 	break;

   588     case RENDER_TEXSIZE:

   589 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );

   590 	break;

   591     case RENDER_PALETTE:

   592 	MMIO_WRITE( PVR2, reg, val&0x00000003 );

   593 	break;

   594     case RENDER_ALPHA_REF:

   595 	MMIO_WRITE( PVR2, reg, val&0x000000FF );

   596 	break;

   597 	/********** CRTC registers *************/

   598     case DISP_HBORDER:

   599     case DISP_VBORDER:

   600 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   601 	break;

   602     case DISP_TOTAL:

   603 	val = val & 0x03FF03FF;

   604 	MMIO_WRITE( PVR2, reg, val );

   605 	pvr2_update_raster_posn(sh4r.slice_cycle);

   606 	pvr2_state.total_lines = (val >> 16) + 1;

   607 	pvr2_state.line_size = (val & 0x03FF) + 1;

   608 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;

   609 	pvr2_state.retrace_end_line = 0x2A;

   610 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;

   611 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   612 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   613 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   614 					  pvr2_state.irq_hpos_time_ns );

   615 	break;

   616     case DISP_SYNCCFG:

   617 	MMIO_WRITE( PVR2, reg, val&0x000003FF );

   618 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;

   619 	break;

   620     case DISP_SYNCTIME:

   621 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;

   622 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;

   623 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );

   624 	break;

   625     case DISP_CFG2:

   626 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );

   627 	break;

   628     case DISP_HPOS:

   629 	val = val & 0x03FF;

   630 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;

   631 	MMIO_WRITE( PVR2, reg, val );

   632 	break;

   633     case DISP_VPOS:

   634 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   635 	break;

   637 	/*********** Tile accelerator registers ***********/

   638     case TA_POLYPOS:

   639     case TA_LISTPOS:

   640 	/* Readonly registers */

   641 	break;

   642     case TA_TILEBASE:

   643     case TA_LISTEND:

   644     case TA_LISTBASE:

   645 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );

   646 	break;

   647     case RENDER_TILEBASE:

   648     case TA_POLYBASE:

   649     case TA_POLYEND:

   650 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   651 	break;

   652     case TA_TILESIZE:

   653 	MMIO_WRITE( PVR2, reg, val&0x000F003F );

   654 	break;

   655     case TA_TILECFG:

   656 	MMIO_WRITE( PVR2, reg, val&0x00133333 );

   657 	break;

   658     case TA_INIT:

   659 	if( val & 0x80000000 )

   660 	    pvr2_ta_init();

   661 	break;

   662     case TA_REINIT:

   663 	break;

   664 	/**************** Scaler registers? ****************/

   665     case RENDER_SCALER:

   666 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );

   667 	break;

   669     case YUV_ADDR:

   670 	val = val & 0x00FFFFF8;

   671 	MMIO_WRITE( PVR2, reg, val );

   672 	pvr2_yuv_init( val );

   673 	break;

   674     case YUV_CFG:

   675 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );

   676 	pvr2_yuv_set_config(val);

   677 	break;

   679 	/**************** Unknowns ***************/

   680     case PVRUNK1:

   681     	MMIO_WRITE( PVR2, reg, val&0x000007FF );

   682     	break;

   683     case PVRUNK2:

   684 	MMIO_WRITE( PVR2, reg, val&0x00000007 );

   685 	break;

   686     case PVRUNK3:

   687 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );

   688 	break;

   689     case PVRUNK5:

   690 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   691 	break;

   692     case PVRUNK7:

   693 	MMIO_WRITE( PVR2, reg, val&0x00000001 );

   694 	break;

   695     }

   696 }

   698 /**

   699  * Calculate the current read value of the syncstat register, using

   700  * the current SH4 clock time as an offset from the last timeslice.

   701  * The register reads (LSB to MSB) as:

   702  *     0..9  Current scan line

   703  *     10    Odd/even field (1 = odd, 0 = even)

   704  *     11    Display active (including border and overscan)

   705  *     12    Horizontal sync off

   706  *     13    Vertical sync off

   707  * Note this method is probably incorrect for anything other than straight

   708  * interlaced PAL/NTSC, and needs further testing.

   709  */

   710 uint32_t pvr2_get_sync_status()

   711 {

   712     pvr2_update_raster_posn(sh4r.slice_cycle);

   713     uint32_t result = pvr2_state.line_count;

   715     if( pvr2_state.odd_even_field ) {

   716 	result |= 0x0400;

   717     }

   718     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {

   719 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {

   720 	    result |= 0x1000; /* !HSYNC */

   721 	}

   722 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   723 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {

   724 		result |= 0x2800; /* Display active */

   725 	    } else {

   726 		result |= 0x2000; /* Front porch */

   727 	    }

   728 	}

   729     } else {

   730 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   731 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {

   732 		result |= 0x3800; /* Display active */

   733 	    } else {

   734 		result |= 0x3000;

   735 	    }

   736 	} else {

   737 	    result |= 0x1000; /* Back porch */

   738 	}

   739     }

   740     return result;

   741 }

   743 /**

   744  * Schedule a "scanline" event. This actually goes off at

   745  * 2 * line in even fields and 2 * line + 1 in odd fields.

   746  * Otherwise this behaves as per pvr2_schedule_line_event().

   747  * The raster position should be updated before calling this

   748  * method.

   749  * @param eventid Event to fire at the specified time

   750  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced

   751  *  displays).

   752  * @param hpos_ns Nanoseconds into the line at which to fire.

   753  */

   754 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )

   755 {

   756     uint32_t field = pvr2_state.odd_even_field;

   757     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {

   758 	field = !field;

   759     }

   760     if( hpos_ns > pvr2_state.line_time_ns ) {

   761 	hpos_ns = pvr2_state.line_time_ns;

   762     }

   764     line <<= 1;

   765     if( field ) {

   766 	line += 1;

   767     }

   769     if( line < pvr2_state.total_lines ) {

   770 	uint32_t lines;

   771 	uint32_t time;

   772 	if( line <= pvr2_state.line_count ) {

   773 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);

   774 	} else {

   775 	    lines = (line - pvr2_state.line_count);

   776 	}

   777 	if( lines <= minimum_lines ) {

   778 	    lines += pvr2_state.total_lines;

   779 	}

   780 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;

   781 	event_schedule( eventid, time );

   782     } else {

   783 	event_cancel( eventid );

   784     }

   785 }

   787 MMIO_REGION_READ_FN( PVR2, reg )

   788 {

   789     switch( reg ) {

   790         case DISP_SYNCSTAT:

   791             return pvr2_get_sync_status();

   792         default:

   793             return MMIO_READ( PVR2, reg );

   794     }

   795 }

   797 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )

   798 {

   799     MMIO_WRITE( PVR2PAL, reg, val );

   800     pvr2_state.palette_changed = TRUE;

   801 }

   803 void pvr2_check_palette_changed()

   804 {

   805     if( pvr2_state.palette_changed ) {

   806 	texcache_invalidate_palette();

   807 	pvr2_state.palette_changed = FALSE;

   808     }

   809 }

   811 MMIO_REGION_READ_DEFFN( PVR2PAL );

   813 void pvr2_set_base_address( uint32_t base )

   814 {

   815     mmio_region_PVR2_write( DISP_ADDR1, base );

   816 }

   821 int32_t mmio_region_PVR2TA_read( uint32_t reg )

   822 {

   823     return 0xFFFFFFFF;

   824 }

   826 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )

   827 {

   828     pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );

   829 }

   831 /**

   832  * Find the render buffer corresponding to the requested output frame

   833  * (does not consider texture renders).

   834  * @return the render_buffer if found, or null if no such buffer.

   835  *

   836  * Note: Currently does not consider "partial matches", ie partial

   837  * frame overlap - it probably needs to do this.

   838  */

   839 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )

   840 {

   841     int i;

   842     for( i=0; i<render_buffer_count; i++ ) {

   843 	if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {

   844 	    return render_buffers[i];

   845 	}

   846     }

   847     return NULL;

   848 }

   850 /**

   851  * Allocate a render buffer with the requested parameters.

   852  * The order of preference is:

   853  *   1. An existing buffer with the same address. (not flushed unless the new

   854  * size is smaller than the old one).

   855  *   2. An existing buffer with the same size chosen by LRU order. Old buffer

   856  *       is flushed to vram.

   857  *   3. A new buffer if one can be created.

   858  *   4. The current display buff

   859  * Note: The current display field(s) will never be overwritten except as a last

   860  * resort.

   861  */

   862 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )

   863 {

   864     int i;

   865     render_buffer_t result = NULL;

   867     /* Check existing buffers for an available buffer */

   868     for( i=0; i<render_buffer_count; i++ ) {

   869 	if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {

   870 	    /* needs to be the right dimensions */

   871 	    if( render_buffers[i]->address == render_addr ) {

   872 		if( displayed_render_buffer == render_buffers[i] ) {

   873 		    /* Same address, but we can't use it because the

   874 		     * display has it. Mark it as unaddressed for later.

   875 		     */

   876 		    render_buffers[i]->address = -1;

   877 		} else {

   878 		    /* perfect */

   879 		    result = render_buffers[i];

   880 		    break;

   881 		}

   882 	    } else if( render_buffers[i]->address == -1 && result == NULL &&

   883 		       displayed_render_buffer != render_buffers[i] ) {

   884 		result = render_buffers[i];

   885 	    }

   887 	} else if( render_buffers[i]->address == render_addr ) {

   888 	    /* right address, wrong size - if it's larger, flush it, otherwise

   889 	     * nuke it quietly */

   890 	    if( render_buffers[i]->width * render_buffers[i]->height >

   891 		width*height ) {

   892 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );

   893 	    }

   894 	    render_buffers[i]->address = -1;

   895 	}

   896     }

   898     /* Nothing available - make one */

   899     if( result == NULL ) {

   900 	if( render_buffer_count == MAX_RENDER_BUFFERS ) {

   901 	    /* maximum buffers reached - need to throw one away */

   902 	    uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );

   903 	    uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );

   904 	    for( i=0; i<render_buffer_count; i++ ) {

   905 		if( render_buffers[i]->address != field1_addr &&

   906 		    render_buffers[i]->address != field2_addr &&

   907 		    render_buffers[i] != displayed_render_buffer ) {

   908 		    /* Never throw away the current "front buffer(s)" */

   909 		    result = render_buffers[i];

   910 		    if( !result->flushed ) {

   911 			pvr2_render_buffer_copy_to_sh4( result );

   912 		    }

   913 		    if( result->width != width || result->height != height ) {

   914 			display_driver->destroy_render_buffer(render_buffers[i]);

   915 			result = display_driver->create_render_buffer(width,height);

   916 			render_buffers[i] = result;

   917 		    }

   918 		    break;

   919 		}

   920 	    }

   921 	} else {

   922 	    result = display_driver->create_render_buffer(width,height);

   923 	    if( result != NULL ) {

   924 		render_buffers[render_buffer_count++] = result;

   925 	    }

   926 	}

   927     }

   929     if( result != NULL ) {

   930 	result->address = render_addr;

   931     }

   932     return result;

   933 }

   935 /**

   936  * Allocate a render buffer based on the current rendering settings

   937  */

   938 render_buffer_t pvr2_next_render_buffer()

   939 {

   940     render_buffer_t result = NULL;

   941     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );

   942     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );

   943     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );

   944     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;

   946     if( render_addr & 0x01000000 ) { /* vram64 */

   947 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;

   948     } else { /* vram32 */

   949 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;

   950     }

   952     int width = pvr2_scene_buffer_width();

   953     int height = pvr2_scene_buffer_height();

   954     int colour_format = pvr2_render_colour_format[render_mode&0x07];

   956     result = pvr2_alloc_render_buffer( render_addr, width, height );

   957     /* Setup the buffer */

   958     if( result != NULL ) {

   959 	result->rowstride = render_stride;

   960 	result->colour_format = colour_format;

   961 	result->scale = render_scale;

   962 	result->size = width * height * colour_formats[colour_format].bpp;

   963 	result->flushed = FALSE;

   964 	result->inverted = TRUE; // render buffers are inverted normally

   965     }

   966     return result;

   967 }

   969 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )

   970 {

   971     render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );

   972     if( result != NULL ) {

   973 	int bpp = colour_formats[frame->colour_format].bpp;

   974 	result->rowstride = frame->rowstride;

   975 	result->colour_format = frame->colour_format;

   976 	result->scale = 0x400;

   977 	result->size = frame->width * frame->height * bpp;

   978 	result->flushed = TRUE;

   979 	result->inverted = frame->inverted;

   980 	display_driver->load_frame_buffer( frame, result );

   981     }

   982     return result;

   983 }

   986 /**

   987  * Invalidate any caching on the supplied address. Specifically, if it falls

   988  * within any of the render buffers, flush the buffer back to PVR2 ram.

   989  */

   990 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )

   991 {

   992     int i;

   993     address = address & 0x1FFFFFFF;

   994     for( i=0; i<render_buffer_count; i++ ) {

   995 	uint32_t bufaddr = render_buffers[i]->address;

   996 	if( bufaddr != -1 && bufaddr <= address &&

   997 	    (bufaddr + render_buffers[i]->size) > address ) {

   998 	    if( !render_buffers[i]->flushed ) {

   999 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );

  1000 		render_buffers[i]->flushed = TRUE;

  1001 	    }

  1002 	    if( isWrite ) {

  1003 		render_buffers[i]->address = -1; /* Invalid */

  1004 	    }

  1005 	    return TRUE; /* should never have overlapping buffers */

  1006 	}

  1007     }

  1008     return FALSE;

  1009 }