2 * $Id: asic.c,v 1.12 2006-02-15 13:11:42 nkeynes Exp $
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE asic_module
27 #include "dreamcast.h"
28 #include "maple/maple.h"
29 #include "gdrom/ide.h"
35 * 1) Does changing the mask after event occurance result in the
36 * interrupt being delivered immediately?
37 * TODO: Logic diagram of ASIC event/interrupt logic.
39 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
40 * practically nothing is publicly known...
43 struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
46 void asic_check_cleared_events( void );
48 void asic_init( void )
50 register_io_region( &mmio_region_ASIC );
51 register_io_region( &mmio_region_EXTDMA );
52 mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
53 asic_event( EVENT_GDROM_CMD );
56 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
62 /* Clear any interrupts */
63 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
64 asic_check_cleared_events();
67 MMIO_WRITE( ASIC, reg, val );
69 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
70 WARN( "Maple request initiated at %08X, halting", maple_addr );
71 maple_handle_buffer( maple_addr );
72 MMIO_WRITE( ASIC, reg, 0 );
75 case PVRDMACTL: /* Initiate PVR DMA transfer */
76 MMIO_WRITE( ASIC, reg, val );
77 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
78 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
80 uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
81 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
82 char *data = alloca( count );
83 uint32_t rcount = DMAC_get_buffer( 2, data, count );
85 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
86 mem_copy_to_sh4( dest_addr, data, rcount );
87 asic_event( EVENT_PVR_DMA );
91 MMIO_WRITE( ASIC, reg, val );
92 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
93 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
97 int32_t mmio_region_ASIC_read( uint32_t reg )
118 val = MMIO_READ(ASIC, reg);
119 // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
120 // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
123 return 0; /* find out later if there's any cases we actually need to care about */
125 val = MMIO_READ(ASIC, reg);
126 WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
127 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
133 void asic_event( int event )
135 int offset = ((event&0x60)>>3);
136 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
138 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
139 intc_raise_interrupt( INT_IRQ13 );
140 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
141 intc_raise_interrupt( INT_IRQ11 );
142 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
143 intc_raise_interrupt( INT_IRQ9 );
146 void asic_check_cleared_events( )
148 int i, setA = 0, setB = 0, setC = 0;
150 for( i=0; i<3; i++ ) {
151 bits = MMIO_READ( ASIC, PIRQ0 + i );
152 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
153 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
154 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
157 intc_clear_interrupt( INT_IRQ13 );
159 intc_clear_interrupt( INT_IRQ11 );
161 intc_clear_interrupt( INT_IRQ9 );
165 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
168 case IDEALTSTATUS: /* Device control */
169 ide_write_control( val );
172 ide_write_data_pio( val );
175 if( ide_can_write_regs() )
176 idereg.feature = (uint8_t)val;
179 if( ide_can_write_regs() )
180 idereg.count = (uint8_t)val;
183 if( ide_can_write_regs() )
184 idereg.lba0 = (uint8_t)val;
187 if( ide_can_write_regs() )
188 idereg.lba1 = (uint8_t)val;
191 if( ide_can_write_regs() )
192 idereg.lba2 = (uint8_t)val;
195 if( ide_can_write_regs() )
196 idereg.device = (uint8_t)val;
199 if( ide_can_write_regs() ) {
200 ide_clear_interrupt();
201 ide_write_command( (uint8_t)val );
205 WARN( "EXTDMA write %08X <= %08X", reg, val );
207 MMIO_WRITE( EXTDMA, reg, val );
211 MMIO_REGION_READ_FN( EXTDMA, reg )
215 case IDEALTSTATUS: return idereg.status;
216 case IDEDATA: return ide_read_data_pio( );
217 case IDEFEAT: return idereg.error;
218 case IDECOUNT:return idereg.count;
219 case IDELBA0: return idereg.disc;
220 case IDELBA1: return idereg.lba1;
221 case IDELBA2: return idereg.lba2;
222 case IDEDEV: return idereg.device;
224 ide_clear_interrupt();
225 return idereg.status;
227 val = MMIO_READ( EXTDMA, reg );
228 //DEBUG( "EXTDMA read %08X => %08X", reg, val );
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