filename | src/pvr2/pvr2.c |
changeset | 153:3d4091e2b136 |
prev | 151:3d3135644b8e |
next | 159:406161fea392 |
author | nkeynes |
date | Thu Jun 15 10:25:45 2006 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Add P4 I/O tracing Add ability to set I/O trace by region address |
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1 /**
2 * $Id: pvr2.c,v 1.25 2006-05-24 11:48:58 nkeynes Exp $
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include "dream.h"
21 #include "display.h"
22 #include "mem.h"
23 #include "asic.h"
24 #include "pvr2/pvr2.h"
25 #include "sh4/sh4core.h"
26 #define MMIO_IMPL
27 #include "pvr2/pvr2mmio.h"
29 char *video_base;
31 static void pvr2_init( void );
32 static void pvr2_reset( void );
33 static uint32_t pvr2_run_slice( uint32_t );
34 static void pvr2_save_state( FILE *f );
35 static int pvr2_load_state( FILE *f );
37 void pvr2_display_frame( void );
39 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
40 pvr2_run_slice, NULL,
41 pvr2_save_state, pvr2_load_state };
44 display_driver_t display_driver = NULL;
46 struct video_timing {
47 int fields_per_second;
48 int total_lines;
49 int retrace_lines;
50 int line_time_ns;
51 };
53 struct video_timing pal_timing = { 50, 625, 65, 32000 };
54 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
56 struct pvr2_state {
57 uint32_t frame_count;
58 uint32_t line_count;
59 uint32_t line_remainder;
60 uint32_t irq_vpos1;
61 uint32_t irq_vpos2;
62 gboolean retrace;
63 struct video_timing timing;
64 } pvr2_state;
66 struct video_buffer video_buffer[2];
67 int video_buffer_idx = 0;
69 static void pvr2_init( void )
70 {
71 register_io_region( &mmio_region_PVR2 );
72 register_io_region( &mmio_region_PVR2PAL );
73 register_io_region( &mmio_region_PVR2TA );
74 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
75 texcache_init();
76 pvr2_reset();
77 }
79 static void pvr2_reset( void )
80 {
81 pvr2_state.line_count = 0;
82 pvr2_state.line_remainder = 0;
83 pvr2_state.irq_vpos1 = 0;
84 pvr2_state.irq_vpos2 = 0;
85 pvr2_state.retrace = FALSE;
86 pvr2_state.timing = ntsc_timing;
87 video_buffer_idx = 0;
89 pvr2_ta_init();
90 pvr2_render_init();
91 texcache_flush();
92 }
94 static void pvr2_save_state( FILE *f )
95 {
96 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
97 }
99 static int pvr2_load_state( FILE *f )
100 {
101 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
102 return 1;
103 return 0;
104 }
106 static uint32_t pvr2_run_slice( uint32_t nanosecs )
107 {
108 pvr2_state.line_remainder += nanosecs;
109 while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
110 pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
112 pvr2_state.line_count++;
113 if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
114 asic_event( EVENT_RETRACE );
115 pvr2_state.line_count = 0;
116 pvr2_state.retrace = TRUE;
117 }
119 if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
120 asic_event( EVENT_SCANLINE1 );
121 }
122 if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
123 asic_event( EVENT_SCANLINE2 );
124 }
126 if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
127 if( pvr2_state.retrace ) {
128 pvr2_display_frame();
129 pvr2_state.retrace = FALSE;
130 }
131 }
132 }
133 return nanosecs;
134 }
136 int pvr2_get_frame_count()
137 {
138 return pvr2_state.frame_count;
139 }
141 /**
142 * Display the next frame, copying the current contents of video ram to
143 * the window. If the video configuration has changed, first recompute the
144 * new frame size/depth.
145 */
146 void pvr2_display_frame( void )
147 {
148 uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
150 int dispsize = MMIO_READ( PVR2, DISPSIZE );
151 int dispmode = MMIO_READ( PVR2, DISPMODE );
152 int vidcfg = MMIO_READ( PVR2, DISPCFG );
153 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
154 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
155 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
156 gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
157 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
158 if( bEnabled ) {
159 video_buffer_t buffer = &video_buffer[video_buffer_idx];
160 video_buffer_idx = !video_buffer_idx;
161 video_buffer_t last = &video_buffer[video_buffer_idx];
162 buffer->rowstride = (vid_ppl + vid_stride) << 2;
163 buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
164 buffer->vres = vid_lpf;
165 if( interlaced ) buffer->vres <<= 1;
166 switch( (dispmode & DISPMODE_COL) >> 2 ) {
167 case 0:
168 buffer->colour_format = COLFMT_ARGB1555;
169 buffer->hres = vid_ppl << 1;
170 break;
171 case 1:
172 buffer->colour_format = COLFMT_RGB565;
173 buffer->hres = vid_ppl << 1;
174 break;
175 case 2:
176 buffer->colour_format = COLFMT_RGB888;
177 buffer->hres = (vid_ppl << 2) / 3;
178 break;
179 case 3:
180 buffer->colour_format = COLFMT_ARGB8888;
181 buffer->hres = vid_ppl;
182 break;
183 }
185 if( display_driver != NULL ) {
186 if( buffer->hres != last->hres ||
187 buffer->vres != last->vres ||
188 buffer->colour_format != last->colour_format) {
189 display_driver->set_display_format( buffer->hres, buffer->vres,
190 buffer->colour_format );
191 }
192 if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
193 uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
194 display_driver->display_blank_frame( colour );
195 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
196 display_driver->display_frame( buffer );
197 }
198 }
199 } else {
200 video_buffer_idx = 0;
201 video_buffer[0].hres = video_buffer[0].vres = 0;
202 }
203 pvr2_state.frame_count++;
204 }
206 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
207 {
208 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
209 MMIO_WRITE( PVR2, reg, val );
210 /* I don't want to hear about these */
211 return;
212 }
214 if( reg == PVRID ) {
215 ERROR( "Write attempted to readonly register PVRID: ", val );
216 return;
217 }
218 INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val,
219 MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
221 MMIO_WRITE( PVR2, reg, val );
223 switch(reg) {
224 case DISPADDR1:
225 if( pvr2_state.retrace ) {
226 pvr2_display_frame();
227 pvr2_state.retrace = FALSE;
228 }
229 break;
230 case VPOS_IRQ:
231 pvr2_state.irq_vpos1 = (val >> 16) & 0x03FF;
232 pvr2_state.irq_vpos2 = val & 0x03FF;
233 break;
234 case TAINIT:
235 if( val & 0x80000000 )
236 pvr2_ta_init();
237 break;
238 case RENDSTART:
239 if( val == 0xFFFFFFFF )
240 pvr2_render_scene();
241 break;
242 }
243 }
245 MMIO_REGION_READ_FN( PVR2, reg )
246 {
247 switch( reg ) {
248 case BEAMPOS:
249 return sh4r.icount&0x20 ? 0x2000 : 1;
250 default:
251 return MMIO_READ( PVR2, reg );
252 }
253 }
255 MMIO_REGION_DEFFNS( PVR2PAL )
257 void pvr2_set_base_address( uint32_t base )
258 {
259 mmio_region_PVR2_write( DISPADDR1, base );
260 }
265 int32_t mmio_region_PVR2TA_read( uint32_t reg )
266 {
267 return 0xFFFFFFFF;
268 }
270 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
271 {
272 pvr2_ta_write( &val, sizeof(uint32_t) );
273 }
276 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
277 {
278 int bank_flag = (destaddr & 0x04) >> 2;
279 uint32_t *banks[2];
280 uint32_t *dwsrc;
281 int i;
283 destaddr = destaddr & 0x7FFFFF;
284 if( destaddr + length > 0x800000 ) {
285 length = 0x800000 - destaddr;
286 }
288 for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
289 texcache_invalidate_page( i );
290 }
292 banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
293 banks[1] = banks[0] + 0x100000;
294 if( bank_flag )
295 banks[0]++;
297 /* Handle non-aligned start of source */
298 if( destaddr & 0x03 ) {
299 char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
300 for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
301 *dest++ = *src++;
302 }
303 bank_flag = !bank_flag;
304 }
306 dwsrc = (uint32_t *)src;
307 while( length >= 4 ) {
308 *banks[bank_flag]++ = *dwsrc++;
309 bank_flag = !bank_flag;
310 length -= 4;
311 }
313 /* Handle non-aligned end of source */
314 if( length ) {
315 src = (char *)dwsrc;
316 char *dest = (char *)banks[bank_flag];
317 while( length-- > 0 ) {
318 *dest++ = *src++;
319 }
320 }
322 }
324 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
325 {
326 int bank_flag = (srcaddr & 0x04) >> 2;
327 uint32_t *banks[2];
328 uint32_t *dwdest;
329 int i;
331 srcaddr = srcaddr & 0x7FFFFF;
332 if( srcaddr + length > 0x800000 )
333 length = 0x800000 - srcaddr;
335 banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
336 banks[1] = banks[0] + 0x100000;
337 if( bank_flag )
338 banks[0]++;
340 /* Handle non-aligned start of source */
341 if( srcaddr & 0x03 ) {
342 char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
343 for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
344 *dest++ = *src++;
345 }
346 bank_flag = !bank_flag;
347 }
349 dwdest = (uint32_t *)dest;
350 while( length >= 4 ) {
351 *dwdest++ = *banks[bank_flag]++;
352 bank_flag = !bank_flag;
353 length -= 4;
354 }
356 /* Handle non-aligned end of source */
357 if( length ) {
358 dest = (char *)dwdest;
359 char *src = (char *)banks[bank_flag];
360 while( length-- > 0 ) {
361 *dest++ = *src++;
362 }
363 }
364 }
366 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f )
367 {
368 char tmp[length];
369 pvr2_vram64_read( tmp, addr, length );
370 fwrite_dump( tmp, length, f );
371 }
.