lxdream 0.9.1| filename | src/sh4/sh4mmio.c |
| changeset | 92:108450d84ce8 |
| prev | 54:d8b73031289c |
| next | 166:8aa70cf503a2 |
| author | nkeynes |
| date | Thu Jun 15 10:25:45 2006 +0000 (17 years ago) |
| permissions | -rw-r--r-- |
| last change | Add P4 I/O tracing Add ability to set I/O trace by region address |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4mmio.c,v 1.8 2006-02-05 04:02:57 nkeynes Exp $
3 *
4 * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
5 * responsible for including the IMPL side of the SH4 MMIO pages.
6 * Most of these will eventually be split off into their own files.
7 *
8 * Copyright (c) 2005 Nathan Keynes.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20 #define MODULE sh4_module
22 #include "dream.h"
23 #include "mem.h"
24 #include "clock.h"
25 #include "sh4core.h"
26 #include "sh4mmio.h"
27 #define MMIO_IMPL
28 #include "sh4mmio.h"
30 /********************************* MMU *************************************/
32 MMIO_REGION_READ_DEFFN( MMU )
34 #define OCRAM_START (0x1C000000>>PAGE_BITS)
35 #define OCRAM_END (0x20000000>>PAGE_BITS)
37 static char *cache = NULL;
39 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
40 {
41 switch(reg) {
42 case CCR:
43 mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
44 INFO( "Cache mode set to %08X", val );
45 break;
46 default:
47 break;
48 }
49 MMIO_WRITE( MMU, reg, val );
50 }
53 void mmu_init()
54 {
55 cache = mem_alloc_pages(2);
56 }
58 void mmu_set_cache_mode( int mode )
59 {
60 uint32_t i;
61 switch( mode ) {
62 case MEM_OC_INDEX0: /* OIX=0 */
63 for( i=OCRAM_START; i<OCRAM_END; i++ )
64 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
65 break;
66 case MEM_OC_INDEX1: /* OIX=1 */
67 for( i=OCRAM_START; i<OCRAM_END; i++ )
68 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
69 break;
70 default: /* disabled */
71 for( i=OCRAM_START; i<OCRAM_END; i++ )
72 page_map[i] = NULL;
73 break;
74 }
75 }
78 /********************************* BSC *************************************/
80 uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
81 uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
82 uint32_t bsc_output = 0, bsc_input = 0x0300;
84 void bsc_out( int output, int mask )
85 {
86 /* Go figure... The BIOS won't start without this mess though */
87 if( ((output | (~mask)) & 0x03) == 3 ) {
88 bsc_output |= 0x03;
89 } else {
90 bsc_output &= ~0x03;
91 }
92 }
94 void mmio_region_BSC_write( uint32_t reg, uint32_t val )
95 {
96 int i;
97 switch( reg ) {
98 case PCTRA:
99 bsc_input_mask_lo = bsc_output_mask_lo = 0;
100 for( i=0; i<16; i++ ) {
101 int bits = (val >> (i<<1)) & 0x03;
102 if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
103 else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
104 }
105 bsc_output = (bsc_output&0x000F0000) |
106 (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
107 bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
108 bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
109 break;
110 case PCTRB:
111 bsc_input_mask_hi = bsc_output_mask_hi = 0;
112 for( i=0; i<4; i++ ) {
113 int bits = (val >> (i>>1)) & 0x03;
114 if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
115 else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
116 }
117 bsc_output = (bsc_output&0xFFFF) |
118 ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
119 break;
120 case PDTRA:
121 bsc_output = (bsc_output&0x000F0000) |
122 (val & bsc_output_mask_lo );
123 bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
124 bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
125 break;
126 case PDTRB:
127 bsc_output = (bsc_output&0xFFFF) |
128 ( (val & bsc_output_mask_hi)<<16 );
129 break;
130 }
131 WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
132 reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
133 MMIO_WRITE( BSC, reg, val );
134 }
136 int32_t mmio_region_BSC_read( uint32_t reg )
137 {
138 int32_t val;
139 switch( reg ) {
140 case PDTRA:
141 val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
142 break;
143 case PDTRB:
144 val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
145 break;
146 default:
147 val = MMIO_READ( BSC, reg );
148 }
149 WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
150 reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
151 return val;
152 }
154 /********************************* UBC *************************************/
156 MMIO_REGION_STUBFNS( UBC )
159 /********************************** SCI *************************************/
161 MMIO_REGION_STUBFNS( SCI )
.