2 * $Id: pvr2.c,v 1.24 2006-05-23 13:11:09 nkeynes Exp $
4 * PVR2 (Video) Core module implementation and MMIO registers.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #define MODULE pvr2_module
24 #include "pvr2/pvr2.h"
25 #include "sh4/sh4core.h"
27 #include "pvr2/pvr2mmio.h"
31 static void pvr2_init( void );
32 static void pvr2_reset( void );
33 static uint32_t pvr2_run_slice( uint32_t );
34 static void pvr2_save_state( FILE *f );
35 static int pvr2_load_state( FILE *f );
37 void pvr2_display_frame( void );
39 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
41 pvr2_save_state, pvr2_load_state };
44 display_driver_t display_driver = NULL;
47 int fields_per_second;
53 struct video_timing pal_timing = { 50, 625, 65, 32000 };
54 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
59 uint32_t line_remainder;
63 struct video_timing timing;
66 struct video_buffer video_buffer[2];
67 int video_buffer_idx = 0;
69 static void pvr2_init( void )
71 register_io_region( &mmio_region_PVR2 );
72 register_io_region( &mmio_region_PVR2PAL );
73 register_io_region( &mmio_region_PVR2TA );
74 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
79 static void pvr2_reset( void )
81 pvr2_state.line_count = 0;
82 pvr2_state.line_remainder = 0;
83 pvr2_state.irq_vpos1 = 0;
84 pvr2_state.irq_vpos2 = 0;
85 pvr2_state.retrace = FALSE;
86 pvr2_state.timing = ntsc_timing;
94 static void pvr2_save_state( FILE *f )
96 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
99 static int pvr2_load_state( FILE *f )
101 fread( &pvr2_state, sizeof(pvr2_state), 1, f );
104 static uint32_t pvr2_run_slice( uint32_t nanosecs )
106 pvr2_state.line_remainder += nanosecs;
107 while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
108 pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
110 pvr2_state.line_count++;
111 if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
112 asic_event( EVENT_RETRACE );
113 pvr2_state.line_count = 0;
114 pvr2_state.retrace = TRUE;
117 if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
118 asic_event( EVENT_SCANLINE1 );
120 if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
121 asic_event( EVENT_SCANLINE2 );
124 if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
125 if( pvr2_state.retrace ) {
126 pvr2_display_frame();
127 pvr2_state.retrace = FALSE;
134 int pvr2_get_frame_count()
136 return pvr2_state.frame_count;
140 * Display the next frame, copying the current contents of video ram to
141 * the window. If the video configuration has changed, first recompute the
142 * new frame size/depth.
144 void pvr2_display_frame( void )
146 uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
148 int dispsize = MMIO_READ( PVR2, DISPSIZE );
149 int dispmode = MMIO_READ( PVR2, DISPMODE );
150 int vidcfg = MMIO_READ( PVR2, DISPCFG );
151 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
152 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
153 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
154 gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
155 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
157 video_buffer_t buffer = &video_buffer[video_buffer_idx];
158 video_buffer_idx = !video_buffer_idx;
159 video_buffer_t last = &video_buffer[video_buffer_idx];
160 buffer->rowstride = (vid_ppl + vid_stride) << 2;
161 buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
162 buffer->vres = vid_lpf;
163 if( interlaced ) buffer->vres <<= 1;
164 switch( (dispmode & DISPMODE_COL) >> 2 ) {
166 buffer->colour_format = COLFMT_ARGB1555;
167 buffer->hres = vid_ppl << 1;
170 buffer->colour_format = COLFMT_RGB565;
171 buffer->hres = vid_ppl << 1;
174 buffer->colour_format = COLFMT_RGB888;
175 buffer->hres = (vid_ppl << 2) / 3;
178 buffer->colour_format = COLFMT_ARGB8888;
179 buffer->hres = vid_ppl;
183 if( display_driver != NULL ) {
184 if( buffer->hres != last->hres ||
185 buffer->vres != last->vres ||
186 buffer->colour_format != last->colour_format) {
187 display_driver->set_display_format( buffer->hres, buffer->vres,
188 buffer->colour_format );
190 if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
191 uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
192 display_driver->display_blank_frame( colour );
193 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
194 display_driver->display_frame( buffer );
198 video_buffer_idx = 0;
199 video_buffer[0].hres = video_buffer[0].vres = 0;
201 pvr2_state.frame_count++;
204 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
206 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
207 MMIO_WRITE( PVR2, reg, val );
208 /* I don't want to hear about these */
213 ERROR( "Write attempted to readonly register PVRID: ", val );
216 INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val,
217 MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
219 MMIO_WRITE( PVR2, reg, val );
223 if( pvr2_state.retrace ) {
224 pvr2_display_frame();
225 pvr2_state.retrace = FALSE;
229 pvr2_state.irq_vpos1 = (val >> 16) & 0x03FF;
230 pvr2_state.irq_vpos2 = val & 0x03FF;
233 if( val & 0x80000000 )
237 if( val == 0xFFFFFFFF )
243 MMIO_REGION_READ_FN( PVR2, reg )
247 return sh4r.icount&0x20 ? 0x2000 : 1;
249 return MMIO_READ( PVR2, reg );
253 MMIO_REGION_DEFFNS( PVR2PAL )
255 void pvr2_set_base_address( uint32_t base )
257 mmio_region_PVR2_write( DISPADDR1, base );
263 int32_t mmio_region_PVR2TA_read( uint32_t reg )
268 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
270 pvr2_ta_write( &val, sizeof(uint32_t) );
274 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
276 int bank_flag = (destaddr & 0x04) >> 2;
281 destaddr = destaddr & 0x7FFFFF;
282 if( destaddr + length > 0x800000 ) {
283 length = 0x800000 - destaddr;
286 for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
287 texcache_invalidate_page( i );
290 banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
291 banks[1] = banks[0] + 0x100000;
295 /* Handle non-aligned start of source */
296 if( destaddr & 0x03 ) {
297 char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
298 for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
301 bank_flag = !bank_flag;
304 dwsrc = (uint32_t *)src;
305 while( length >= 4 ) {
306 *banks[bank_flag]++ = *dwsrc++;
307 bank_flag = !bank_flag;
311 /* Handle non-aligned end of source */
314 char *dest = (char *)banks[bank_flag];
315 while( length-- > 0 ) {
322 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
324 int bank_flag = (srcaddr & 0x04) >> 2;
329 srcaddr = srcaddr & 0x7FFFFF;
330 if( srcaddr + length > 0x800000 )
331 length = 0x800000 - srcaddr;
333 banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
334 banks[1] = banks[0] + 0x100000;
338 /* Handle non-aligned start of source */
339 if( srcaddr & 0x03 ) {
340 char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
341 for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
344 bank_flag = !bank_flag;
347 dwdest = (uint32_t *)dest;
348 while( length >= 4 ) {
349 *dwdest++ = *banks[bank_flag]++;
350 bank_flag = !bank_flag;
354 /* Handle non-aligned end of source */
356 dest = (char *)dwdest;
357 char *src = (char *)banks[bank_flag];
358 while( length-- > 0 ) {
364 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f )
367 pvr2_vram64_read( tmp, addr, length );
368 fwrite_dump( tmp, length, f );
.