2 * $Id: asic.c,v 1.14 2006-04-30 01:50:13 nkeynes Exp $
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE asic_module
28 #include "dreamcast.h"
29 #include "maple/maple.h"
30 #include "gdrom/ide.h"
36 * 1) Does changing the mask after event occurance result in the
37 * interrupt being delivered immediately?
38 * TODO: Logic diagram of ASIC event/interrupt logic.
40 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
41 * practically nothing is publicly known...
44 struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
47 #define G2_BIT5_TICKS 8
48 #define G2_BIT4_TICKS 16
49 #define G2_BIT0_ON_TICKS 24
50 #define G2_BIT0_OFF_TICKS 24
52 struct asic_g2_state {
53 unsigned int bit5_off_timer;
54 unsigned int bit4_on_timer;
55 unsigned int bit4_off_timer;
56 unsigned int bit0_on_timer;
57 unsigned int bit0_off_timer;
60 /* FIXME: Handle rollover */
61 void asic_g2_write_word()
63 g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
64 if( g2_state.bit4_off_timer < sh4r.icount )
65 g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
66 g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
67 if( g2_state.bit0_off_timer < sh4r.icount ) {
68 g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
69 g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
71 g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
73 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
76 static uint32_t g2_read_status()
78 uint32_t val = MMIO_READ( ASIC, G2STATUS );
79 if( g2_state.bit5_off_timer <= sh4r.icount )
81 if( g2_state.bit4_off_timer <= sh4r.icount )
83 else if( g2_state.bit4_on_timer <= sh4r.icount )
85 if( g2_state.bit0_off_timer <= sh4r.icount )
87 else if( g2_state.bit0_on_timer <= sh4r.icount )
92 void asic_check_cleared_events( void );
94 void asic_init( void )
96 register_io_region( &mmio_region_ASIC );
97 register_io_region( &mmio_region_EXTDMA );
98 mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
101 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
105 val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
109 /* Clear any interrupts */
110 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
111 asic_check_cleared_events();
114 MMIO_WRITE( ASIC, reg, val );
116 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
117 WARN( "Maple request initiated at %08X, halting", maple_addr );
118 maple_handle_buffer( maple_addr );
119 MMIO_WRITE( ASIC, reg, 0 );
122 case PVRDMACTL: /* Initiate PVR DMA transfer */
123 MMIO_WRITE( ASIC, reg, val );
124 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
125 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
127 uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
128 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
129 char *data = alloca( count );
130 uint32_t rcount = DMAC_get_buffer( 2, data, count );
131 if( rcount != count )
132 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
133 mem_copy_to_sh4( dest_addr, data, rcount );
134 asic_event( EVENT_PVR_DMA );
138 MMIO_WRITE( ASIC, reg, val );
139 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
140 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
144 int32_t mmio_region_ASIC_read( uint32_t reg )
165 val = MMIO_READ(ASIC, reg);
166 // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
167 // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
170 return g2_read_status();
172 val = MMIO_READ(ASIC, reg);
173 WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
174 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
180 void asic_event( int event )
182 int offset = ((event&0x60)>>3);
183 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
185 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
186 intc_raise_interrupt( INT_IRQ13 );
187 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
188 intc_raise_interrupt( INT_IRQ11 );
189 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
190 intc_raise_interrupt( INT_IRQ9 );
193 void asic_clear_event( int event ) {
194 int offset = ((event&0x60)>>3);
195 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
196 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
198 asic_check_cleared_events();
201 void asic_check_cleared_events( )
203 int i, setA = 0, setB = 0, setC = 0;
205 for( i=0; i<3; i++ ) {
206 bits = MMIO_READ( ASIC, PIRQ0 + i );
207 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
208 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
209 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
212 intc_clear_interrupt( INT_IRQ13 );
214 intc_clear_interrupt( INT_IRQ11 );
216 intc_clear_interrupt( INT_IRQ9 );
220 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
222 WARN( "EXTDMA write %08X <= %08X", reg, val );
225 case IDEALTSTATUS: /* Device control */
226 ide_write_control( val );
229 ide_write_data_pio( val );
232 if( ide_can_write_regs() )
233 idereg.feature = (uint8_t)val;
236 if( ide_can_write_regs() )
237 idereg.count = (uint8_t)val;
240 if( ide_can_write_regs() )
241 idereg.lba0 = (uint8_t)val;
244 if( ide_can_write_regs() )
245 idereg.lba1 = (uint8_t)val;
248 if( ide_can_write_regs() )
249 idereg.lba2 = (uint8_t)val;
252 if( ide_can_write_regs() )
253 idereg.device = (uint8_t)val;
256 if( ide_can_write_regs() ) {
257 ide_write_command( (uint8_t)val );
262 MMIO_WRITE( EXTDMA, reg, val );
263 if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 &&
264 MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
265 uint32_t target_addr = MMIO_READ( EXTDMA, IDEDMASH4 );
266 uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
267 int dir = MMIO_READ( EXTDMA, IDEDMADIR );
271 MMIO_WRITE( EXTDMA, reg, val );
275 MMIO_REGION_READ_FN( EXTDMA, reg )
279 case IDEALTSTATUS: return idereg.status;
280 case IDEDATA: return ide_read_data_pio( );
281 case IDEFEAT: return idereg.error;
282 case IDECOUNT:return idereg.count;
283 case IDELBA0: return idereg.disc;
284 case IDELBA1: return idereg.lba1;
285 case IDELBA2: return idereg.lba2;
286 case IDEDEV: return idereg.device;
288 return ide_read_status();
290 val = MMIO_READ( EXTDMA, reg );
291 //DEBUG( "EXTDMA read %08X => %08X", reg, val );
.