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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 159:406161fea392
prev153:3d4091e2b136
next161:408b9210395f
author nkeynes
date Thu Jun 15 10:33:08 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Remove superfluous logging
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     1 /**
     2  * $Id: pvr2.c,v 1.26 2006-06-15 10:33:08 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "display.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2/pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2/pvr2mmio.h"
    29 char *video_base;
    31 static void pvr2_init( void );
    32 static void pvr2_reset( void );
    33 static uint32_t pvr2_run_slice( uint32_t );
    34 static void pvr2_save_state( FILE *f );
    35 static int pvr2_load_state( FILE *f );
    37 void pvr2_display_frame( void );
    39 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    40 					pvr2_run_slice, NULL,
    41 					pvr2_save_state, pvr2_load_state };
    44 display_driver_t display_driver = NULL;
    46 struct video_timing {
    47     int fields_per_second;
    48     int total_lines;
    49     int retrace_lines;
    50     int line_time_ns;
    51 };
    53 struct video_timing pal_timing = { 50, 625, 65, 32000 };
    54 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    56 struct pvr2_state {
    57     uint32_t frame_count;
    58     uint32_t line_count;
    59     uint32_t line_remainder;
    60     uint32_t irq_vpos1;
    61     uint32_t irq_vpos2;
    62     gboolean retrace;
    63     struct video_timing timing;
    64 } pvr2_state;
    66 struct video_buffer video_buffer[2];
    67 int video_buffer_idx = 0;
    69 static void pvr2_init( void )
    70 {
    71     register_io_region( &mmio_region_PVR2 );
    72     register_io_region( &mmio_region_PVR2PAL );
    73     register_io_region( &mmio_region_PVR2TA );
    74     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    75     texcache_init();
    76     pvr2_reset();
    77 }
    79 static void pvr2_reset( void )
    80 {
    81     pvr2_state.line_count = 0;
    82     pvr2_state.line_remainder = 0;
    83     pvr2_state.irq_vpos1 = 0;
    84     pvr2_state.irq_vpos2 = 0;
    85     pvr2_state.retrace = FALSE;
    86     pvr2_state.timing = ntsc_timing;
    87     video_buffer_idx = 0;
    89     pvr2_ta_init();
    90     pvr2_render_init();
    91     texcache_flush();
    92 }
    94 static void pvr2_save_state( FILE *f )
    95 {
    96     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
    97 }
    99 static int pvr2_load_state( FILE *f )
   100 {
   101     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   102 	return 1;
   103     return 0;
   104 }
   106 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   107 {
   108     pvr2_state.line_remainder += nanosecs;
   109     while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
   110 	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
   112 	pvr2_state.line_count++;
   113 	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
   114 	    asic_event( EVENT_RETRACE );
   115 	    pvr2_state.line_count = 0;
   116 	    pvr2_state.retrace = TRUE;
   117 	}
   119 	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
   120 	    asic_event( EVENT_SCANLINE1 );
   121 	} 
   122 	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
   123 	    asic_event( EVENT_SCANLINE2 );
   124 	}
   126 	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
   127 	    if( pvr2_state.retrace ) {
   128 		pvr2_display_frame();
   129 		pvr2_state.retrace = FALSE;
   130 	    }
   131 	}
   132     }
   133     return nanosecs;
   134 }
   136 int pvr2_get_frame_count() 
   137 {
   138     return pvr2_state.frame_count;
   139 }
   141 /**
   142  * Display the next frame, copying the current contents of video ram to
   143  * the window. If the video configuration has changed, first recompute the
   144  * new frame size/depth.
   145  */
   146 void pvr2_display_frame( void )
   147 {
   148     uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
   150     int dispsize = MMIO_READ( PVR2, DISPSIZE );
   151     int dispmode = MMIO_READ( PVR2, DISPMODE );
   152     int vidcfg = MMIO_READ( PVR2, DISPCFG );
   153     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   154     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   155     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   156     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   157     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   158     if( bEnabled ) {
   159 	video_buffer_t buffer = &video_buffer[video_buffer_idx];
   160 	video_buffer_idx = !video_buffer_idx;
   161 	video_buffer_t last = &video_buffer[video_buffer_idx];
   162 	buffer->rowstride = (vid_ppl + vid_stride) << 2;
   163 	buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
   164 	buffer->vres = vid_lpf;
   165 	if( interlaced ) buffer->vres <<= 1;
   166 	switch( (dispmode & DISPMODE_COL) >> 2 ) {
   167 	case 0: 
   168 	    buffer->colour_format = COLFMT_ARGB1555;
   169 	    buffer->hres = vid_ppl << 1; 
   170 	    break;
   171 	case 1: 
   172 	    buffer->colour_format = COLFMT_RGB565;
   173 	    buffer->hres = vid_ppl << 1; 
   174 	    break;
   175 	case 2:
   176 	    buffer->colour_format = COLFMT_RGB888;
   177 	    buffer->hres = (vid_ppl << 2) / 3; 
   178 	    break;
   179 	case 3: 
   180 	    buffer->colour_format = COLFMT_ARGB8888;
   181 	    buffer->hres = vid_ppl; 
   182 	    break;
   183 	}
   185 	if( display_driver != NULL ) {
   186 	    if( buffer->hres != last->hres ||
   187 		buffer->vres != last->vres ||
   188 		buffer->colour_format != last->colour_format) {
   189 		display_driver->set_display_format( buffer->hres, buffer->vres,
   190 						  buffer->colour_format );
   191 	    }
   192 	    if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
   193 		uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
   194 		display_driver->display_blank_frame( colour );
   195 	    } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   196 		display_driver->display_frame( buffer );
   197 	    }
   198 	}
   199     } else {
   200 	video_buffer_idx = 0;
   201 	video_buffer[0].hres = video_buffer[0].vres = 0;
   202     }
   203     pvr2_state.frame_count++;
   204 }
   206 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   207 {
   208     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   209         MMIO_WRITE( PVR2, reg, val );
   210         /* I don't want to hear about these */
   211         return;
   212     }
   214     if( reg == PVRID ) {
   215 	ERROR( "Write attempted to readonly register PVRID: ", val );
   216 	return;
   217     }
   219     MMIO_WRITE( PVR2, reg, val );
   221     switch(reg) {
   222     case DISPADDR1:
   223 	if( pvr2_state.retrace ) {
   224 	    pvr2_display_frame();
   225 	    pvr2_state.retrace = FALSE;
   226 	}
   227 	break;
   228     case VPOS_IRQ:
   229 	pvr2_state.irq_vpos1 = (val >> 16) & 0x03FF;
   230 	pvr2_state.irq_vpos2 = val & 0x03FF;
   231 	break;
   232     case TAINIT:
   233 	if( val & 0x80000000 )
   234 	    pvr2_ta_init();
   235 	break;
   236     case RENDSTART:
   237 	if( val == 0xFFFFFFFF )
   238 	    pvr2_render_scene();
   239 	break;
   240     }
   241 }
   243 MMIO_REGION_READ_FN( PVR2, reg )
   244 {
   245     switch( reg ) {
   246         case BEAMPOS:
   247             return sh4r.icount&0x20 ? 0x2000 : 1;
   248         default:
   249             return MMIO_READ( PVR2, reg );
   250     }
   251 }
   253 MMIO_REGION_DEFFNS( PVR2PAL )
   255 void pvr2_set_base_address( uint32_t base ) 
   256 {
   257     mmio_region_PVR2_write( DISPADDR1, base );
   258 }
   263 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   264 {
   265     return 0xFFFFFFFF;
   266 }
   268 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   269 {
   270     pvr2_ta_write( &val, sizeof(uint32_t) );
   271 }
   274 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
   275 {
   276     int bank_flag = (destaddr & 0x04) >> 2;
   277     uint32_t *banks[2];
   278     uint32_t *dwsrc;
   279     int i;
   281     destaddr = destaddr & 0x7FFFFF;
   282     if( destaddr + length > 0x800000 ) {
   283 	length = 0x800000 - destaddr;
   284     }
   286     for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
   287 	texcache_invalidate_page( i );
   288     }
   290     banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
   291     banks[1] = banks[0] + 0x100000;
   292     if( bank_flag ) 
   293 	banks[0]++;
   295     /* Handle non-aligned start of source */
   296     if( destaddr & 0x03 ) {
   297 	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
   298 	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   299 	    *dest++ = *src++;
   300 	}
   301 	bank_flag = !bank_flag;
   302     }
   304     dwsrc = (uint32_t *)src;
   305     while( length >= 4 ) {
   306 	*banks[bank_flag]++ = *dwsrc++;
   307 	bank_flag = !bank_flag;
   308 	length -= 4;
   309     }
   311     /* Handle non-aligned end of source */
   312     if( length ) {
   313 	src = (char *)dwsrc;
   314 	char *dest = (char *)banks[bank_flag];
   315 	while( length-- > 0 ) {
   316 	    *dest++ = *src++;
   317 	}
   318     }  
   320 }
   322 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
   323 {
   324     int bank_flag = (srcaddr & 0x04) >> 2;
   325     uint32_t *banks[2];
   326     uint32_t *dwdest;
   327     int i;
   329     srcaddr = srcaddr & 0x7FFFFF;
   330     if( srcaddr + length > 0x800000 )
   331 	length = 0x800000 - srcaddr;
   333     banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
   334     banks[1] = banks[0] + 0x100000;
   335     if( bank_flag )
   336 	banks[0]++;
   338     /* Handle non-aligned start of source */
   339     if( srcaddr & 0x03 ) {
   340 	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
   341 	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   342 	    *dest++ = *src++;
   343 	}
   344 	bank_flag = !bank_flag;
   345     }
   347     dwdest = (uint32_t *)dest;
   348     while( length >= 4 ) {
   349 	*dwdest++ = *banks[bank_flag]++;
   350 	bank_flag = !bank_flag;
   351 	length -= 4;
   352     }
   354     /* Handle non-aligned end of source */
   355     if( length ) {
   356 	dest = (char *)dwdest;
   357 	char *src = (char *)banks[bank_flag];
   358 	while( length-- > 0 ) {
   359 	    *dest++ = *src++;
   360 	}
   361     }
   362 }
   364 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
   365 {
   366     char tmp[length];
   367     pvr2_vram64_read( tmp, addr, length );
   368     fwrite_dump( tmp, length, f );
   369 }
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