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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 851:41e8ae2c114b
prev850:28782ebbd01d
next856:02ac5f37bfc9
author nkeynes
date Mon Sep 08 11:23:32 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change As long as we've broken save-state compatibility anyway, remove the two FIXME
padding words, and bump the version number
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     1 /**
     2  * $Id$
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include <assert.h>
    21 #include "dream.h"
    22 #include "eventq.h"
    23 #include "display.h"
    24 #include "mem.h"
    25 #include "asic.h"
    26 #include "clock.h"
    27 #include "pvr2/pvr2.h"
    28 #include "pvr2/pvr2mmio.h"
    29 #include "pvr2/scene.h"
    30 #include "sh4/sh4.h"
    31 #define MMIO_IMPL
    32 #include "pvr2/pvr2mmio.h"
    34 unsigned char *video_base;
    36 #define MAX_RENDER_BUFFERS 4
    38 #define HPOS_PER_FRAME 0
    39 #define HPOS_PER_LINECOUNT 1
    41 static void pvr2_init( void );
    42 static void pvr2_reset( void );
    43 static uint32_t pvr2_run_slice( uint32_t );
    44 static void pvr2_save_state( FILE *f );
    45 static int pvr2_load_state( FILE *f );
    46 static void pvr2_update_raster_posn( uint32_t nanosecs );
    47 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
    48 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
    49 static render_buffer_t pvr2_next_render_buffer( );
    50 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
    51 uint32_t pvr2_get_sync_status();
    53 void pvr2_display_frame( void );
    55 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
    57 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    58         pvr2_run_slice, NULL,
    59         pvr2_save_state, pvr2_load_state };
    62 display_driver_t display_driver = NULL;
    64 struct pvr2_state {
    65     uint32_t frame_count;
    66     uint32_t line_count;
    67     uint32_t line_remainder;
    68     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    69     uint32_t irq_hpos_line;
    70     uint32_t irq_hpos_line_count;
    71     uint32_t irq_hpos_mode;
    72     uint32_t irq_hpos_time_ns; /* Time within the line */
    73     uint32_t irq_vpos1;
    74     uint32_t irq_vpos2;
    75     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    76     int32_t palette_changed; /* TRUE if palette has changed since last render */
    77     /* timing */
    78     uint32_t dot_clock;
    79     uint32_t total_lines;
    80     uint32_t line_size;
    81     uint32_t line_time_ns;
    82     uint32_t vsync_lines;
    83     uint32_t hsync_width_ns;
    84     uint32_t front_porch_ns;
    85     uint32_t back_porch_ns;
    86     uint32_t retrace_start_line;
    87     uint32_t retrace_end_line;
    88     int32_t interlaced;
    89 } pvr2_state;
    91 static gchar *save_next_render_filename;
    92 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
    93 static uint32_t render_buffer_count = 0;
    94 static render_buffer_t displayed_render_buffer = NULL;
    95 static uint32_t displayed_border_colour = 0;
    97 /**
    98  * Event handler for the hpos callback
    99  */
   100 static void pvr2_hpos_callback( int eventid ) {
   101     asic_event( eventid );
   102     pvr2_update_raster_posn(sh4r.slice_cycle);
   103     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
   104         pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
   105         while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   106             pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   107         }
   108     }
   109     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
   110                                   pvr2_state.irq_hpos_time_ns );
   111 }
   113 /**
   114  * Event handler for the scanline callbacks. Fires the corresponding
   115  * ASIC event, and resets the timer for the next field.
   116  */
   117 static void pvr2_scanline_callback( int eventid ) 
   118 {
   119     asic_event( eventid );
   120     pvr2_update_raster_posn(sh4r.slice_cycle);
   121     if( eventid == EVENT_SCANLINE1 ) {
   122         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
   123     } else {
   124         pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
   125     }
   126 }
   128 static void pvr2_gunpos_callback( int eventid ) 
   129 {
   130     pvr2_update_raster_posn(sh4r.slice_cycle);
   131     int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
   132     MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
   133     asic_event( EVENT_MAPLE_DMA );
   134 }
   136 static void pvr2_init( void )
   137 {
   138     int i;
   139     register_io_region( &mmio_region_PVR2 );
   140     register_io_region( &mmio_region_PVR2PAL );
   141     register_io_region( &mmio_region_PVR2TA );
   142     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
   143     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   144     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   145     register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
   146     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   147     texcache_init();
   148     pvr2_reset();
   149     pvr2_ta_reset();
   150     save_next_render_filename = NULL;
   151     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
   152         render_buffers[i] = NULL;
   153     }
   154     render_buffer_count = 0;
   155     displayed_render_buffer = NULL;
   156     displayed_border_colour = 0;
   157 }
   159 static void pvr2_reset( void )
   160 {
   161     int i;
   162     pvr2_state.line_count = 0;
   163     pvr2_state.line_remainder = 0;
   164     pvr2_state.cycles_run = 0;
   165     pvr2_state.irq_vpos1 = 0;
   166     pvr2_state.irq_vpos2 = 0;
   167     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   168     pvr2_state.back_porch_ns = 4000;
   169     pvr2_state.palette_changed = FALSE;
   170     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   171     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   172     mmio_region_PVR2_write( YUV_ADDR, 0 );
   173     mmio_region_PVR2_write( YUV_CFG, 0 );
   175     pvr2_ta_init();
   176     texcache_flush();
   177     if( display_driver ) {
   178         display_driver->display_blank(0);
   179         for( i=0; i<render_buffer_count; i++ ) {
   180             display_driver->destroy_render_buffer(render_buffers[i]);
   181             render_buffers[i] = NULL;
   182         }
   183         render_buffer_count = 0;
   184     }
   185 }
   187 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
   188 {
   189     struct frame_buffer fbuf;
   191     fbuf.width = buffer->width;
   192     fbuf.height = buffer->height;
   193     fbuf.rowstride = fbuf.width*3;
   194     fbuf.colour_format = COLFMT_BGR888;
   195     fbuf.inverted = buffer->inverted;
   196     fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
   198     display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
   199     write_png_to_stream( f, &fbuf );
   200     g_free( fbuf.data );
   202     fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   203     fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   204     fwrite( &buffer->address, sizeof(buffer->address), 1, f );
   205     fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
   206     int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
   207     fwrite( &flushed, sizeof(flushed), 1, f );
   209 }
   211 render_buffer_t pvr2_load_render_buffer( FILE *f )
   212 {
   213     frame_buffer_t frame = read_png_from_stream( f );
   214     if( frame == NULL ) {
   215         return NULL;
   216     }
   218     render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
   219     if( buffer != NULL ) {
   220         int32_t flushed;
   221         fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   222         fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   223         fread( &buffer->address, sizeof(buffer->address), 1, f );
   224         fread( &buffer->scale, sizeof(buffer->scale), 1, f );
   225         fread( &flushed, sizeof(flushed), 1, f );
   226         buffer->flushed = (gboolean)flushed;
   227     } else {
   228         fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
   229                 sizeof(buffer->address)+sizeof(buffer->scale)+
   230                 sizeof(int32_t), SEEK_CUR );
   231     }
   232     return buffer;
   233 }
   238 void pvr2_save_render_buffers( FILE *f )
   239 {
   240     int i;
   241     uint32_t has_frontbuffer;
   242     fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
   243     if( displayed_render_buffer != NULL ) {
   244         has_frontbuffer = 1;
   245         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   246         pvr2_save_render_buffer( f, displayed_render_buffer );
   247     } else {
   248         has_frontbuffer = 0;
   249         fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   250     }
   252     for( i=0; i<render_buffer_count; i++ ) {
   253         if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
   254             pvr2_save_render_buffer( f, render_buffers[i] );
   255         }
   256     }
   257 }
   259 gboolean pvr2_load_render_buffers( FILE *f )
   260 {
   261     uint32_t count, has_frontbuffer;
   262     int i;
   264     fread( &count, sizeof(count), 1, f );
   265     if( count > MAX_RENDER_BUFFERS ) {
   266         return FALSE;
   267     }
   268     fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   269     for( i=0; i<render_buffer_count; i++ ) {
   270         display_driver->destroy_render_buffer(render_buffers[i]);
   271         render_buffers[i] = NULL;
   272     }
   273     render_buffer_count = 0;
   275     if( has_frontbuffer ) {
   276         displayed_render_buffer = pvr2_load_render_buffer(f);
   277         display_driver->display_render_buffer( displayed_render_buffer );
   278         count--;
   279     }
   281     for( i=0; i<count; i++ ) {
   282         pvr2_load_render_buffer( f );
   283     }
   284     return TRUE;
   285 }
   288 static void pvr2_save_state( FILE *f )
   289 {
   290     pvr2_save_render_buffers( f );
   291     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   292     pvr2_ta_save_state( f );
   293     pvr2_yuv_save_state( f );
   294 }
   296 static int pvr2_load_state( FILE *f )
   297 {
   298     if( !pvr2_load_render_buffers(f) )
   299         return 1;
   300     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   301         return 1;
   302     if( pvr2_ta_load_state(f) ) {
   303         return 1;
   304     }
   305     return pvr2_yuv_load_state(f);
   306 }
   308 /**
   309  * Update the current raster position to the given number of nanoseconds,
   310  * relative to the last time slice. (ie the raster will be adjusted forward
   311  * by nanosecs - nanosecs_already_run_this_timeslice)
   312  */
   313 static void pvr2_update_raster_posn( uint32_t nanosecs )
   314 {
   315     uint32_t old_line_count = pvr2_state.line_count;
   316     if( pvr2_state.line_time_ns == 0 ) {
   317         return; /* do nothing */
   318     }
   319     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   320     pvr2_state.cycles_run = nanosecs;
   321     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   322         pvr2_state.line_count ++;
   323         pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   324     }
   326     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   327         pvr2_state.line_count -= pvr2_state.total_lines;
   328         if( pvr2_state.interlaced ) {
   329             pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   330         }
   331     }
   332     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   333             (old_line_count < pvr2_state.retrace_end_line ||
   334                     old_line_count > pvr2_state.line_count) ) {
   335         pvr2_state.frame_count++;
   336         pvr2_display_frame();
   337     }
   338 }
   340 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   341 {
   342     pvr2_update_raster_posn( nanosecs );
   343     pvr2_state.cycles_run = 0;
   344     return nanosecs;
   345 }
   347 int pvr2_get_frame_count() 
   348 {
   349     return pvr2_state.frame_count;
   350 }
   352 void pvr2_redraw_display()
   353 {
   354     if( display_driver != NULL ) {
   355         if( displayed_render_buffer == NULL ) {
   356             display_driver->display_blank(displayed_border_colour);
   357         } else {
   358             display_driver->display_render_buffer(displayed_render_buffer);
   359         }
   360     }
   361 }
   363 gboolean pvr2_save_next_scene( const gchar *filename )
   364 {
   365     if( save_next_render_filename != NULL ) {
   366         g_free( save_next_render_filename );
   367     } 
   368     save_next_render_filename = g_strdup(filename);
   369     return TRUE;
   370 }
   374 /**
   375  * Display the next frame, copying the current contents of video ram to
   376  * the window. If the video configuration has changed, first recompute the
   377  * new frame size/depth.
   378  */
   379 void pvr2_display_frame( void )
   380 {
   381     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   382     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   383     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   385     if( display_driver == NULL ) {
   386         return; /* can't really do anything much */
   387     } else if( !bEnabled ) {
   388         /* Output disabled == black */
   389         displayed_render_buffer = NULL;
   390         displayed_border_colour = 0;
   391         display_driver->display_blank( 0 ); 
   392     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
   393         /* Enabled but blanked - border colour */
   394         displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
   395         displayed_render_buffer = NULL;
   396         display_driver->display_blank( displayed_border_colour );
   397     } else {
   398         /* Real output - determine dimensions etc */
   399         struct frame_buffer fbuf;
   400         uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
   401         int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
   402         int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   404         fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
   405         fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
   406         fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   407         fbuf.size = vid_ppl << 2 * fbuf.height;
   408         fbuf.rowstride = (vid_ppl + vid_stride) << 2;
   410         /* Determine the field to display, and deinterlace if possible */
   411         if( pvr2_state.interlaced ) {
   412             if( vid_ppl == vid_stride ) { /* Magic deinterlace */
   413                 fbuf.height = fbuf.height << 1;
   414                 fbuf.rowstride = vid_ppl << 2;
   415                 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   416             } else { 
   417                 /* Just display the field as is, folks. This is slightly tricky -
   418                  * we pick the field based on which frame is about to come through,
   419                  * which may not be the same as the odd_even_field.
   420                  */
   421                 gboolean oddfield = pvr2_state.odd_even_field;
   422                 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
   423                     oddfield = !oddfield;
   424                 }
   425                 if( oddfield ) {
   426                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   427                 } else {
   428                     fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
   429                 }
   430             }
   431         } else {
   432             fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   433         }
   434         fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
   435         fbuf.inverted = FALSE;
   436         fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
   438         render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
   439         if( rbuf == NULL ) {
   440             rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
   441         }
   442         displayed_render_buffer = rbuf;
   443         if( rbuf != NULL ) {
   444             display_driver->display_render_buffer( rbuf );
   445         }
   446     }
   447 }
   449 /**
   450  * This has to handle every single register individually as they all get masked 
   451  * off differently (and its easier to do it at write time)
   452  */
   453 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   454 {
   455     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   456         MMIO_WRITE( PVR2, reg, val );
   457         return;
   458     }
   460     switch(reg) {
   461     case PVRID:
   462     case PVRVER:
   463     case GUNPOS: /* Read only registers */
   464         break;
   465     case PVRRESET:
   466         val &= 0x00000007; /* Do stuff? */
   467         MMIO_WRITE( PVR2, reg, val );
   468         break;
   469     case RENDER_START: /* Don't really care what value */
   470         if( save_next_render_filename != NULL ) {
   471             if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
   472                 INFO( "Saved scene to %s", save_next_render_filename);
   473             }
   474             g_free( save_next_render_filename );
   475             save_next_render_filename = NULL;
   476         }
   477         pvr2_scene_read();
   478         render_buffer_t buffer = pvr2_next_render_buffer();
   479         if( buffer != NULL ) {
   480             pvr2_scene_render( buffer );
   481         }
   482         asic_event( EVENT_PVR_RENDER_DONE );
   483         break;
   484     case RENDER_POLYBASE:
   485         MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   486         break;
   487     case RENDER_TSPCFG:
   488         MMIO_WRITE( PVR2, reg, val&0x00010101 );
   489         break;
   490     case DISP_BORDER:
   491         MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   492         break;
   493     case DISP_MODE:
   494         MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   495         break;
   496     case RENDER_MODE:
   497         MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   498         break;
   499     case RENDER_SIZE:
   500         MMIO_WRITE( PVR2, reg, val&0x000001FF );
   501         break;
   502     case DISP_ADDR1:
   503         val &= 0x00FFFFFC;
   504         MMIO_WRITE( PVR2, reg, val );
   505         pvr2_update_raster_posn(sh4r.slice_cycle);
   506         break;
   507     case DISP_ADDR2:
   508         MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   509         pvr2_update_raster_posn(sh4r.slice_cycle);
   510         break;
   511     case DISP_SIZE:
   512         MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   513         break;
   514     case RENDER_ADDR1:
   515     case RENDER_ADDR2:
   516         MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   517         break;
   518     case RENDER_HCLIP:
   519         MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   520         break;
   521     case RENDER_VCLIP:
   522         MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   523         break;
   524     case DISP_HPOSIRQ:
   525         MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   526         pvr2_state.irq_hpos_line = val & 0x03FF;
   527         pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
   528         pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
   529         switch( pvr2_state.irq_hpos_mode ) {
   530         case 3: /* Reserved - treat as 0 */
   531         case 0: /* Once per frame at specified line */
   532             pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
   533             break;
   534         case 2: /* Once per line - as per-line-count */
   535             pvr2_state.irq_hpos_line = 1;
   536             pvr2_state.irq_hpos_mode = 1;
   537         case 1: /* Once per N lines */
   538             pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
   539             pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
   540             pvr2_state.irq_hpos_line_count;
   541             while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   542                 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   543             }
   544             pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
   545         }
   546         pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
   547                                       pvr2_state.irq_hpos_time_ns );
   548         break;
   549         case DISP_VPOSIRQ:
   550             val = val & 0x03FF03FF;
   551             pvr2_state.irq_vpos1 = (val >> 16);
   552             pvr2_state.irq_vpos2 = val & 0x03FF;
   553             pvr2_update_raster_posn(sh4r.slice_cycle);
   554             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   555             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   556             MMIO_WRITE( PVR2, reg, val );
   557             break;
   558         case RENDER_NEARCLIP:
   559             MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   560             break;
   561         case RENDER_SHADOW:
   562             MMIO_WRITE( PVR2, reg, val&0x000001FF );
   563             break;
   564         case RENDER_OBJCFG:
   565             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   566             break;
   567         case RENDER_TSPCLIP:
   568             MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   569             break;
   570         case RENDER_FARCLIP:
   571             MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   572             break;
   573         case RENDER_BGPLANE:
   574             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   575             break;
   576         case RENDER_ISPCFG:
   577             MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   578             break;
   579         case VRAM_CFG1:
   580             MMIO_WRITE( PVR2, reg, val&0x000000FF );
   581             break;
   582         case VRAM_CFG2:
   583             MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   584             break;
   585         case VRAM_CFG3:
   586             MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   587             break;
   588         case RENDER_FOGTBLCOL:
   589         case RENDER_FOGVRTCOL:
   590             MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   591             break;
   592         case RENDER_FOGCOEFF:
   593             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   594             break;
   595         case RENDER_CLAMPHI:
   596         case RENDER_CLAMPLO:
   597             MMIO_WRITE( PVR2, reg, val );
   598             break;
   599         case RENDER_TEXSIZE:
   600             MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   601             break;
   602         case RENDER_PALETTE:
   603             MMIO_WRITE( PVR2, reg, val&0x00000003 );
   604             break;
   605         case RENDER_ALPHA_REF:
   606             MMIO_WRITE( PVR2, reg, val&0x000000FF );
   607             break;
   608             /********** CRTC registers *************/
   609         case DISP_HBORDER:
   610         case DISP_VBORDER:
   611             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   612             break;
   613         case DISP_TOTAL:
   614             val = val & 0x03FF03FF;
   615             MMIO_WRITE( PVR2, reg, val );
   616             pvr2_update_raster_posn(sh4r.slice_cycle);
   617             pvr2_state.total_lines = (val >> 16) + 1;
   618             pvr2_state.line_size = (val & 0x03FF) + 1;
   619             pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   620             pvr2_state.retrace_end_line = 0x2A;
   621             pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   622             pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   623             pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   624             pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
   625                                           pvr2_state.irq_hpos_time_ns );
   626             break;
   627         case DISP_SYNCCFG:
   628             MMIO_WRITE( PVR2, reg, val&0x000003FF );
   629             pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   630             break;
   631         case DISP_SYNCTIME:
   632             pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   633             pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   634             MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   635             break;
   636         case DISP_CFG2:
   637             MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   638             break;
   639         case DISP_HPOS:
   640             val = val & 0x03FF;
   641             pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   642             MMIO_WRITE( PVR2, reg, val );
   643             break;
   644         case DISP_VPOS:
   645             MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   646             break;
   648             /*********** Tile accelerator registers ***********/
   649         case TA_POLYPOS:
   650         case TA_LISTPOS:
   651             /* Readonly registers */
   652             break;
   653         case TA_TILEBASE:
   654         case TA_LISTEND:
   655         case TA_LISTBASE:
   656             MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   657             break;
   658         case RENDER_TILEBASE:
   659         case TA_POLYBASE:
   660         case TA_POLYEND:
   661             MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   662             break;
   663         case TA_TILESIZE:
   664             MMIO_WRITE( PVR2, reg, val&0x000F003F );
   665             break;
   666         case TA_TILECFG:
   667             MMIO_WRITE( PVR2, reg, val&0x00133333 );
   668             break;
   669         case TA_INIT:
   670             if( val & 0x80000000 )
   671                 pvr2_ta_init();
   672             break;
   673         case TA_REINIT:
   674             break;
   675             /**************** Scaler registers? ****************/
   676         case RENDER_SCALER:
   677             MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   678             break;
   680         case YUV_ADDR:
   681             val = val & 0x00FFFFF8;
   682             MMIO_WRITE( PVR2, reg, val );
   683             pvr2_yuv_init( val );
   684             break;
   685         case YUV_CFG:
   686             MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   687             pvr2_yuv_set_config(val);
   688             break;
   690             /**************** Unknowns ***************/
   691         case PVRUNK1:
   692             MMIO_WRITE( PVR2, reg, val&0x000007FF );
   693             break;
   694         case PVRUNK2:
   695             MMIO_WRITE( PVR2, reg, val&0x00000007 );
   696             break;
   697         case PVRUNK3:
   698             MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   699             break;
   700         case PVRUNK5:
   701             MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   702             break;
   703         case PVRUNK7:
   704             MMIO_WRITE( PVR2, reg, val&0x00000001 );
   705             break;
   706         case PVRUNK8:
   707             MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
   708             break;
   709     }
   710 }
   712 /**
   713  * Calculate the current read value of the syncstat register, using
   714  * the current SH4 clock time as an offset from the last timeslice.
   715  * The register reads (LSB to MSB) as:
   716  *     0..9  Current scan line
   717  *     10    Odd/even field (1 = odd, 0 = even)
   718  *     11    Display active (including border and overscan)
   719  *     12    Horizontal sync off
   720  *     13    Vertical sync off
   721  * Note this method is probably incorrect for anything other than straight
   722  * interlaced PAL/NTSC, and needs further testing. 
   723  */
   724 uint32_t pvr2_get_sync_status()
   725 {
   726     pvr2_update_raster_posn(sh4r.slice_cycle);
   727     uint32_t result = pvr2_state.line_count;
   729     if( pvr2_state.odd_even_field ) {
   730         result |= 0x0400;
   731     }
   732     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   733         if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   734             result |= 0x1000; /* !HSYNC */
   735         }
   736         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   737             if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   738                 result |= 0x2800; /* Display active */
   739             } else {
   740                 result |= 0x2000; /* Front porch */
   741             }
   742         }
   743     } else {
   744         if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   745             if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   746                 result |= 0x3800; /* Display active */
   747             } else {
   748                 result |= 0x3000;
   749             }
   750         } else {
   751             result |= 0x1000; /* Back porch */
   752         }
   753     }
   754     return result;
   755 }
   757 /**
   758  * Schedule a "scanline" event. This actually goes off at
   759  * 2 * line in even fields and 2 * line + 1 in odd fields.
   760  * Otherwise this behaves as per pvr2_schedule_line_event().
   761  * The raster position should be updated before calling this
   762  * method.
   763  * @param eventid Event to fire at the specified time
   764  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
   765  *  displays). 
   766  * @param hpos_ns Nanoseconds into the line at which to fire.
   767  */
   768 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
   769 {
   770     uint32_t field = pvr2_state.odd_even_field;
   771     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   772         field = !field;
   773     }
   774     if( hpos_ns > pvr2_state.line_time_ns ) {
   775         hpos_ns = pvr2_state.line_time_ns;
   776     }
   778     line <<= 1;
   779     if( field ) {
   780         line += 1;
   781     }
   783     if( line < pvr2_state.total_lines ) {
   784         uint32_t lines;
   785         uint32_t time;
   786         if( line <= pvr2_state.line_count ) {
   787             lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   788         } else {
   789             lines = (line - pvr2_state.line_count);
   790         }
   791         if( lines <= minimum_lines ) {
   792             lines += pvr2_state.total_lines;
   793         }
   794         time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
   795         event_schedule( eventid, time );
   796     } else {
   797         event_cancel( eventid );
   798     }
   799 }
   801 void pvr2_queue_gun_event( int xpos, int ypos )
   802 {
   803     pvr2_update_raster_posn(sh4r.slice_cycle);
   804     pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,  
   805             (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns ); 
   806 }
   808 MMIO_REGION_READ_FN( PVR2, reg )
   809 {
   810     switch( reg ) {
   811     case DISP_SYNCSTAT:
   812         return pvr2_get_sync_status();
   813     default:
   814         return MMIO_READ( PVR2, reg );
   815     }
   816 }
   818 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
   819 {
   820     MMIO_WRITE( PVR2PAL, reg, val );
   821     pvr2_state.palette_changed = TRUE;
   822 }
   824 void pvr2_check_palette_changed()
   825 {
   826     if( pvr2_state.palette_changed ) {
   827         texcache_invalidate_palette();
   828         pvr2_state.palette_changed = FALSE;
   829     }
   830 }
   832 MMIO_REGION_READ_DEFFN( PVR2PAL );
   834 void pvr2_set_base_address( uint32_t base ) 
   835 {
   836     mmio_region_PVR2_write( DISP_ADDR1, base );
   837 }
   842 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   843 {
   844     return 0xFFFFFFFF;
   845 }
   847 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   848 {
   849     pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
   850 }
   852 /**
   853  * Find the render buffer corresponding to the requested output frame
   854  * (does not consider texture renders). 
   855  * @return the render_buffer if found, or null if no such buffer.
   856  *
   857  * Note: Currently does not consider "partial matches", ie partial
   858  * frame overlap - it probably needs to do this.
   859  */
   860 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
   861 {
   862     int i;
   863     for( i=0; i<render_buffer_count; i++ ) {
   864         if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
   865             return render_buffers[i];
   866         }
   867     }
   868     return NULL;
   869 }
   871 /**
   872  * Allocate a render buffer with the requested parameters.
   873  * The order of preference is:
   874  *   1. An existing buffer with the same address. (not flushed unless the new
   875  * size is smaller than the old one).
   876  *   2. An existing buffer with the same size chosen by LRU order. Old buffer
   877  *       is flushed to vram.
   878  *   3. A new buffer if one can be created.
   879  *   4. The current display buff
   880  * Note: The current display field(s) will never be overwritten except as a last
   881  * resort.
   882  */
   883 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
   884 {
   885     int i;
   886     render_buffer_t result = NULL;
   888     /* Check existing buffers for an available buffer */
   889     for( i=0; i<render_buffer_count; i++ ) {
   890         if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
   891             /* needs to be the right dimensions */
   892             if( render_buffers[i]->address == render_addr ) {
   893                 if( displayed_render_buffer == render_buffers[i] ) {
   894                     /* Same address, but we can't use it because the
   895                      * display has it. Mark it as unaddressed for later.
   896                      */
   897                     render_buffers[i]->address = -1;
   898                 } else {
   899                     /* perfect */
   900                     result = render_buffers[i];
   901                     break;
   902                 }
   903             } else if( render_buffers[i]->address == -1 && result == NULL && 
   904                     displayed_render_buffer != render_buffers[i] ) {
   905                 result = render_buffers[i];
   906             }
   908         } else if( render_buffers[i]->address == render_addr ) {
   909             /* right address, wrong size - if it's larger, flush it, otherwise 
   910              * nuke it quietly */
   911             if( render_buffers[i]->width * render_buffers[i]->height >
   912             width*height ) {
   913                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   914             }
   915             render_buffers[i]->address = -1;
   916         }
   917     }
   919     /* Nothing available - make one */
   920     if( result == NULL ) {
   921         if( render_buffer_count == MAX_RENDER_BUFFERS ) {
   922             /* maximum buffers reached - need to throw one away */
   923             uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   924             uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
   925             for( i=0; i<render_buffer_count; i++ ) {
   926                 if( render_buffers[i]->address != field1_addr &&
   927                         render_buffers[i]->address != field2_addr &&
   928                         render_buffers[i] != displayed_render_buffer ) {
   929                     /* Never throw away the current "front buffer(s)" */
   930                     result = render_buffers[i];
   931                     if( !result->flushed ) {
   932                         pvr2_render_buffer_copy_to_sh4( result );
   933                     }
   934                     if( result->width != width || result->height != height ) {
   935                         display_driver->destroy_render_buffer(render_buffers[i]);
   936                         result = display_driver->create_render_buffer(width,height,0);
   937                         render_buffers[i] = result;
   938                     }
   939                     break;
   940                 }
   941             }
   942         } else {
   943             result = display_driver->create_render_buffer(width,height,0);
   944             if( result != NULL ) { 
   945                 render_buffers[render_buffer_count++] = result;
   946             }
   947         }
   948     }
   950     if( result != NULL ) {
   951         result->address = render_addr;
   952     }
   953     return result;
   954 }
   956 /**
   957  * Allocate a render buffer based on the current rendering settings
   958  */
   959 render_buffer_t pvr2_next_render_buffer()
   960 {
   961     render_buffer_t result = NULL;
   962     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
   963     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
   964     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
   965     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
   967     if( render_addr & 0x01000000 ) { /* vram64 */
   968         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
   969     } else { /* vram32 */
   970         render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
   971     }
   973     int width = pvr2_scene_buffer_width();
   974     int height = pvr2_scene_buffer_height();
   975     int colour_format = pvr2_render_colour_format[render_mode&0x07];
   977     result = pvr2_alloc_render_buffer( render_addr, width, height );
   978     /* Setup the buffer */
   979     if( result != NULL ) {
   980         result->rowstride = render_stride;
   981         result->colour_format = colour_format;
   982         result->scale = render_scale;
   983         result->size = width * height * colour_formats[colour_format].bpp;
   984         result->flushed = FALSE;
   985         result->inverted = TRUE; // render buffers are inverted normally
   986     }
   987     return result;
   988 }
   990 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
   991 {
   992     render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
   993     if( result != NULL ) {
   994         int bpp = colour_formats[frame->colour_format].bpp;
   995         result->rowstride = frame->rowstride;
   996         result->colour_format = frame->colour_format;
   997         result->scale = 0x400;
   998         result->size = frame->width * frame->height * bpp;
   999         result->flushed = TRUE;
  1000         result->inverted = frame->inverted;
  1001         display_driver->load_frame_buffer( frame, result );
  1003     return result;
  1007 /**
  1008  * Invalidate any caching on the supplied address. Specifically, if it falls
  1009  * within any of the render buffers, flush the buffer back to PVR2 ram.
  1010  */
  1011 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
  1013     int i;
  1014     address = address & 0x1FFFFFFF;
  1015     for( i=0; i<render_buffer_count; i++ ) {
  1016         uint32_t bufaddr = render_buffers[i]->address;
  1017         if( bufaddr != -1 && bufaddr <= address && 
  1018                 (bufaddr + render_buffers[i]->size) > address ) {
  1019             if( !render_buffers[i]->flushed ) {
  1020                 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
  1021                 render_buffers[i]->flushed = TRUE;
  1023             if( isWrite ) {
  1024                 render_buffers[i]->address = -1; /* Invalid */
  1026             return TRUE; /* should never have overlapping buffers */
  1029     return FALSE;
.