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lxdream.org :: lxdream/src/gdrom/ide.h
lxdream 0.9.1
released Jun 29
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filename src/gdrom/ide.h
changeset 2:42349f6ea216
next31:495e480360d7
author nkeynes
date Sat Aug 21 06:15:49 2004 +0000 (17 years ago)
permissions -rw-r--r--
last change Commit changes into cvs
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     1 /*
     2  * ide.h    31 Mar 2004  - IDE Interface definitions
     3  *
     4  * Copyright (c) 2004 Nathan Keynes. Distribution and modification permitted
     5  * under the terms of the GNU General Public License version 2 or later. 
     6  *
     7  * This file defines the interface and structures of the dreamcast's IDE port. 
     8  * Note that the register definitions are in asic.h, as the registers fall into
     9  * the general ASIC ranges (and I don't want to use smaller pages at this
    10  * stage). The registers here are exactly as per the ATA specifications, which
    11  * makes things a little easier.
    12  */
    13 #ifndef dream_ide_H
    14 #define dream_ide_H 1
    16 #include "dream.h"
    18 struct ide_registers {
    19     uint8_t status;  /* A05F709C + A05F7018 Read-only */
    20     uint8_t control; /* A05F7018 Write-only 01110 */
    21     uint8_t error;   /* A05F7084 Read-only  10001 */
    22     uint8_t feature; /* A05F7084 Write-only 10001 */
    23     uint8_t count;   /* A05F7088 Read/Write 10010 */
    24     uint8_t disc;    /* A05F708C Read-only 10011 */
    25     uint8_t lba0;    /* A05F708C Write-only 10011 (NB: Presumed, TBV */
    26     uint8_t lba1;    /* A05F7090 Read/Write 10100 */
    27     uint8_t lba2;    /* A05F7094 Read/Write 10101 */
    28     uint8_t device;  /* A05F7098 Read/Write 10110 */
    29     uint8_t command; /* A05F709C Write-only 10111 */
    31     /* We don't keep the data register per se, rather the currently pending
    32      * data is kept here and read out a byte at a time (in PIO mode) or all at
    33      * once (in DMA mode). The IDE routines are responsible for managing this
    34      * memory. If dataptr == NULL, there is no data available.
    35      */
    36     char *data;
    37     uint16_t *readptr, *writeptr;
    38     int datalen;
    39 };
    41 #define IDE_ST_BUSY  0x80
    42 #define IDE_ST_READY 0x40
    43 #define IDE_ST_SERV  0x10
    44 #define IDE_ST_DATA  0x08
    45 #define IDE_ST_ERROR 0x01
    47 #define IDE_CTL_RESET 0x04
    48 #define IDE_CTL_IRQEN 0x02 /* IRQ enabled when == 0 */
    50 #define IDE_CMD_RESET_DEVICE 0x08
    51 #define IDE_CMD_PACKET 0xA0
    52 #define IDE_CMD_IDENTIFY_PACKET_DEVICE 0xA1
    53 #define IDE_CMD_SERVICE 0xA2
    54 #define IDE_CMD_SET_FEATURE 0xEF
    56 /* The disc register indicates the current contents of the drive. When open
    57  * contains 0x06.
    58  */
    59 #define IDE_DISC_AUDIO 0x00
    60 #define IDE_DISC_NONE  0x06
    61 #define IDE_DISC_CDROM 0x20
    62 #define IDE_DISC_GDROM 0x80
    63 #define IDE_DISC_READY 0x01 /* ored with above */
    64 #define IDE_DISC_IDLE  0x02 /* ie spun-down */
    66 #define PKT_CMD_RESET    0x00 /* Wild-ass guess */
    67 #define PKT_CMD_IDENTIFY 0x11
    69 extern struct ide_registers idereg;
    71 /* Note: control can be written at any time - all other registers are writable
    72  * only when ide_can_write_regs() is true
    73  */
    74 #define ide_can_write_regs() ((idereg.status&0x88)==0)
    76 /* Called upon:
    77  *   a) Writing the command register
    78  *   b) Reading the status (but not altstatus) register
    79  *  (whether this actually has any effect an the ASIC event is TBD)
    80  */
    81 void ide_clear_interrupt(void);
    83 void ide_reset(void);
    85 uint16_t ide_read_data_pio(void);
    86 void ide_write_data_pio( uint16_t value );
    87 void ide_write_buffer( char * ); 
    89 void ide_write_command( uint8_t command );
    90 void ide_write_control( uint8_t value );
    91 #endif
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