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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 2:42349f6ea216
prev1:eea311cfd33e
next15:5194dd0fdb60
author nkeynes
date Sat Aug 21 06:15:49 2004 +0000 (15 years ago)
permissions -rw-r--r--
last change Commit changes into cvs
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     1 #include "dream.h"
     2 #include "video.h"
     3 #include "mem.h"
     4 #include "asic.h"
     5 #include "pvr2.h"
     6 #define MMIO_IMPL
     7 #include "pvr2.h"
     9 char *video_base;
    11 void pvr2_init( void )
    12 {
    13     register_io_region( &mmio_region_PVR2 );
    14     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    15 }
    17 uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
    18 int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
    19 char *frame_start; /* current video start address (in real memory) */
    21 /*
    22  * Display the next frame, copying the current contents of video ram to
    23  * the window. If the video configuration has changed, first recompute the
    24  * new frame size/depth.
    25  */
    26 void pvr2_next_frame( void )
    27 {
    28     if( bChanged ) {
    29         int dispsize = MMIO_READ( PVR2, DISPSIZE );
    30         int dispmode = MMIO_READ( PVR2, DISPMODE );
    31         int vidcfg = MMIO_READ( PVR2, VIDCFG );
    32         vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
    33         vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
    34         vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
    35         vid_col = (dispmode & DISPMODE_COL);
    36         frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
    37         interlaced = (vidcfg & VIDCFG_I ? 1 : 0);
    38         bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & VIDCFG_VO ) ? 1 : 0;
    39         vid_size = (vid_ppl * vid_lpf) << (interlaced ? 3 : 2);
    40         vid_hres = vid_ppl;
    41         vid_vres = vid_lpf;
    42         if( interlaced ) vid_vres <<= 1;
    43         switch( vid_col ) {
    44             case MODE_RGB15:
    45             case MODE_RGB16: vid_hres <<= 1; break;
    46             case MODE_RGB24: vid_hres *= 3; break;
    47             case MODE_RGB32: vid_hres <<= 2; break;
    48         }
    49         vid_hres >>= 2;
    50         video_update_size( vid_hres, vid_vres, vid_col );
    51         bChanged = 0;
    52     }
    53     if( bEnabled ) {
    54         /* Assume bit depths match for now... */
    55         memcpy( video_data, frame_start, vid_size );
    56     } else {
    57         memset( video_data, 0, vid_size );
    58     }
    59     video_update_frame();
    60     asic_event( EVENT_SCANLINE1 );
    61     asic_event( EVENT_SCANLINE2 );
    62     asic_event( EVENT_RETRACE );
    63 }
    65 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
    66 {
    67     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
    68         MMIO_WRITE( PVR2, reg, val );
    69         /* I don't want to hear about these */
    70         return;
    71     }
    73     INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
    74           MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
    76     switch(reg) {
    77         case DISPSIZE: bChanged = 1;
    78         case DISPMODE: bChanged = 1;
    79         case DISPADDR1: bChanged = 1;
    80         case DISPADDR2: bChanged = 1;
    81         case VIDCFG: bChanged = 1;
    82             break;
    84     }
    85     MMIO_WRITE( PVR2, reg, val );
    86 }
    88 MMIO_REGION_READ_FN( PVR2, reg )
    89 {
    90     switch( reg ) {
    91         case BEAMPOS:
    92             return sh4r.icount&0x20 ? 0x2000 : 1;
    93         default:
    94             return MMIO_READ( PVR2, reg );
    95     }
    96 }
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