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lxdream.org :: lxdream/src/sh4/sh4core.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 2:42349f6ea216
prev1:eea311cfd33e
next10:c898b37506e0
author nkeynes
date Sat Aug 21 06:15:49 2004 +0000 (16 years ago)
permissions -rw-r--r--
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     1 /*
     2  * Header for the basic sh4 emulator core
     3  */
     4 #ifndef sh4core_H
     5 #define sh4core_H 1
     7 #include <stdint.h>
     9 #ifdef __cplusplus
    10 extern "C" {
    11 #if 0
    12 }
    13 #endif
    14 #endif
    16 struct sh4_registers {
    17     uint32_t r[16];
    18     uint32_t r_bank[8]; /* hidden banked registers */
    19     uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
    20     uint32_t pr, pc, fpul, fpscr;
    21     uint64_t mac;
    22     uint32_t m, q, s, t; /* really boolean - 0 or 1 */
    23     float fr[2][16];
    25     int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
    27     uint32_t new_pc; /* Not a real register, but used to handle delay slots */
    28     uint32_t icount; /* Also not a real register, instruction counter */
    29     uint32_t int_pending; /* flag set by the INTC = pending priority level */
    30     int in_delay_slot; /* flag to indicate the current instruction is in
    31                              * a delay slot (certain rules apply) */
    32 };
    34 extern struct sh4_registers sh4r;
    36 /* Public functions */
    38 void sh4_init( void );
    39 void sh4_reset( void );
    40 void sh4_run( void );
    41 void sh4_runto( uint32_t pc, uint32_t count );
    42 void sh4_runfor( uint32_t count );
    43 int sh4_isrunning( void );
    44 void sh4_stop( void );
    45 void sh4_set_pc( int );
    46 void sh4_execute_instruction( void );
    47 void sh4_raise_exception( int, int );
    49 void run_timers( int );
    51 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
    52 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
    53 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
    54 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
    55 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
    56 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
    58 /* Status Register (SR) bits */
    59 #define SR_MD    0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ 
    60 #define SR_RB    0x20000000 /* Register bank (priviledged mode only) */
    61 #define SR_BL    0x10000000 /* Exception/interupt block (1 = masked) */
    62 #define SR_FD    0x00008000 /* FPU disable */
    63 #define SR_M     0x00000200
    64 #define SR_Q     0x00000100
    65 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
    66 #define SR_S     0x00000002 /* Saturation operation for MAC instructions */
    67 #define SR_T     0x00000001 /* True/false or carry/borrow */
    68 #define SR_MASK  0x700083F3
    69 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
    71 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
    72 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
    73 #define SH4_INT_PENDING() (sh4r.int_pending && !sh4r.in_delay_slot)
    75 #define FPSCR_FR     0x00200000 /* FPU register bank */
    76 #define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
    77 #define FPSCR_PR     0x00080000 /* Precision (0=32 bites, 1=64 bits) */
    78 #define FPSCR_DN     0x00040000 /* Denormalization mode (1 = treat as 0) */
    79 #define FPSCR_CAUSE  0x0003F000
    80 #define FPSCR_ENABLE 0x00000F80
    81 #define FPSCR_FLAG   0x0000007C
    82 #define FPSCR_RM     0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
    84 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
    85 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
    86 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
    88 #define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
    89 #define XF sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]
    91 /* Exceptions (for use with sh4_raise_exception) */
    93 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
    94 #define EX_SLOT_ILLEGAL        0x1A0, 0x100
    95 #define EX_TLB_MISS_READ       0x040, 0x400
    96 #define EX_TLB_MISS_WRITE      0x060, 0x400
    97 #define EX_INIT_PAGE_WRITE     0x080, 0x100
    98 #define EX_TLB_PROT_READ       0x0A0, 0x100
    99 #define EX_TLB_PROT_WRITE      0x0C0, 0x100
   100 #define EX_DATA_ADDR_READ      0x0E0, 0x100
   101 #define EX_DATA_ADDR_WRITE     0x100, 0x100
   102 #define EX_FPU_EXCEPTION       0x120, 0x100
   103 #define EX_TRAPA               0x160, 0x100
   104 #define EX_BREAKPOINT          0x1E0, 0x100
   105 #define EX_FPU_DISABLED        0x800, 0x100
   106 #define EX_SLOT_FPU_DISABLED   0x820, 0x100
   108 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
   110 #ifdef __cplusplus
   111 }
   112 #endif
   113 #endif
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