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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 430:467519b050f4
prev401:f79327f39818
next490:1e0f9940e064
author nkeynes
date Mon Oct 08 12:09:06 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix compilation warnings
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     1 /**
     2  * $Id: sh4core.c,v 1.49 2007-10-08 12:06:01 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "eventq.h"
    25 #include "mem.h"
    26 #include "clock.h"
    27 #include "syscall.h"
    28 #include "sh4/sh4core.h"
    29 #include "sh4/sh4mmio.h"
    30 #include "sh4/intc.h"
    32 #define SH4_CALLTRACE 1
    34 #define MAX_INT 0x7FFFFFFF
    35 #define MIN_INT 0x80000000
    36 #define MAX_INTF 2147483647.0
    37 #define MIN_INTF -2147483648.0
    39 /********************** SH4 Module Definition ****************************/
    41 uint16_t *sh4_icache = NULL;
    42 uint32_t sh4_icache_addr = 0;
    44 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    45 {
    46     int i;
    47     sh4r.slice_cycle = 0;
    49     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    50 	if( sh4r.event_pending < nanosecs ) {
    51 	    sh4r.sh4_state = SH4_STATE_RUNNING;
    52 	    sh4r.slice_cycle = sh4r.event_pending;
    53 	}
    54     }
    56     if( sh4_breakpoint_count == 0 ) {
    57 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    58 	    if( SH4_EVENT_PENDING() ) {
    59 		if( sh4r.event_types & PENDING_EVENT ) {
    60 		    event_execute();
    61 		}
    62 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    63 		if( sh4r.event_types & PENDING_IRQ ) {
    64 		    sh4_accept_interrupt();
    65 		}
    66 	    }
    67 	    if( !sh4_execute_instruction() ) {
    68 		break;
    69 	    }
    70 	}
    71     } else {
    72 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    73 	    if( SH4_EVENT_PENDING() ) {
    74 		if( sh4r.event_types & PENDING_EVENT ) {
    75 		    event_execute();
    76 		}
    77 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    78 		if( sh4r.event_types & PENDING_IRQ ) {
    79 		    sh4_accept_interrupt();
    80 		}
    81 	    }
    83 	    if( !sh4_execute_instruction() )
    84 		break;
    85 #ifdef ENABLE_DEBUG_MODE
    86 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    87 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    88 		    break;
    89 		}
    90 	    }
    91 	    if( i != sh4_breakpoint_count ) {
    92 		dreamcast_stop();
    93 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    94 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    95 		break;
    96 	    }
    97 #endif	
    98 	}
    99     }
   101     /* If we aborted early, but the cpu is still technically running,
   102      * we're doing a hard abort - cut the timeslice back to what we
   103      * actually executed
   104      */
   105     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   106 	nanosecs = sh4r.slice_cycle;
   107     }
   108     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   109 	TMU_run_slice( nanosecs );
   110 	SCIF_run_slice( nanosecs );
   111     }
   112     return nanosecs;
   113 }
   115 /********************** SH4 emulation core  ****************************/
   117 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   118 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   120 #if(SH4_CALLTRACE == 1)
   121 #define MAX_CALLSTACK 32
   122 static struct call_stack {
   123     sh4addr_t call_addr;
   124     sh4addr_t target_addr;
   125     sh4addr_t stack_pointer;
   126 } call_stack[MAX_CALLSTACK];
   128 static int call_stack_depth = 0;
   129 int sh4_call_trace_on = 0;
   131 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   132 {
   133     if( call_stack_depth < MAX_CALLSTACK ) {
   134 	call_stack[call_stack_depth].call_addr = source;
   135 	call_stack[call_stack_depth].target_addr = dest;
   136 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   137     }
   138     call_stack_depth++;
   139 }
   141 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   142 {
   143     if( call_stack_depth > 0 ) {
   144 	call_stack_depth--;
   145     }
   146 }
   148 void fprint_stack_trace( FILE *f )
   149 {
   150     int i = call_stack_depth -1;
   151     if( i >= MAX_CALLSTACK )
   152 	i = MAX_CALLSTACK - 1;
   153     for( ; i >= 0; i-- ) {
   154 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   155 		 (call_stack_depth - i), call_stack[i].call_addr,
   156 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   157     }
   158 }
   160 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   161 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   162 #else
   163 #define TRACE_CALL( dest, rts ) 
   164 #define TRACE_RETURN( source, dest )
   165 #endif
   167 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   168 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   169 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   170 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   171 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   172 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   174 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   176 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   177 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   179 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   180 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   181 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   182 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   183 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   185 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   186 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   187 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   189 static void sh4_write_float( uint32_t addr, int reg )
   190 {
   191     if( IS_FPU_DOUBLESIZE() ) {
   192 	if( reg & 1 ) {
   193 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   194 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   195 	} else {
   196 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   197 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   198 	}
   199     } else {
   200 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   201     }
   202 }
   204 static void sh4_read_float( uint32_t addr, int reg )
   205 {
   206     if( IS_FPU_DOUBLESIZE() ) {
   207 	if( reg & 1 ) {
   208 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   209 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   210 	} else {
   211 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   212 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   213 	}
   214     } else {
   215 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   216     }
   217 }
   219 gboolean sh4_execute_instruction( void )
   220 {
   221     uint32_t pc;
   222     unsigned short ir;
   223     uint32_t tmp;
   224     float ftmp;
   225     double dtmp;
   227 #define R0 sh4r.r[0]
   228     pc = sh4r.pc;
   229     if( pc > 0xFFFFFF00 ) {
   230 	/* SYSCALL Magic */
   231 	syscall_invoke( pc );
   232 	sh4r.in_delay_slot = 0;
   233 	pc = sh4r.pc = sh4r.pr;
   234 	sh4r.new_pc = sh4r.pc + 2;
   235     }
   236     CHECKRALIGN16(pc);
   238     /* Read instruction */
   239     uint32_t pageaddr = pc >> 12;
   240     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   241 	ir = sh4_icache[(pc&0xFFF)>>1];
   242     } else {
   243 	sh4_icache = (uint16_t *)mem_get_page(pc);
   244 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   245 	    /* If someone's actually been so daft as to try to execute out of an IO
   246 	     * region, fallback on the full-blown memory read
   247 	     */
   248 	    sh4_icache = NULL;
   249 	    ir = MEM_READ_WORD(pc);
   250 	} else {
   251 	    sh4_icache_addr = pageaddr;
   252 	    ir = sh4_icache[(pc&0xFFF)>>1];
   253 	}
   254     }
   255         switch( (ir&0xF000) >> 12 ) {
   256             case 0x0:
   257                 switch( ir&0xF ) {
   258                     case 0x2:
   259                         switch( (ir&0x80) >> 7 ) {
   260                             case 0x0:
   261                                 switch( (ir&0x70) >> 4 ) {
   262                                     case 0x0:
   263                                         { /* STC SR, Rn */
   264                                         uint32_t Rn = ((ir>>8)&0xF); 
   265                                         CHECKPRIV();
   266                                         sh4r.r[Rn] = sh4_read_sr();
   267                                         }
   268                                         break;
   269                                     case 0x1:
   270                                         { /* STC GBR, Rn */
   271                                         uint32_t Rn = ((ir>>8)&0xF); 
   272                                         CHECKPRIV();
   273                                         sh4r.r[Rn] = sh4r.gbr;
   274                                         }
   275                                         break;
   276                                     case 0x2:
   277                                         { /* STC VBR, Rn */
   278                                         uint32_t Rn = ((ir>>8)&0xF); 
   279                                         CHECKPRIV();
   280                                         sh4r.r[Rn] = sh4r.vbr;
   281                                         }
   282                                         break;
   283                                     case 0x3:
   284                                         { /* STC SSR, Rn */
   285                                         uint32_t Rn = ((ir>>8)&0xF); 
   286                                         CHECKPRIV();
   287                                         sh4r.r[Rn] = sh4r.ssr;
   288                                         }
   289                                         break;
   290                                     case 0x4:
   291                                         { /* STC SPC, Rn */
   292                                         uint32_t Rn = ((ir>>8)&0xF); 
   293                                         CHECKPRIV();
   294                                         sh4r.r[Rn] = sh4r.spc;
   295                                         }
   296                                         break;
   297                                     default:
   298                                         UNDEF();
   299                                         break;
   300                                 }
   301                                 break;
   302                             case 0x1:
   303                                 { /* STC Rm_BANK, Rn */
   304                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   305                                 CHECKPRIV();
   306                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   307                                 }
   308                                 break;
   309                         }
   310                         break;
   311                     case 0x3:
   312                         switch( (ir&0xF0) >> 4 ) {
   313                             case 0x0:
   314                                 { /* BSRF Rn */
   315                                 uint32_t Rn = ((ir>>8)&0xF); 
   316                                 CHECKSLOTILLEGAL();
   317                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   318                                 sh4r.in_delay_slot = 1;
   319                                 sh4r.pr = sh4r.pc + 4;
   320                                 sh4r.pc = sh4r.new_pc;
   321                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   322                                 TRACE_CALL( pc, sh4r.new_pc );
   323                                 return TRUE;
   324                                 }
   325                                 break;
   326                             case 0x2:
   327                                 { /* BRAF Rn */
   328                                 uint32_t Rn = ((ir>>8)&0xF); 
   329                                 CHECKSLOTILLEGAL();
   330                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   331                                 sh4r.in_delay_slot = 1;
   332                                 sh4r.pc = sh4r.new_pc;
   333                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   334                                 return TRUE;
   335                                 }
   336                                 break;
   337                             case 0x8:
   338                                 { /* PREF @Rn */
   339                                 uint32_t Rn = ((ir>>8)&0xF); 
   340                                 tmp = sh4r.r[Rn];
   341                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {
   342                            	 sh4_flush_store_queue(tmp);
   343                                 }
   344                                 }
   345                                 break;
   346                             case 0x9:
   347                                 { /* OCBI @Rn */
   348                                 uint32_t Rn = ((ir>>8)&0xF); 
   349                                 }
   350                                 break;
   351                             case 0xA:
   352                                 { /* OCBP @Rn */
   353                                 uint32_t Rn = ((ir>>8)&0xF); 
   354                                 }
   355                                 break;
   356                             case 0xB:
   357                                 { /* OCBWB @Rn */
   358                                 uint32_t Rn = ((ir>>8)&0xF); 
   359                                 }
   360                                 break;
   361                             case 0xC:
   362                                 { /* MOVCA.L R0, @Rn */
   363                                 uint32_t Rn = ((ir>>8)&0xF); 
   364                                 tmp = sh4r.r[Rn];
   365                                 CHECKWALIGN32(tmp);
   366                                 MEM_WRITE_LONG( tmp, R0 );
   367                                 }
   368                                 break;
   369                             default:
   370                                 UNDEF();
   371                                 break;
   372                         }
   373                         break;
   374                     case 0x4:
   375                         { /* MOV.B Rm, @(R0, Rn) */
   376                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   377                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   378                         }
   379                         break;
   380                     case 0x5:
   381                         { /* MOV.W Rm, @(R0, Rn) */
   382                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   383                         CHECKWALIGN16( R0 + sh4r.r[Rn] );
   384                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   385                         }
   386                         break;
   387                     case 0x6:
   388                         { /* MOV.L Rm, @(R0, Rn) */
   389                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   390                         CHECKWALIGN32( R0 + sh4r.r[Rn] );
   391                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   392                         }
   393                         break;
   394                     case 0x7:
   395                         { /* MUL.L Rm, Rn */
   396                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   397                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   398                                                (sh4r.r[Rm] * sh4r.r[Rn]);
   399                         }
   400                         break;
   401                     case 0x8:
   402                         switch( (ir&0xFF0) >> 4 ) {
   403                             case 0x0:
   404                                 { /* CLRT */
   405                                 sh4r.t = 0;
   406                                 }
   407                                 break;
   408                             case 0x1:
   409                                 { /* SETT */
   410                                 sh4r.t = 1;
   411                                 }
   412                                 break;
   413                             case 0x2:
   414                                 { /* CLRMAC */
   415                                 sh4r.mac = 0;
   416                                 }
   417                                 break;
   418                             case 0x3:
   419                                 { /* LDTLB */
   420                                 /* TODO */
   421                                 }
   422                                 break;
   423                             case 0x4:
   424                                 { /* CLRS */
   425                                 sh4r.s = 0;
   426                                 }
   427                                 break;
   428                             case 0x5:
   429                                 { /* SETS */
   430                                 sh4r.s = 1;
   431                                 }
   432                                 break;
   433                             default:
   434                                 UNDEF();
   435                                 break;
   436                         }
   437                         break;
   438                     case 0x9:
   439                         switch( (ir&0xF0) >> 4 ) {
   440                             case 0x0:
   441                                 { /* NOP */
   442                                 /* NOP */
   443                                 }
   444                                 break;
   445                             case 0x1:
   446                                 { /* DIV0U */
   447                                 sh4r.m = sh4r.q = sh4r.t = 0;
   448                                 }
   449                                 break;
   450                             case 0x2:
   451                                 { /* MOVT Rn */
   452                                 uint32_t Rn = ((ir>>8)&0xF); 
   453                                 sh4r.r[Rn] = sh4r.t;
   454                                 }
   455                                 break;
   456                             default:
   457                                 UNDEF();
   458                                 break;
   459                         }
   460                         break;
   461                     case 0xA:
   462                         switch( (ir&0xF0) >> 4 ) {
   463                             case 0x0:
   464                                 { /* STS MACH, Rn */
   465                                 uint32_t Rn = ((ir>>8)&0xF); 
   466                                 sh4r.r[Rn] = (sh4r.mac>>32);
   467                                 }
   468                                 break;
   469                             case 0x1:
   470                                 { /* STS MACL, Rn */
   471                                 uint32_t Rn = ((ir>>8)&0xF); 
   472                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;
   473                                 }
   474                                 break;
   475                             case 0x2:
   476                                 { /* STS PR, Rn */
   477                                 uint32_t Rn = ((ir>>8)&0xF); 
   478                                 sh4r.r[Rn] = sh4r.pr;
   479                                 }
   480                                 break;
   481                             case 0x3:
   482                                 { /* STC SGR, Rn */
   483                                 uint32_t Rn = ((ir>>8)&0xF); 
   484                                 CHECKPRIV();
   485                                 sh4r.r[Rn] = sh4r.sgr;
   486                                 }
   487                                 break;
   488                             case 0x5:
   489                                 { /* STS FPUL, Rn */
   490                                 uint32_t Rn = ((ir>>8)&0xF); 
   491                                 sh4r.r[Rn] = sh4r.fpul;
   492                                 }
   493                                 break;
   494                             case 0x6:
   495                                 { /* STS FPSCR, Rn */
   496                                 uint32_t Rn = ((ir>>8)&0xF); 
   497                                 sh4r.r[Rn] = sh4r.fpscr;
   498                                 }
   499                                 break;
   500                             case 0xF:
   501                                 { /* STC DBR, Rn */
   502                                 uint32_t Rn = ((ir>>8)&0xF); 
   503                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
   504                                 }
   505                                 break;
   506                             default:
   507                                 UNDEF();
   508                                 break;
   509                         }
   510                         break;
   511                     case 0xB:
   512                         switch( (ir&0xFF0) >> 4 ) {
   513                             case 0x0:
   514                                 { /* RTS */
   515                                 CHECKSLOTILLEGAL();
   516                                 CHECKDEST( sh4r.pr );
   517                                 sh4r.in_delay_slot = 1;
   518                                 sh4r.pc = sh4r.new_pc;
   519                                 sh4r.new_pc = sh4r.pr;
   520                                 TRACE_RETURN( pc, sh4r.new_pc );
   521                                 return TRUE;
   522                                 }
   523                                 break;
   524                             case 0x1:
   525                                 { /* SLEEP */
   526                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   527                             	sh4r.sh4_state = SH4_STATE_STANDBY;
   528                                 } else {
   529                             	sh4r.sh4_state = SH4_STATE_SLEEP;
   530                                 }
   531                                 return FALSE; /* Halt CPU */
   532                                 }
   533                                 break;
   534                             case 0x2:
   535                                 { /* RTE */
   536                                 CHECKPRIV();
   537                                 CHECKDEST( sh4r.spc );
   538                                 CHECKSLOTILLEGAL();
   539                                 sh4r.in_delay_slot = 1;
   540                                 sh4r.pc = sh4r.new_pc;
   541                                 sh4r.new_pc = sh4r.spc;
   542                                 sh4_write_sr( sh4r.ssr );
   543                                 return TRUE;
   544                                 }
   545                                 break;
   546                             default:
   547                                 UNDEF();
   548                                 break;
   549                         }
   550                         break;
   551                     case 0xC:
   552                         { /* MOV.B @(R0, Rm), Rn */
   553                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   554                         sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );
   555                         }
   556                         break;
   557                     case 0xD:
   558                         { /* MOV.W @(R0, Rm), Rn */
   559                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   560                         CHECKRALIGN16( R0 + sh4r.r[Rm] );
   561                                            sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
   562                         }
   563                         break;
   564                     case 0xE:
   565                         { /* MOV.L @(R0, Rm), Rn */
   566                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   567                         CHECKRALIGN32( R0 + sh4r.r[Rm] );
   568                                            sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
   569                         }
   570                         break;
   571                     case 0xF:
   572                         { /* MAC.L @Rm+, @Rn+ */
   573                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   574                         CHECKRALIGN32( sh4r.r[Rm] );
   575                         CHECKRALIGN32( sh4r.r[Rn] );
   576                         int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
   577                         sh4r.r[Rn] += 4;
   578                         tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
   579                         sh4r.r[Rm] += 4;
   580                         if( sh4r.s ) {
   581                             /* 48-bit Saturation. Yuch */
   582                             if( tmpl < (int64_t)0xFFFF800000000000LL )
   583                                 tmpl = 0xFFFF800000000000LL;
   584                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   585                                 tmpl = 0x00007FFFFFFFFFFFLL;
   586                         }
   587                         sh4r.mac = tmpl;
   588                         }
   589                         break;
   590                     default:
   591                         UNDEF();
   592                         break;
   593                 }
   594                 break;
   595             case 0x1:
   596                 { /* MOV.L Rm, @(disp, Rn) */
   597                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   598                 tmp = sh4r.r[Rn] + disp;
   599                 CHECKWALIGN32( tmp );
   600                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   601                 }
   602                 break;
   603             case 0x2:
   604                 switch( ir&0xF ) {
   605                     case 0x0:
   606                         { /* MOV.B Rm, @Rn */
   607                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   608                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   609                         }
   610                         break;
   611                     case 0x1:
   612                         { /* MOV.W Rm, @Rn */
   613                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   614                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   615                         }
   616                         break;
   617                     case 0x2:
   618                         { /* MOV.L Rm, @Rn */
   619                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   620                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   621                         }
   622                         break;
   623                     case 0x4:
   624                         { /* MOV.B Rm, @-Rn */
   625                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   626                         sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   627                         }
   628                         break;
   629                     case 0x5:
   630                         { /* MOV.W Rm, @-Rn */
   631                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   632                         sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   633                         }
   634                         break;
   635                     case 0x6:
   636                         { /* MOV.L Rm, @-Rn */
   637                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   638                         sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   639                         }
   640                         break;
   641                     case 0x7:
   642                         { /* DIV0S Rm, Rn */
   643                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   644                         sh4r.q = sh4r.r[Rn]>>31;
   645                         sh4r.m = sh4r.r[Rm]>>31;
   646                         sh4r.t = sh4r.q ^ sh4r.m;
   647                         }
   648                         break;
   649                     case 0x8:
   650                         { /* TST Rm, Rn */
   651                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   652                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
   653                         }
   654                         break;
   655                     case 0x9:
   656                         { /* AND Rm, Rn */
   657                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   658                         sh4r.r[Rn] &= sh4r.r[Rm];
   659                         }
   660                         break;
   661                     case 0xA:
   662                         { /* XOR Rm, Rn */
   663                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   664                         sh4r.r[Rn] ^= sh4r.r[Rm];
   665                         }
   666                         break;
   667                     case 0xB:
   668                         { /* OR Rm, Rn */
   669                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   670                         sh4r.r[Rn] |= sh4r.r[Rm];
   671                         }
   672                         break;
   673                     case 0xC:
   674                         { /* CMP/STR Rm, Rn */
   675                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   676                         /* set T = 1 if any byte in RM & RN is the same */
   677                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   678                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   679                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   680                         }
   681                         break;
   682                     case 0xD:
   683                         { /* XTRCT Rm, Rn */
   684                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   685                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
   686                         }
   687                         break;
   688                     case 0xE:
   689                         { /* MULU.W Rm, Rn */
   690                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   691                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   692                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   693                         }
   694                         break;
   695                     case 0xF:
   696                         { /* MULS.W Rm, Rn */
   697                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   698                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   699                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   700                         }
   701                         break;
   702                     default:
   703                         UNDEF();
   704                         break;
   705                 }
   706                 break;
   707             case 0x3:
   708                 switch( ir&0xF ) {
   709                     case 0x0:
   710                         { /* CMP/EQ Rm, Rn */
   711                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   712                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
   713                         }
   714                         break;
   715                     case 0x2:
   716                         { /* CMP/HS Rm, Rn */
   717                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   718                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
   719                         }
   720                         break;
   721                     case 0x3:
   722                         { /* CMP/GE Rm, Rn */
   723                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   724                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   725                         }
   726                         break;
   727                     case 0x4:
   728                         { /* DIV1 Rm, Rn */
   729                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   730                         /* This is derived from the sh4 manual with some simplifications */
   731                         uint32_t tmp0, tmp1, tmp2, dir;
   733                         dir = sh4r.q ^ sh4r.m;
   734                         sh4r.q = (sh4r.r[Rn] >> 31);
   735                         tmp2 = sh4r.r[Rm];
   736                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   737                         tmp0 = sh4r.r[Rn];
   738                         if( dir ) {
   739                              sh4r.r[Rn] += tmp2;
   740                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   741                         } else {
   742                              sh4r.r[Rn] -= tmp2;
   743                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   744                         }
   745                         sh4r.q ^= sh4r.m ^ tmp1;
   746                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   747                         }
   748                         break;
   749                     case 0x5:
   750                         { /* DMULU.L Rm, Rn */
   751                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   752                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
   753                         }
   754                         break;
   755                     case 0x6:
   756                         { /* CMP/HI Rm, Rn */
   757                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   758                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
   759                         }
   760                         break;
   761                     case 0x7:
   762                         { /* CMP/GT Rm, Rn */
   763                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   764                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   765                         }
   766                         break;
   767                     case 0x8:
   768                         { /* SUB Rm, Rn */
   769                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   770                         sh4r.r[Rn] -= sh4r.r[Rm];
   771                         }
   772                         break;
   773                     case 0xA:
   774                         { /* SUBC Rm, Rn */
   775                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   776                         tmp = sh4r.r[Rn];
   777                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   778                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   779                         }
   780                         break;
   781                     case 0xB:
   782                         UNIMP(ir); /* SUBV Rm, Rn */
   783                         break;
   784                     case 0xC:
   785                         { /* ADD Rm, Rn */
   786                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   787                         sh4r.r[Rn] += sh4r.r[Rm];
   788                         }
   789                         break;
   790                     case 0xD:
   791                         { /* DMULS.L Rm, Rn */
   792                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   793                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
   794                         }
   795                         break;
   796                     case 0xE:
   797                         { /* ADDC Rm, Rn */
   798                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   799                         tmp = sh4r.r[Rn];
   800                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   801                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   802                         }
   803                         break;
   804                     case 0xF:
   805                         { /* ADDV Rm, Rn */
   806                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   807                         tmp = sh4r.r[Rn] + sh4r.r[Rm];
   808                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   809                         sh4r.r[Rn] = tmp;
   810                         }
   811                         break;
   812                     default:
   813                         UNDEF();
   814                         break;
   815                 }
   816                 break;
   817             case 0x4:
   818                 switch( ir&0xF ) {
   819                     case 0x0:
   820                         switch( (ir&0xF0) >> 4 ) {
   821                             case 0x0:
   822                                 { /* SHLL Rn */
   823                                 uint32_t Rn = ((ir>>8)&0xF); 
   824                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
   825                                 }
   826                                 break;
   827                             case 0x1:
   828                                 { /* DT Rn */
   829                                 uint32_t Rn = ((ir>>8)&0xF); 
   830                                 sh4r.r[Rn] --;
   831                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   832                                 }
   833                                 break;
   834                             case 0x2:
   835                                 { /* SHAL Rn */
   836                                 uint32_t Rn = ((ir>>8)&0xF); 
   837                                 sh4r.t = sh4r.r[Rn] >> 31;
   838                                 sh4r.r[Rn] <<= 1;
   839                                 }
   840                                 break;
   841                             default:
   842                                 UNDEF();
   843                                 break;
   844                         }
   845                         break;
   846                     case 0x1:
   847                         switch( (ir&0xF0) >> 4 ) {
   848                             case 0x0:
   849                                 { /* SHLR Rn */
   850                                 uint32_t Rn = ((ir>>8)&0xF); 
   851                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
   852                                 }
   853                                 break;
   854                             case 0x1:
   855                                 { /* CMP/PZ Rn */
   856                                 uint32_t Rn = ((ir>>8)&0xF); 
   857                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
   858                                 }
   859                                 break;
   860                             case 0x2:
   861                                 { /* SHAR Rn */
   862                                 uint32_t Rn = ((ir>>8)&0xF); 
   863                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
   864                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   865                                 }
   866                                 break;
   867                             default:
   868                                 UNDEF();
   869                                 break;
   870                         }
   871                         break;
   872                     case 0x2:
   873                         switch( (ir&0xF0) >> 4 ) {
   874                             case 0x0:
   875                                 { /* STS.L MACH, @-Rn */
   876                                 uint32_t Rn = ((ir>>8)&0xF); 
   877                                 sh4r.r[Rn] -= 4;
   878                                 CHECKWALIGN32( sh4r.r[Rn] );
   879                                 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
   880                                 }
   881                                 break;
   882                             case 0x1:
   883                                 { /* STS.L MACL, @-Rn */
   884                                 uint32_t Rn = ((ir>>8)&0xF); 
   885                                 sh4r.r[Rn] -= 4;
   886                                 CHECKWALIGN32( sh4r.r[Rn] );
   887                                 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
   888                                 }
   889                                 break;
   890                             case 0x2:
   891                                 { /* STS.L PR, @-Rn */
   892                                 uint32_t Rn = ((ir>>8)&0xF); 
   893                                 sh4r.r[Rn] -= 4;
   894                                 CHECKWALIGN32( sh4r.r[Rn] );
   895                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
   896                                 }
   897                                 break;
   898                             case 0x3:
   899                                 { /* STC.L SGR, @-Rn */
   900                                 uint32_t Rn = ((ir>>8)&0xF); 
   901                                 CHECKPRIV();
   902                                 sh4r.r[Rn] -= 4;
   903                                 CHECKWALIGN32( sh4r.r[Rn] );
   904                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
   905                                 }
   906                                 break;
   907                             case 0x5:
   908                                 { /* STS.L FPUL, @-Rn */
   909                                 uint32_t Rn = ((ir>>8)&0xF); 
   910                                 sh4r.r[Rn] -= 4;
   911                                 CHECKWALIGN32( sh4r.r[Rn] );
   912                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
   913                                 }
   914                                 break;
   915                             case 0x6:
   916                                 { /* STS.L FPSCR, @-Rn */
   917                                 uint32_t Rn = ((ir>>8)&0xF); 
   918                                 sh4r.r[Rn] -= 4;
   919                                 CHECKWALIGN32( sh4r.r[Rn] );
   920                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
   921                                 }
   922                                 break;
   923                             case 0xF:
   924                                 { /* STC.L DBR, @-Rn */
   925                                 uint32_t Rn = ((ir>>8)&0xF); 
   926                                 CHECKPRIV();
   927                                 sh4r.r[Rn] -= 4;
   928                                 CHECKWALIGN32( sh4r.r[Rn] );
   929                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
   930                                 }
   931                                 break;
   932                             default:
   933                                 UNDEF();
   934                                 break;
   935                         }
   936                         break;
   937                     case 0x3:
   938                         switch( (ir&0x80) >> 7 ) {
   939                             case 0x0:
   940                                 switch( (ir&0x70) >> 4 ) {
   941                                     case 0x0:
   942                                         { /* STC.L SR, @-Rn */
   943                                         uint32_t Rn = ((ir>>8)&0xF); 
   944                                         CHECKPRIV();
   945                                         sh4r.r[Rn] -= 4;
   946                                         CHECKWALIGN32( sh4r.r[Rn] );
   947                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
   948                                         }
   949                                         break;
   950                                     case 0x1:
   951                                         { /* STC.L GBR, @-Rn */
   952                                         uint32_t Rn = ((ir>>8)&0xF); 
   953                                         sh4r.r[Rn] -= 4;
   954                                         CHECKWALIGN32( sh4r.r[Rn] );
   955                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
   956                                         }
   957                                         break;
   958                                     case 0x2:
   959                                         { /* STC.L VBR, @-Rn */
   960                                         uint32_t Rn = ((ir>>8)&0xF); 
   961                                         CHECKPRIV();
   962                                         sh4r.r[Rn] -= 4;
   963                                         CHECKWALIGN32( sh4r.r[Rn] );
   964                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
   965                                         }
   966                                         break;
   967                                     case 0x3:
   968                                         { /* STC.L SSR, @-Rn */
   969                                         uint32_t Rn = ((ir>>8)&0xF); 
   970                                         CHECKPRIV();
   971                                         sh4r.r[Rn] -= 4;
   972                                         CHECKWALIGN32( sh4r.r[Rn] );
   973                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
   974                                         }
   975                                         break;
   976                                     case 0x4:
   977                                         { /* STC.L SPC, @-Rn */
   978                                         uint32_t Rn = ((ir>>8)&0xF); 
   979                                         CHECKPRIV();
   980                                         sh4r.r[Rn] -= 4;
   981                                         CHECKWALIGN32( sh4r.r[Rn] );
   982                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
   983                                         }
   984                                         break;
   985                                     default:
   986                                         UNDEF();
   987                                         break;
   988                                 }
   989                                 break;
   990                             case 0x1:
   991                                 { /* STC.L Rm_BANK, @-Rn */
   992                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   993                                 CHECKPRIV();
   994                                 sh4r.r[Rn] -= 4;
   995                                 CHECKWALIGN32( sh4r.r[Rn] );
   996                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
   997                                 }
   998                                 break;
   999                         }
  1000                         break;
  1001                     case 0x4:
  1002                         switch( (ir&0xF0) >> 4 ) {
  1003                             case 0x0:
  1004                                 { /* ROTL Rn */
  1005                                 uint32_t Rn = ((ir>>8)&0xF); 
  1006                                 sh4r.t = sh4r.r[Rn] >> 31;
  1007                                 sh4r.r[Rn] <<= 1;
  1008                                 sh4r.r[Rn] |= sh4r.t;
  1010                                 break;
  1011                             case 0x2:
  1012                                 { /* ROTCL Rn */
  1013                                 uint32_t Rn = ((ir>>8)&0xF); 
  1014                                 tmp = sh4r.r[Rn] >> 31;
  1015                                 sh4r.r[Rn] <<= 1;
  1016                                 sh4r.r[Rn] |= sh4r.t;
  1017                                 sh4r.t = tmp;
  1019                                 break;
  1020                             default:
  1021                                 UNDEF();
  1022                                 break;
  1024                         break;
  1025                     case 0x5:
  1026                         switch( (ir&0xF0) >> 4 ) {
  1027                             case 0x0:
  1028                                 { /* ROTR Rn */
  1029                                 uint32_t Rn = ((ir>>8)&0xF); 
  1030                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1031                                 sh4r.r[Rn] >>= 1;
  1032                                 sh4r.r[Rn] |= (sh4r.t << 31);
  1034                                 break;
  1035                             case 0x1:
  1036                                 { /* CMP/PL Rn */
  1037                                 uint32_t Rn = ((ir>>8)&0xF); 
  1038                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
  1040                                 break;
  1041                             case 0x2:
  1042                                 { /* ROTCR Rn */
  1043                                 uint32_t Rn = ((ir>>8)&0xF); 
  1044                                 tmp = sh4r.r[Rn] & 0x00000001;
  1045                                 sh4r.r[Rn] >>= 1;
  1046                                 sh4r.r[Rn] |= (sh4r.t << 31 );
  1047                                 sh4r.t = tmp;
  1049                                 break;
  1050                             default:
  1051                                 UNDEF();
  1052                                 break;
  1054                         break;
  1055                     case 0x6:
  1056                         switch( (ir&0xF0) >> 4 ) {
  1057                             case 0x0:
  1058                                 { /* LDS.L @Rm+, MACH */
  1059                                 uint32_t Rm = ((ir>>8)&0xF); 
  1060                                 CHECKRALIGN32( sh4r.r[Rm] );
  1061                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1062                                            (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
  1063                                 sh4r.r[Rm] += 4;
  1065                                 break;
  1066                             case 0x1:
  1067                                 { /* LDS.L @Rm+, MACL */
  1068                                 uint32_t Rm = ((ir>>8)&0xF); 
  1069                                 CHECKRALIGN32( sh4r.r[Rm] );
  1070                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1071                                            (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
  1072                                 sh4r.r[Rm] += 4;
  1074                                 break;
  1075                             case 0x2:
  1076                                 { /* LDS.L @Rm+, PR */
  1077                                 uint32_t Rm = ((ir>>8)&0xF); 
  1078                                 CHECKRALIGN32( sh4r.r[Rm] );
  1079                                 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
  1080                                 sh4r.r[Rm] += 4;
  1082                                 break;
  1083                             case 0x3:
  1084                                 { /* LDC.L @Rm+, SGR */
  1085                                 uint32_t Rm = ((ir>>8)&0xF); 
  1086                                 CHECKPRIV();
  1087                                 CHECKRALIGN32( sh4r.r[Rm] );
  1088                                 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
  1089                                 sh4r.r[Rm] +=4;
  1091                                 break;
  1092                             case 0x5:
  1093                                 { /* LDS.L @Rm+, FPUL */
  1094                                 uint32_t Rm = ((ir>>8)&0xF); 
  1095                                 CHECKRALIGN32( sh4r.r[Rm] );
  1096                                 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
  1097                                 sh4r.r[Rm] +=4;
  1099                                 break;
  1100                             case 0x6:
  1101                                 { /* LDS.L @Rm+, FPSCR */
  1102                                 uint32_t Rm = ((ir>>8)&0xF); 
  1103                                 CHECKRALIGN32( sh4r.r[Rm] );
  1104                                 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
  1105                                 sh4r.r[Rm] +=4;
  1106                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1108                                 break;
  1109                             case 0xF:
  1110                                 { /* LDC.L @Rm+, DBR */
  1111                                 uint32_t Rm = ((ir>>8)&0xF); 
  1112                                 CHECKPRIV();
  1113                                 CHECKRALIGN32( sh4r.r[Rm] );
  1114                                 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
  1115                                 sh4r.r[Rm] +=4;
  1117                                 break;
  1118                             default:
  1119                                 UNDEF();
  1120                                 break;
  1122                         break;
  1123                     case 0x7:
  1124                         switch( (ir&0x80) >> 7 ) {
  1125                             case 0x0:
  1126                                 switch( (ir&0x70) >> 4 ) {
  1127                                     case 0x0:
  1128                                         { /* LDC.L @Rm+, SR */
  1129                                         uint32_t Rm = ((ir>>8)&0xF); 
  1130                                         CHECKSLOTILLEGAL();
  1131                                         CHECKPRIV();
  1132                                         CHECKWALIGN32( sh4r.r[Rm] );
  1133                                         sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
  1134                                         sh4r.r[Rm] +=4;
  1136                                         break;
  1137                                     case 0x1:
  1138                                         { /* LDC.L @Rm+, GBR */
  1139                                         uint32_t Rm = ((ir>>8)&0xF); 
  1140                                         CHECKRALIGN32( sh4r.r[Rm] );
  1141                                         sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
  1142                                         sh4r.r[Rm] +=4;
  1144                                         break;
  1145                                     case 0x2:
  1146                                         { /* LDC.L @Rm+, VBR */
  1147                                         uint32_t Rm = ((ir>>8)&0xF); 
  1148                                         CHECKPRIV();
  1149                                         CHECKRALIGN32( sh4r.r[Rm] );
  1150                                         sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
  1151                                         sh4r.r[Rm] +=4;
  1153                                         break;
  1154                                     case 0x3:
  1155                                         { /* LDC.L @Rm+, SSR */
  1156                                         uint32_t Rm = ((ir>>8)&0xF); 
  1157                                         CHECKPRIV();
  1158                                         CHECKRALIGN32( sh4r.r[Rm] );
  1159                                         sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
  1160                                         sh4r.r[Rm] +=4;
  1162                                         break;
  1163                                     case 0x4:
  1164                                         { /* LDC.L @Rm+, SPC */
  1165                                         uint32_t Rm = ((ir>>8)&0xF); 
  1166                                         CHECKPRIV();
  1167                                         CHECKRALIGN32( sh4r.r[Rm] );
  1168                                         sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
  1169                                         sh4r.r[Rm] +=4;
  1171                                         break;
  1172                                     default:
  1173                                         UNDEF();
  1174                                         break;
  1176                                 break;
  1177                             case 0x1:
  1178                                 { /* LDC.L @Rm+, Rn_BANK */
  1179                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1180                                 CHECKPRIV();
  1181                                 CHECKRALIGN32( sh4r.r[Rm] );
  1182                                 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
  1183                                 sh4r.r[Rm] += 4;
  1185                                 break;
  1187                         break;
  1188                     case 0x8:
  1189                         switch( (ir&0xF0) >> 4 ) {
  1190                             case 0x0:
  1191                                 { /* SHLL2 Rn */
  1192                                 uint32_t Rn = ((ir>>8)&0xF); 
  1193                                 sh4r.r[Rn] <<= 2;
  1195                                 break;
  1196                             case 0x1:
  1197                                 { /* SHLL8 Rn */
  1198                                 uint32_t Rn = ((ir>>8)&0xF); 
  1199                                 sh4r.r[Rn] <<= 8;
  1201                                 break;
  1202                             case 0x2:
  1203                                 { /* SHLL16 Rn */
  1204                                 uint32_t Rn = ((ir>>8)&0xF); 
  1205                                 sh4r.r[Rn] <<= 16;
  1207                                 break;
  1208                             default:
  1209                                 UNDEF();
  1210                                 break;
  1212                         break;
  1213                     case 0x9:
  1214                         switch( (ir&0xF0) >> 4 ) {
  1215                             case 0x0:
  1216                                 { /* SHLR2 Rn */
  1217                                 uint32_t Rn = ((ir>>8)&0xF); 
  1218                                 sh4r.r[Rn] >>= 2;
  1220                                 break;
  1221                             case 0x1:
  1222                                 { /* SHLR8 Rn */
  1223                                 uint32_t Rn = ((ir>>8)&0xF); 
  1224                                 sh4r.r[Rn] >>= 8;
  1226                                 break;
  1227                             case 0x2:
  1228                                 { /* SHLR16 Rn */
  1229                                 uint32_t Rn = ((ir>>8)&0xF); 
  1230                                 sh4r.r[Rn] >>= 16;
  1232                                 break;
  1233                             default:
  1234                                 UNDEF();
  1235                                 break;
  1237                         break;
  1238                     case 0xA:
  1239                         switch( (ir&0xF0) >> 4 ) {
  1240                             case 0x0:
  1241                                 { /* LDS Rm, MACH */
  1242                                 uint32_t Rm = ((ir>>8)&0xF); 
  1243                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1244                                            (((uint64_t)sh4r.r[Rm])<<32);
  1246                                 break;
  1247                             case 0x1:
  1248                                 { /* LDS Rm, MACL */
  1249                                 uint32_t Rm = ((ir>>8)&0xF); 
  1250                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1251                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));
  1253                                 break;
  1254                             case 0x2:
  1255                                 { /* LDS Rm, PR */
  1256                                 uint32_t Rm = ((ir>>8)&0xF); 
  1257                                 sh4r.pr = sh4r.r[Rm];
  1259                                 break;
  1260                             case 0x3:
  1261                                 { /* LDC Rm, SGR */
  1262                                 uint32_t Rm = ((ir>>8)&0xF); 
  1263                                 CHECKPRIV();
  1264                                 sh4r.sgr = sh4r.r[Rm];
  1266                                 break;
  1267                             case 0x5:
  1268                                 { /* LDS Rm, FPUL */
  1269                                 uint32_t Rm = ((ir>>8)&0xF); 
  1270                                 sh4r.fpul = sh4r.r[Rm];
  1272                                 break;
  1273                             case 0x6:
  1274                                 { /* LDS Rm, FPSCR */
  1275                                 uint32_t Rm = ((ir>>8)&0xF); 
  1276                                 sh4r.fpscr = sh4r.r[Rm]; 
  1277                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1279                                 break;
  1280                             case 0xF:
  1281                                 { /* LDC Rm, DBR */
  1282                                 uint32_t Rm = ((ir>>8)&0xF); 
  1283                                 CHECKPRIV();
  1284                                 sh4r.dbr = sh4r.r[Rm];
  1286                                 break;
  1287                             default:
  1288                                 UNDEF();
  1289                                 break;
  1291                         break;
  1292                     case 0xB:
  1293                         switch( (ir&0xF0) >> 4 ) {
  1294                             case 0x0:
  1295                                 { /* JSR @Rn */
  1296                                 uint32_t Rn = ((ir>>8)&0xF); 
  1297                                 CHECKDEST( sh4r.r[Rn] );
  1298                                 CHECKSLOTILLEGAL();
  1299                                 sh4r.in_delay_slot = 1;
  1300                                 sh4r.pc = sh4r.new_pc;
  1301                                 sh4r.new_pc = sh4r.r[Rn];
  1302                                 sh4r.pr = pc + 4;
  1303                                 TRACE_CALL( pc, sh4r.new_pc );
  1304                                 return TRUE;
  1306                                 break;
  1307                             case 0x1:
  1308                                 { /* TAS.B @Rn */
  1309                                 uint32_t Rn = ((ir>>8)&0xF); 
  1310                                 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
  1311                                 sh4r.t = ( tmp == 0 ? 1 : 0 );
  1312                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
  1314                                 break;
  1315                             case 0x2:
  1316                                 { /* JMP @Rn */
  1317                                 uint32_t Rn = ((ir>>8)&0xF); 
  1318                                 CHECKDEST( sh4r.r[Rn] );
  1319                                 CHECKSLOTILLEGAL();
  1320                                 sh4r.in_delay_slot = 1;
  1321                                 sh4r.pc = sh4r.new_pc;
  1322                                 sh4r.new_pc = sh4r.r[Rn];
  1323                                 return TRUE;
  1325                                 break;
  1326                             default:
  1327                                 UNDEF();
  1328                                 break;
  1330                         break;
  1331                     case 0xC:
  1332                         { /* SHAD Rm, Rn */
  1333                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1334                         tmp = sh4r.r[Rm];
  1335                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1336                         else if( (tmp & 0x1F) == 0 )  
  1337                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
  1338                         else 
  1339                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
  1341                         break;
  1342                     case 0xD:
  1343                         { /* SHLD Rm, Rn */
  1344                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1345                         tmp = sh4r.r[Rm];
  1346                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1347                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
  1348                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
  1350                         break;
  1351                     case 0xE:
  1352                         switch( (ir&0x80) >> 7 ) {
  1353                             case 0x0:
  1354                                 switch( (ir&0x70) >> 4 ) {
  1355                                     case 0x0:
  1356                                         { /* LDC Rm, SR */
  1357                                         uint32_t Rm = ((ir>>8)&0xF); 
  1358                                         CHECKSLOTILLEGAL();
  1359                                         CHECKPRIV();
  1360                                         sh4_write_sr( sh4r.r[Rm] );
  1362                                         break;
  1363                                     case 0x1:
  1364                                         { /* LDC Rm, GBR */
  1365                                         uint32_t Rm = ((ir>>8)&0xF); 
  1366                                         sh4r.gbr = sh4r.r[Rm];
  1368                                         break;
  1369                                     case 0x2:
  1370                                         { /* LDC Rm, VBR */
  1371                                         uint32_t Rm = ((ir>>8)&0xF); 
  1372                                         CHECKPRIV();
  1373                                         sh4r.vbr = sh4r.r[Rm];
  1375                                         break;
  1376                                     case 0x3:
  1377                                         { /* LDC Rm, SSR */
  1378                                         uint32_t Rm = ((ir>>8)&0xF); 
  1379                                         CHECKPRIV();
  1380                                         sh4r.ssr = sh4r.r[Rm];
  1382                                         break;
  1383                                     case 0x4:
  1384                                         { /* LDC Rm, SPC */
  1385                                         uint32_t Rm = ((ir>>8)&0xF); 
  1386                                         CHECKPRIV();
  1387                                         sh4r.spc = sh4r.r[Rm];
  1389                                         break;
  1390                                     default:
  1391                                         UNDEF();
  1392                                         break;
  1394                                 break;
  1395                             case 0x1:
  1396                                 { /* LDC Rm, Rn_BANK */
  1397                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1398                                 CHECKPRIV();
  1399                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1401                                 break;
  1403                         break;
  1404                     case 0xF:
  1405                         { /* MAC.W @Rm+, @Rn+ */
  1406                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1407                         CHECKRALIGN16( sh4r.r[Rn] );
  1408                         CHECKRALIGN16( sh4r.r[Rm] );
  1409                         int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
  1410                         sh4r.r[Rn] += 2;
  1411                         stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
  1412                         sh4r.r[Rm] += 2;
  1413                         if( sh4r.s ) {
  1414                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
  1415                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
  1416                     	    sh4r.mac = 0x000000017FFFFFFFLL;
  1417                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
  1418                     	    sh4r.mac = 0x0000000180000000LL;
  1419                     	} else {
  1420                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1421                     		((uint32_t)(sh4r.mac + stmp));
  1423                         } else {
  1424                     	sh4r.mac += SIGNEXT32(stmp);
  1427                         break;
  1429                 break;
  1430             case 0x5:
  1431                 { /* MOV.L @(disp, Rm), Rn */
  1432                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  1433                 tmp = sh4r.r[Rm] + disp;
  1434                 CHECKRALIGN32( tmp );
  1435                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1437                 break;
  1438             case 0x6:
  1439                 switch( ir&0xF ) {
  1440                     case 0x0:
  1441                         { /* MOV.B @Rm, Rn */
  1442                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1443                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );
  1445                         break;
  1446                     case 0x1:
  1447                         { /* MOV.W @Rm, Rn */
  1448                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1449                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );
  1451                         break;
  1452                     case 0x2:
  1453                         { /* MOV.L @Rm, Rn */
  1454                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1455                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );
  1457                         break;
  1458                     case 0x3:
  1459                         { /* MOV Rm, Rn */
  1460                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1461                         sh4r.r[Rn] = sh4r.r[Rm];
  1463                         break;
  1464                     case 0x4:
  1465                         { /* MOV.B @Rm+, Rn */
  1466                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1467                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;
  1469                         break;
  1470                     case 0x5:
  1471                         { /* MOV.W @Rm+, Rn */
  1472                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1473                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;
  1475                         break;
  1476                     case 0x6:
  1477                         { /* MOV.L @Rm+, Rn */
  1478                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1479                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;
  1481                         break;
  1482                     case 0x7:
  1483                         { /* NOT Rm, Rn */
  1484                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1485                         sh4r.r[Rn] = ~sh4r.r[Rm];
  1487                         break;
  1488                     case 0x8:
  1489                         { /* SWAP.B Rm, Rn */
  1490                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1491                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
  1493                         break;
  1494                     case 0x9:
  1495                         { /* SWAP.W Rm, Rn */
  1496                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1497                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
  1499                         break;
  1500                     case 0xA:
  1501                         { /* NEGC Rm, Rn */
  1502                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1503                         tmp = 0 - sh4r.r[Rm];
  1504                         sh4r.r[Rn] = tmp - sh4r.t;
  1505                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
  1507                         break;
  1508                     case 0xB:
  1509                         { /* NEG Rm, Rn */
  1510                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1511                         sh4r.r[Rn] = 0 - sh4r.r[Rm];
  1513                         break;
  1514                     case 0xC:
  1515                         { /* EXTU.B Rm, Rn */
  1516                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1517                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
  1519                         break;
  1520                     case 0xD:
  1521                         { /* EXTU.W Rm, Rn */
  1522                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1523                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
  1525                         break;
  1526                     case 0xE:
  1527                         { /* EXTS.B Rm, Rn */
  1528                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1529                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
  1531                         break;
  1532                     case 0xF:
  1533                         { /* EXTS.W Rm, Rn */
  1534                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1535                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
  1537                         break;
  1539                 break;
  1540             case 0x7:
  1541                 { /* ADD #imm, Rn */
  1542                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1543                 sh4r.r[Rn] += imm;
  1545                 break;
  1546             case 0x8:
  1547                 switch( (ir&0xF00) >> 8 ) {
  1548                     case 0x0:
  1549                         { /* MOV.B R0, @(disp, Rn) */
  1550                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1551                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
  1553                         break;
  1554                     case 0x1:
  1555                         { /* MOV.W R0, @(disp, Rn) */
  1556                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1557                         tmp = sh4r.r[Rn] + disp;
  1558                         CHECKWALIGN16( tmp );
  1559                         MEM_WRITE_WORD( tmp, R0 );
  1561                         break;
  1562                     case 0x4:
  1563                         { /* MOV.B @(disp, Rm), R0 */
  1564                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1565                         R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );
  1567                         break;
  1568                     case 0x5:
  1569                         { /* MOV.W @(disp, Rm), R0 */
  1570                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1571                         tmp = sh4r.r[Rm] + disp;
  1572                         CHECKRALIGN16( tmp );
  1573                         R0 = MEM_READ_WORD( tmp );
  1575                         break;
  1576                     case 0x8:
  1577                         { /* CMP/EQ #imm, R0 */
  1578                         int32_t imm = SIGNEXT8(ir&0xFF); 
  1579                         sh4r.t = ( R0 == imm ? 1 : 0 );
  1581                         break;
  1582                     case 0x9:
  1583                         { /* BT disp */
  1584                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1585                         CHECKSLOTILLEGAL();
  1586                         if( sh4r.t ) {
  1587                             CHECKDEST( sh4r.pc + disp + 4 )
  1588                             sh4r.pc += disp + 4;
  1589                             sh4r.new_pc = sh4r.pc + 2;
  1590                             return TRUE;
  1593                         break;
  1594                     case 0xB:
  1595                         { /* BF disp */
  1596                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1597                         CHECKSLOTILLEGAL();
  1598                         if( !sh4r.t ) {
  1599                             CHECKDEST( sh4r.pc + disp + 4 )
  1600                             sh4r.pc += disp + 4;
  1601                             sh4r.new_pc = sh4r.pc + 2;
  1602                             return TRUE;
  1605                         break;
  1606                     case 0xD:
  1607                         { /* BT/S disp */
  1608                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1609                         CHECKSLOTILLEGAL();
  1610                         if( sh4r.t ) {
  1611                             CHECKDEST( sh4r.pc + disp + 4 )
  1612                             sh4r.in_delay_slot = 1;
  1613                             sh4r.pc = sh4r.new_pc;
  1614                             sh4r.new_pc = pc + disp + 4;
  1615                             sh4r.in_delay_slot = 1;
  1616                             return TRUE;
  1619                         break;
  1620                     case 0xF:
  1621                         { /* BF/S disp */
  1622                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1623                         CHECKSLOTILLEGAL();
  1624                         if( !sh4r.t ) {
  1625                             CHECKDEST( sh4r.pc + disp + 4 )
  1626                             sh4r.in_delay_slot = 1;
  1627                             sh4r.pc = sh4r.new_pc;
  1628                             sh4r.new_pc = pc + disp + 4;
  1629                             return TRUE;
  1632                         break;
  1633                     default:
  1634                         UNDEF();
  1635                         break;
  1637                 break;
  1638             case 0x9:
  1639                 { /* MOV.W @(disp, PC), Rn */
  1640                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  1641                 CHECKSLOTILLEGAL();
  1642                 tmp = pc + 4 + disp;
  1643                 sh4r.r[Rn] = MEM_READ_WORD( tmp );
  1645                 break;
  1646             case 0xA:
  1647                 { /* BRA disp */
  1648                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1649                 CHECKSLOTILLEGAL();
  1650                 CHECKDEST( sh4r.pc + disp + 4 );
  1651                 sh4r.in_delay_slot = 1;
  1652                 sh4r.pc = sh4r.new_pc;
  1653                 sh4r.new_pc = pc + 4 + disp;
  1654                 return TRUE;
  1656                 break;
  1657             case 0xB:
  1658                 { /* BSR disp */
  1659                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1660                 CHECKDEST( sh4r.pc + disp + 4 );
  1661                 CHECKSLOTILLEGAL();
  1662                 sh4r.in_delay_slot = 1;
  1663                 sh4r.pr = pc + 4;
  1664                 sh4r.pc = sh4r.new_pc;
  1665                 sh4r.new_pc = pc + 4 + disp;
  1666                 TRACE_CALL( pc, sh4r.new_pc );
  1667                 return TRUE;
  1669                 break;
  1670             case 0xC:
  1671                 switch( (ir&0xF00) >> 8 ) {
  1672                     case 0x0:
  1673                         { /* MOV.B R0, @(disp, GBR) */
  1674                         uint32_t disp = (ir&0xFF); 
  1675                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
  1677                         break;
  1678                     case 0x1:
  1679                         { /* MOV.W R0, @(disp, GBR) */
  1680                         uint32_t disp = (ir&0xFF)<<1; 
  1681                         tmp = sh4r.gbr + disp;
  1682                         CHECKWALIGN16( tmp );
  1683                         MEM_WRITE_WORD( tmp, R0 );
  1685                         break;
  1686                     case 0x2:
  1687                         { /* MOV.L R0, @(disp, GBR) */
  1688                         uint32_t disp = (ir&0xFF)<<2; 
  1689                         tmp = sh4r.gbr + disp;
  1690                         CHECKWALIGN32( tmp );
  1691                         MEM_WRITE_LONG( tmp, R0 );
  1693                         break;
  1694                     case 0x3:
  1695                         { /* TRAPA #imm */
  1696                         uint32_t imm = (ir&0xFF); 
  1697                         CHECKSLOTILLEGAL();
  1698                         MMIO_WRITE( MMU, TRA, imm<<2 );
  1699                         sh4r.pc += 2;
  1700                         sh4_raise_exception( EXC_TRAP );
  1702                         break;
  1703                     case 0x4:
  1704                         { /* MOV.B @(disp, GBR), R0 */
  1705                         uint32_t disp = (ir&0xFF); 
  1706                         R0 = MEM_READ_BYTE( sh4r.gbr + disp );
  1708                         break;
  1709                     case 0x5:
  1710                         { /* MOV.W @(disp, GBR), R0 */
  1711                         uint32_t disp = (ir&0xFF)<<1; 
  1712                         tmp = sh4r.gbr + disp;
  1713                         CHECKRALIGN16( tmp );
  1714                         R0 = MEM_READ_WORD( tmp );
  1716                         break;
  1717                     case 0x6:
  1718                         { /* MOV.L @(disp, GBR), R0 */
  1719                         uint32_t disp = (ir&0xFF)<<2; 
  1720                         tmp = sh4r.gbr + disp;
  1721                         CHECKRALIGN32( tmp );
  1722                         R0 = MEM_READ_LONG( tmp );
  1724                         break;
  1725                     case 0x7:
  1726                         { /* MOVA @(disp, PC), R0 */
  1727                         uint32_t disp = (ir&0xFF)<<2; 
  1728                         CHECKSLOTILLEGAL();
  1729                         R0 = (pc&0xFFFFFFFC) + disp + 4;
  1731                         break;
  1732                     case 0x8:
  1733                         { /* TST #imm, R0 */
  1734                         uint32_t imm = (ir&0xFF); 
  1735                         sh4r.t = (R0 & imm ? 0 : 1);
  1737                         break;
  1738                     case 0x9:
  1739                         { /* AND #imm, R0 */
  1740                         uint32_t imm = (ir&0xFF); 
  1741                         R0 &= imm;
  1743                         break;
  1744                     case 0xA:
  1745                         { /* XOR #imm, R0 */
  1746                         uint32_t imm = (ir&0xFF); 
  1747                         R0 ^= imm;
  1749                         break;
  1750                     case 0xB:
  1751                         { /* OR #imm, R0 */
  1752                         uint32_t imm = (ir&0xFF); 
  1753                         R0 |= imm;
  1755                         break;
  1756                     case 0xC:
  1757                         { /* TST.B #imm, @(R0, GBR) */
  1758                         uint32_t imm = (ir&0xFF); 
  1759                         sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );
  1761                         break;
  1762                     case 0xD:
  1763                         { /* AND.B #imm, @(R0, GBR) */
  1764                         uint32_t imm = (ir&0xFF); 
  1765                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1767                         break;
  1768                     case 0xE:
  1769                         { /* XOR.B #imm, @(R0, GBR) */
  1770                         uint32_t imm = (ir&0xFF); 
  1771                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1773                         break;
  1774                     case 0xF:
  1775                         { /* OR.B #imm, @(R0, GBR) */
  1776                         uint32_t imm = (ir&0xFF); 
  1777                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1779                         break;
  1781                 break;
  1782             case 0xD:
  1783                 { /* MOV.L @(disp, PC), Rn */
  1784                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  1785                 CHECKSLOTILLEGAL();
  1786                 tmp = (pc&0xFFFFFFFC) + disp + 4;
  1787                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1789                 break;
  1790             case 0xE:
  1791                 { /* MOV #imm, Rn */
  1792                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1793                 sh4r.r[Rn] = imm;
  1795                 break;
  1796             case 0xF:
  1797                 switch( ir&0xF ) {
  1798                     case 0x0:
  1799                         { /* FADD FRm, FRn */
  1800                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1801                         CHECKFPUEN();
  1802                         if( IS_FPU_DOUBLEPREC() ) {
  1803                     	DR(FRn) += DR(FRm);
  1804                         } else {
  1805                     	FR(FRn) += FR(FRm);
  1808                         break;
  1809                     case 0x1:
  1810                         { /* FSUB FRm, FRn */
  1811                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1812                         CHECKFPUEN();
  1813                         if( IS_FPU_DOUBLEPREC() ) {
  1814                     	DR(FRn) -= DR(FRm);
  1815                         } else {
  1816                     	FR(FRn) -= FR(FRm);
  1819                         break;
  1820                     case 0x2:
  1821                         { /* FMUL FRm, FRn */
  1822                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1823                         CHECKFPUEN();
  1824                         if( IS_FPU_DOUBLEPREC() ) {
  1825                     	DR(FRn) *= DR(FRm);
  1826                         } else {
  1827                     	FR(FRn) *= FR(FRm);
  1830                         break;
  1831                     case 0x3:
  1832                         { /* FDIV FRm, FRn */
  1833                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1834                         CHECKFPUEN();
  1835                         if( IS_FPU_DOUBLEPREC() ) {
  1836                     	DR(FRn) /= DR(FRm);
  1837                         } else {
  1838                     	FR(FRn) /= FR(FRm);
  1841                         break;
  1842                     case 0x4:
  1843                         { /* FCMP/EQ FRm, FRn */
  1844                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1845                         CHECKFPUEN();
  1846                         if( IS_FPU_DOUBLEPREC() ) {
  1847                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1848                         } else {
  1849                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1852                         break;
  1853                     case 0x5:
  1854                         { /* FCMP/GT FRm, FRn */
  1855                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1856                         CHECKFPUEN();
  1857                         if( IS_FPU_DOUBLEPREC() ) {
  1858                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1859                         } else {
  1860                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1863                         break;
  1864                     case 0x6:
  1865                         { /* FMOV @(R0, Rm), FRn */
  1866                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1867                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
  1869                         break;
  1870                     case 0x7:
  1871                         { /* FMOV FRm, @(R0, Rn) */
  1872                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1873                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
  1875                         break;
  1876                     case 0x8:
  1877                         { /* FMOV @Rm, FRn */
  1878                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1879                         MEM_FP_READ( sh4r.r[Rm], FRn );
  1881                         break;
  1882                     case 0x9:
  1883                         { /* FMOV @Rm+, FRn */
  1884                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1885                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
  1887                         break;
  1888                     case 0xA:
  1889                         { /* FMOV FRm, @Rn */
  1890                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1891                         MEM_FP_WRITE( sh4r.r[Rn], FRm );
  1893                         break;
  1894                     case 0xB:
  1895                         { /* FMOV FRm, @-Rn */
  1896                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1897                         sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
  1899                         break;
  1900                     case 0xC:
  1901                         { /* FMOV FRm, FRn */
  1902                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1903                         if( IS_FPU_DOUBLESIZE() )
  1904                     	DR(FRn) = DR(FRm);
  1905                         else
  1906                     	FR(FRn) = FR(FRm);
  1908                         break;
  1909                     case 0xD:
  1910                         switch( (ir&0xF0) >> 4 ) {
  1911                             case 0x0:
  1912                                 { /* FSTS FPUL, FRn */
  1913                                 uint32_t FRn = ((ir>>8)&0xF); 
  1914                                 CHECKFPUEN(); FR(FRn) = FPULf;
  1916                                 break;
  1917                             case 0x1:
  1918                                 { /* FLDS FRm, FPUL */
  1919                                 uint32_t FRm = ((ir>>8)&0xF); 
  1920                                 CHECKFPUEN(); FPULf = FR(FRm);
  1922                                 break;
  1923                             case 0x2:
  1924                                 { /* FLOAT FPUL, FRn */
  1925                                 uint32_t FRn = ((ir>>8)&0xF); 
  1926                                 CHECKFPUEN();
  1927                                 if( IS_FPU_DOUBLEPREC() ) {
  1928                             	if( FRn&1 ) { // No, really...
  1929                             	    dtmp = (double)FPULi;
  1930                             	    FR(FRn) = *(((float *)&dtmp)+1);
  1931                             	} else {
  1932                             	    DRF(FRn>>1) = (double)FPULi;
  1934                                 } else {
  1935                             	FR(FRn) = (float)FPULi;
  1938                                 break;
  1939                             case 0x3:
  1940                                 { /* FTRC FRm, FPUL */
  1941                                 uint32_t FRm = ((ir>>8)&0xF); 
  1942                                 CHECKFPUEN();
  1943                                 if( IS_FPU_DOUBLEPREC() ) {
  1944                             	if( FRm&1 ) {
  1945                             	    dtmp = 0;
  1946                             	    *(((float *)&dtmp)+1) = FR(FRm);
  1947                             	} else {
  1948                             	    dtmp = DRF(FRm>>1);
  1950                                     if( dtmp >= MAX_INTF )
  1951                                         FPULi = MAX_INT;
  1952                                     else if( dtmp <= MIN_INTF )
  1953                                         FPULi = MIN_INT;
  1954                                     else 
  1955                                         FPULi = (int32_t)dtmp;
  1956                                 } else {
  1957                             	ftmp = FR(FRm);
  1958                             	if( ftmp >= MAX_INTF )
  1959                             	    FPULi = MAX_INT;
  1960                             	else if( ftmp <= MIN_INTF )
  1961                             	    FPULi = MIN_INT;
  1962                             	else
  1963                             	    FPULi = (int32_t)ftmp;
  1966                                 break;
  1967                             case 0x4:
  1968                                 { /* FNEG FRn */
  1969                                 uint32_t FRn = ((ir>>8)&0xF); 
  1970                                 CHECKFPUEN();
  1971                                 if( IS_FPU_DOUBLEPREC() ) {
  1972                             	DR(FRn) = -DR(FRn);
  1973                                 } else {
  1974                                     FR(FRn) = -FR(FRn);
  1977                                 break;
  1978                             case 0x5:
  1979                                 { /* FABS FRn */
  1980                                 uint32_t FRn = ((ir>>8)&0xF); 
  1981                                 CHECKFPUEN();
  1982                                 if( IS_FPU_DOUBLEPREC() ) {
  1983                             	DR(FRn) = fabs(DR(FRn));
  1984                                 } else {
  1985                                     FR(FRn) = fabsf(FR(FRn));
  1988                                 break;
  1989                             case 0x6:
  1990                                 { /* FSQRT FRn */
  1991                                 uint32_t FRn = ((ir>>8)&0xF); 
  1992                                 CHECKFPUEN();
  1993                                 if( IS_FPU_DOUBLEPREC() ) {
  1994                             	DR(FRn) = sqrt(DR(FRn));
  1995                                 } else {
  1996                                     FR(FRn) = sqrtf(FR(FRn));
  1999                                 break;
  2000                             case 0x7:
  2001                                 { /* FSRRA FRn */
  2002                                 uint32_t FRn = ((ir>>8)&0xF); 
  2003                                 CHECKFPUEN();
  2004                                 if( !IS_FPU_DOUBLEPREC() ) {
  2005                             	FR(FRn) = 1.0/sqrtf(FR(FRn));
  2008                                 break;
  2009                             case 0x8:
  2010                                 { /* FLDI0 FRn */
  2011                                 uint32_t FRn = ((ir>>8)&0xF); 
  2012                                 CHECKFPUEN();
  2013                                 if( IS_FPU_DOUBLEPREC() ) {
  2014                             	DR(FRn) = 0.0;
  2015                                 } else {
  2016                                     FR(FRn) = 0.0;
  2019                                 break;
  2020                             case 0x9:
  2021                                 { /* FLDI1 FRn */
  2022                                 uint32_t FRn = ((ir>>8)&0xF); 
  2023                                 CHECKFPUEN();
  2024                                 if( IS_FPU_DOUBLEPREC() ) {
  2025                             	DR(FRn) = 1.0;
  2026                                 } else {
  2027                                     FR(FRn) = 1.0;
  2030                                 break;
  2031                             case 0xA:
  2032                                 { /* FCNVSD FPUL, FRn */
  2033                                 uint32_t FRn = ((ir>>8)&0xF); 
  2034                                 CHECKFPUEN();
  2035                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2036                             	DR(FRn) = (double)FPULf;
  2039                                 break;
  2040                             case 0xB:
  2041                                 { /* FCNVDS FRm, FPUL */
  2042                                 uint32_t FRm = ((ir>>8)&0xF); 
  2043                                 CHECKFPUEN();
  2044                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2045                             	FPULf = (float)DR(FRm);
  2048                                 break;
  2049                             case 0xE:
  2050                                 { /* FIPR FVm, FVn */
  2051                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  2052                                 CHECKFPUEN();
  2053                                 if( !IS_FPU_DOUBLEPREC() ) {
  2054                                     int tmp2 = FVn<<2;
  2055                                     tmp = FVm<<2;
  2056                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  2057                                         FR(tmp+1)*FR(tmp2+1) +
  2058                                         FR(tmp+2)*FR(tmp2+2) +
  2059                                         FR(tmp+3)*FR(tmp2+3);
  2062                                 break;
  2063                             case 0xF:
  2064                                 switch( (ir&0x100) >> 8 ) {
  2065                                     case 0x0:
  2066                                         { /* FSCA FPUL, FRn */
  2067                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  2068                                         CHECKFPUEN();
  2069                                         if( !IS_FPU_DOUBLEPREC() ) {
  2070                                     	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
  2071                                     	/*
  2072                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  2073                                             FR(FRn) = sinf(angle);
  2074                                             FR((FRn)+1) = cosf(angle);
  2075                                     	*/
  2078                                         break;
  2079                                     case 0x1:
  2080                                         switch( (ir&0x200) >> 9 ) {
  2081                                             case 0x0:
  2082                                                 { /* FTRV XMTRX, FVn */
  2083                                                 uint32_t FVn = ((ir>>10)&0x3); 
  2084                                                 CHECKFPUEN();
  2085                                                 if( !IS_FPU_DOUBLEPREC() ) {
  2086                                             	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
  2087                                             	/*
  2088                                                     tmp = FVn<<2;
  2089                                             	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
  2090                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  2091                                                     FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
  2092                                             	    xf[9]*fv[2] + xf[13]*fv[3];
  2093                                                     FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
  2094                                             	    xf[8]*fv[2] + xf[12]*fv[3];
  2095                                                     FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
  2096                                             	    xf[11]*fv[2] + xf[15]*fv[3];
  2097                                                     FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
  2098                                             	    xf[10]*fv[2] + xf[14]*fv[3];
  2099                                             	*/
  2102                                                 break;
  2103                                             case 0x1:
  2104                                                 switch( (ir&0xC00) >> 10 ) {
  2105                                                     case 0x0:
  2106                                                         { /* FSCHG */
  2107                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
  2109                                                         break;
  2110                                                     case 0x2:
  2111                                                         { /* FRCHG */
  2112                                                         CHECKFPUEN(); 
  2113                                                         sh4r.fpscr ^= FPSCR_FR; 
  2114                                                         sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  2116                                                         break;
  2117                                                     case 0x3:
  2118                                                         { /* UNDEF */
  2119                                                         UNDEF(ir);
  2121                                                         break;
  2122                                                     default:
  2123                                                         UNDEF();
  2124                                                         break;
  2126                                                 break;
  2128                                         break;
  2130                                 break;
  2131                             default:
  2132                                 UNDEF();
  2133                                 break;
  2135                         break;
  2136                     case 0xE:
  2137                         { /* FMAC FR0, FRm, FRn */
  2138                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2139                         CHECKFPUEN();
  2140                         if( IS_FPU_DOUBLEPREC() ) {
  2141                             DR(FRn) += DR(FRm)*DR(0);
  2142                         } else {
  2143                     	FR(FRn) += FR(FRm)*FR(0);
  2146                         break;
  2147                     default:
  2148                         UNDEF();
  2149                         break;
  2151                 break;
  2154     sh4r.pc = sh4r.new_pc;
  2155     sh4r.new_pc += 2;
  2156     sh4r.in_delay_slot = 0;
  2157     return TRUE;
.