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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 430:467519b050f4
prev401:f79327f39818
next490:1e0f9940e064
author nkeynes
date Mon Oct 08 12:09:06 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix compilation warnings
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     1 /**
     2  * $Id: sh4core.in,v 1.9 2007-10-08 12:06:01 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "eventq.h"
    25 #include "mem.h"
    26 #include "clock.h"
    27 #include "syscall.h"
    28 #include "sh4/sh4core.h"
    29 #include "sh4/sh4mmio.h"
    30 #include "sh4/intc.h"
    32 #define SH4_CALLTRACE 1
    34 #define MAX_INT 0x7FFFFFFF
    35 #define MIN_INT 0x80000000
    36 #define MAX_INTF 2147483647.0
    37 #define MIN_INTF -2147483648.0
    39 /********************** SH4 Module Definition ****************************/
    41 uint16_t *sh4_icache = NULL;
    42 uint32_t sh4_icache_addr = 0;
    44 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    45 {
    46     int i;
    47     sh4r.slice_cycle = 0;
    49     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    50 	if( sh4r.event_pending < nanosecs ) {
    51 	    sh4r.sh4_state = SH4_STATE_RUNNING;
    52 	    sh4r.slice_cycle = sh4r.event_pending;
    53 	}
    54     }
    56     if( sh4_breakpoint_count == 0 ) {
    57 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    58 	    if( SH4_EVENT_PENDING() ) {
    59 		if( sh4r.event_types & PENDING_EVENT ) {
    60 		    event_execute();
    61 		}
    62 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    63 		if( sh4r.event_types & PENDING_IRQ ) {
    64 		    sh4_accept_interrupt();
    65 		}
    66 	    }
    67 	    if( !sh4_execute_instruction() ) {
    68 		break;
    69 	    }
    70 	}
    71     } else {
    72 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    73 	    if( SH4_EVENT_PENDING() ) {
    74 		if( sh4r.event_types & PENDING_EVENT ) {
    75 		    event_execute();
    76 		}
    77 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    78 		if( sh4r.event_types & PENDING_IRQ ) {
    79 		    sh4_accept_interrupt();
    80 		}
    81 	    }
    83 	    if( !sh4_execute_instruction() )
    84 		break;
    85 #ifdef ENABLE_DEBUG_MODE
    86 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    87 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    88 		    break;
    89 		}
    90 	    }
    91 	    if( i != sh4_breakpoint_count ) {
    92 		dreamcast_stop();
    93 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    94 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    95 		break;
    96 	    }
    97 #endif	
    98 	}
    99     }
   101     /* If we aborted early, but the cpu is still technically running,
   102      * we're doing a hard abort - cut the timeslice back to what we
   103      * actually executed
   104      */
   105     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   106 	nanosecs = sh4r.slice_cycle;
   107     }
   108     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   109 	TMU_run_slice( nanosecs );
   110 	SCIF_run_slice( nanosecs );
   111     }
   112     return nanosecs;
   113 }
   115 /********************** SH4 emulation core  ****************************/
   117 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   118 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   120 #if(SH4_CALLTRACE == 1)
   121 #define MAX_CALLSTACK 32
   122 static struct call_stack {
   123     sh4addr_t call_addr;
   124     sh4addr_t target_addr;
   125     sh4addr_t stack_pointer;
   126 } call_stack[MAX_CALLSTACK];
   128 static int call_stack_depth = 0;
   129 int sh4_call_trace_on = 0;
   131 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   132 {
   133     if( call_stack_depth < MAX_CALLSTACK ) {
   134 	call_stack[call_stack_depth].call_addr = source;
   135 	call_stack[call_stack_depth].target_addr = dest;
   136 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   137     }
   138     call_stack_depth++;
   139 }
   141 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   142 {
   143     if( call_stack_depth > 0 ) {
   144 	call_stack_depth--;
   145     }
   146 }
   148 void fprint_stack_trace( FILE *f )
   149 {
   150     int i = call_stack_depth -1;
   151     if( i >= MAX_CALLSTACK )
   152 	i = MAX_CALLSTACK - 1;
   153     for( ; i >= 0; i-- ) {
   154 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   155 		 (call_stack_depth - i), call_stack[i].call_addr,
   156 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   157     }
   158 }
   160 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   161 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   162 #else
   163 #define TRACE_CALL( dest, rts ) 
   164 #define TRACE_RETURN( source, dest )
   165 #endif
   167 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   168 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   169 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   170 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   171 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   172 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   174 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   176 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   177 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   179 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   180 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   181 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   182 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   183 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   185 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   186 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   187 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   189 static void sh4_write_float( uint32_t addr, int reg )
   190 {
   191     if( IS_FPU_DOUBLESIZE() ) {
   192 	if( reg & 1 ) {
   193 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   194 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   195 	} else {
   196 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   197 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   198 	}
   199     } else {
   200 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   201     }
   202 }
   204 static void sh4_read_float( uint32_t addr, int reg )
   205 {
   206     if( IS_FPU_DOUBLESIZE() ) {
   207 	if( reg & 1 ) {
   208 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   209 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   210 	} else {
   211 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   212 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   213 	}
   214     } else {
   215 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   216     }
   217 }
   219 gboolean sh4_execute_instruction( void )
   220 {
   221     uint32_t pc;
   222     unsigned short ir;
   223     uint32_t tmp;
   224     float ftmp;
   225     double dtmp;
   227 #define R0 sh4r.r[0]
   228     pc = sh4r.pc;
   229     if( pc > 0xFFFFFF00 ) {
   230 	/* SYSCALL Magic */
   231 	syscall_invoke( pc );
   232 	sh4r.in_delay_slot = 0;
   233 	pc = sh4r.pc = sh4r.pr;
   234 	sh4r.new_pc = sh4r.pc + 2;
   235     }
   236     CHECKRALIGN16(pc);
   238     /* Read instruction */
   239     uint32_t pageaddr = pc >> 12;
   240     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   241 	ir = sh4_icache[(pc&0xFFF)>>1];
   242     } else {
   243 	sh4_icache = (uint16_t *)mem_get_page(pc);
   244 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   245 	    /* If someone's actually been so daft as to try to execute out of an IO
   246 	     * region, fallback on the full-blown memory read
   247 	     */
   248 	    sh4_icache = NULL;
   249 	    ir = MEM_READ_WORD(pc);
   250 	} else {
   251 	    sh4_icache_addr = pageaddr;
   252 	    ir = sh4_icache[(pc&0xFFF)>>1];
   253 	}
   254     }
   255 %%
   256 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   257 AND #imm, R0 {: R0 &= imm; :}
   258 AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
   259 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   260 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   261 OR #imm, R0  {: R0 |= imm; :}
   262 OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
   263 TAS.B @Rn {:
   264     tmp = MEM_READ_BYTE( sh4r.r[Rn] );
   265     sh4r.t = ( tmp == 0 ? 1 : 0 );
   266     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   267 :}
   268 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   269 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   270 TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}
   271 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   272 XOR #imm, R0 {: R0 ^= imm; :}
   273 XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
   274 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   276 ROTL Rn {:
   277     sh4r.t = sh4r.r[Rn] >> 31;
   278     sh4r.r[Rn] <<= 1;
   279     sh4r.r[Rn] |= sh4r.t;
   280 :}
   281 ROTR Rn {:
   282     sh4r.t = sh4r.r[Rn] & 0x00000001;
   283     sh4r.r[Rn] >>= 1;
   284     sh4r.r[Rn] |= (sh4r.t << 31);
   285 :}
   286 ROTCL Rn {:
   287     tmp = sh4r.r[Rn] >> 31;
   288     sh4r.r[Rn] <<= 1;
   289     sh4r.r[Rn] |= sh4r.t;
   290     sh4r.t = tmp;
   291 :}
   292 ROTCR Rn {:
   293     tmp = sh4r.r[Rn] & 0x00000001;
   294     sh4r.r[Rn] >>= 1;
   295     sh4r.r[Rn] |= (sh4r.t << 31 );
   296     sh4r.t = tmp;
   297 :}
   298 SHAD Rm, Rn {:
   299     tmp = sh4r.r[Rm];
   300     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   301     else if( (tmp & 0x1F) == 0 )  
   302         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   303     else 
   304 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   305 :}
   306 SHLD Rm, Rn {:
   307     tmp = sh4r.r[Rm];
   308     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   309     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   310     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   311 :}
   312 SHAL Rn {:
   313     sh4r.t = sh4r.r[Rn] >> 31;
   314     sh4r.r[Rn] <<= 1;
   315 :}
   316 SHAR Rn {:
   317     sh4r.t = sh4r.r[Rn] & 0x00000001;
   318     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   319 :}
   320 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   321 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   322 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   323 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   324 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   325 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   326 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   327 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   329 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   330 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   331 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   332 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   333 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   334 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   336 CLRT {: sh4r.t = 0; :}
   337 SETT {: sh4r.t = 1; :}
   338 CLRMAC {: sh4r.mac = 0; :}
   339 LDTLB {: /* TODO */ :}
   340 CLRS {: sh4r.s = 0; :}
   341 SETS {: sh4r.s = 1; :}
   342 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   343 NOP {: /* NOP */ :}
   345 PREF @Rn {:
   346      tmp = sh4r.r[Rn];
   347      if( (tmp & 0xFC000000) == 0xE0000000 ) {
   348 	 sh4_flush_store_queue(tmp);
   349      }
   350 :}
   351 OCBI @Rn {: :}
   352 OCBP @Rn {: :}
   353 OCBWB @Rn {: :}
   354 MOVCA.L R0, @Rn {:
   355     tmp = sh4r.r[Rn];
   356     CHECKWALIGN32(tmp);
   357     MEM_WRITE_LONG( tmp, R0 );
   358 :}
   359 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   360 MOV.W Rm, @(R0, Rn) {: 
   361     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   362     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   363 :}
   364 MOV.L Rm, @(R0, Rn) {:
   365     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   366     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   367 :}
   368 MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}
   369 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   370                     sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
   371 :}
   372 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   373                     sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
   374 :}
   375 MOV.L Rm, @(disp, Rn) {:
   376     tmp = sh4r.r[Rn] + disp;
   377     CHECKWALIGN32( tmp );
   378     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   379 :}
   380 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   381 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   382 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   383 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   384 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   385 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   386 MOV.L @(disp, Rm), Rn {:
   387     tmp = sh4r.r[Rm] + disp;
   388     CHECKRALIGN32( tmp );
   389     sh4r.r[Rn] = MEM_READ_LONG( tmp );
   390 :}
   391 MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}
   392 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}
   393 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}
   394 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   395 MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}
   396 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}
   397 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}
   398 MOV.L @(disp, PC), Rn {:
   399     CHECKSLOTILLEGAL();
   400     tmp = (pc&0xFFFFFFFC) + disp + 4;
   401     sh4r.r[Rn] = MEM_READ_LONG( tmp );
   402 :}
   403 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   404 MOV.W R0, @(disp, GBR) {:
   405     tmp = sh4r.gbr + disp;
   406     CHECKWALIGN16( tmp );
   407     MEM_WRITE_WORD( tmp, R0 );
   408 :}
   409 MOV.L R0, @(disp, GBR) {:
   410     tmp = sh4r.gbr + disp;
   411     CHECKWALIGN32( tmp );
   412     MEM_WRITE_LONG( tmp, R0 );
   413 :}
   414 MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}
   415 MOV.W @(disp, GBR), R0 {: 
   416     tmp = sh4r.gbr + disp;
   417     CHECKRALIGN16( tmp );
   418     R0 = MEM_READ_WORD( tmp );
   419 :}
   420 MOV.L @(disp, GBR), R0 {:
   421     tmp = sh4r.gbr + disp;
   422     CHECKRALIGN32( tmp );
   423     R0 = MEM_READ_LONG( tmp );
   424 :}
   425 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   426 MOV.W R0, @(disp, Rn) {: 
   427     tmp = sh4r.r[Rn] + disp;
   428     CHECKWALIGN16( tmp );
   429     MEM_WRITE_WORD( tmp, R0 );
   430 :}
   431 MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}
   432 MOV.W @(disp, Rm), R0 {: 
   433     tmp = sh4r.r[Rm] + disp;
   434     CHECKRALIGN16( tmp );
   435     R0 = MEM_READ_WORD( tmp );
   436 :}
   437 MOV.W @(disp, PC), Rn {:
   438     CHECKSLOTILLEGAL();
   439     tmp = pc + 4 + disp;
   440     sh4r.r[Rn] = MEM_READ_WORD( tmp );
   441 :}
   442 MOVA @(disp, PC), R0 {:
   443     CHECKSLOTILLEGAL();
   444     R0 = (pc&0xFFFFFFFC) + disp + 4;
   445 :}
   446 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   448 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   449 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   450 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   451 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   452 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   453 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   454 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   455 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   456 CMP/STR Rm, Rn {: 
   457     /* set T = 1 if any byte in RM & RN is the same */
   458     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   459     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   460              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   461 :}
   463 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   464 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   465 ADDC Rm, Rn {:
   466     tmp = sh4r.r[Rn];
   467     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   468     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   469 :}
   470 ADDV Rm, Rn {:
   471     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   472     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   473     sh4r.r[Rn] = tmp;
   474 :}
   475 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   476 DIV0S Rm, Rn {: 
   477     sh4r.q = sh4r.r[Rn]>>31;
   478     sh4r.m = sh4r.r[Rm]>>31;
   479     sh4r.t = sh4r.q ^ sh4r.m;
   480 :}
   481 DIV1 Rm, Rn {:
   482     /* This is derived from the sh4 manual with some simplifications */
   483     uint32_t tmp0, tmp1, tmp2, dir;
   485     dir = sh4r.q ^ sh4r.m;
   486     sh4r.q = (sh4r.r[Rn] >> 31);
   487     tmp2 = sh4r.r[Rm];
   488     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   489     tmp0 = sh4r.r[Rn];
   490     if( dir ) {
   491          sh4r.r[Rn] += tmp2;
   492          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   493     } else {
   494          sh4r.r[Rn] -= tmp2;
   495          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   496     }
   497     sh4r.q ^= sh4r.m ^ tmp1;
   498     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   499 :}
   500 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   501 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   502 DT Rn {:
   503     sh4r.r[Rn] --;
   504     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   505 :}
   506 MAC.W @Rm+, @Rn+ {:
   507     CHECKRALIGN16( sh4r.r[Rn] );
   508     CHECKRALIGN16( sh4r.r[Rm] );
   509     int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
   510     sh4r.r[Rn] += 2;
   511     stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
   512     sh4r.r[Rm] += 2;
   513     if( sh4r.s ) {
   514 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   515 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   516 	    sh4r.mac = 0x000000017FFFFFFFLL;
   517 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   518 	    sh4r.mac = 0x0000000180000000LL;
   519 	} else {
   520 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   521 		((uint32_t)(sh4r.mac + stmp));
   522 	}
   523     } else {
   524 	sh4r.mac += SIGNEXT32(stmp);
   525     }
   526 :}
   527 MAC.L @Rm+, @Rn+ {:
   528     CHECKRALIGN32( sh4r.r[Rm] );
   529     CHECKRALIGN32( sh4r.r[Rn] );
   530     int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
   531     sh4r.r[Rn] += 4;
   532     tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
   533     sh4r.r[Rm] += 4;
   534     if( sh4r.s ) {
   535         /* 48-bit Saturation. Yuch */
   536         if( tmpl < (int64_t)0xFFFF800000000000LL )
   537             tmpl = 0xFFFF800000000000LL;
   538         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   539             tmpl = 0x00007FFFFFFFFFFFLL;
   540     }
   541     sh4r.mac = tmpl;
   542 :}
   543 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   544                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   545 MULU.W Rm, Rn {:
   546     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   547                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   548 :}
   549 MULS.W Rm, Rn {:
   550     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   551                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   552 :}
   553 NEGC Rm, Rn {:
   554     tmp = 0 - sh4r.r[Rm];
   555     sh4r.r[Rn] = tmp - sh4r.t;
   556     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   557 :}
   558 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   559 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   560 SUBC Rm, Rn {: 
   561     tmp = sh4r.r[Rn];
   562     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   563     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   564 :}
   566 BRAF Rn {:
   567      CHECKSLOTILLEGAL();
   568      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   569      sh4r.in_delay_slot = 1;
   570      sh4r.pc = sh4r.new_pc;
   571      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   572      return TRUE;
   573 :}
   574 BSRF Rn {:
   575      CHECKSLOTILLEGAL();
   576      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   577      sh4r.in_delay_slot = 1;
   578      sh4r.pr = sh4r.pc + 4;
   579      sh4r.pc = sh4r.new_pc;
   580      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   581      TRACE_CALL( pc, sh4r.new_pc );
   582      return TRUE;
   583 :}
   584 BT disp {:
   585     CHECKSLOTILLEGAL();
   586     if( sh4r.t ) {
   587         CHECKDEST( sh4r.pc + disp + 4 )
   588         sh4r.pc += disp + 4;
   589         sh4r.new_pc = sh4r.pc + 2;
   590         return TRUE;
   591     }
   592 :}
   593 BF disp {:
   594     CHECKSLOTILLEGAL();
   595     if( !sh4r.t ) {
   596         CHECKDEST( sh4r.pc + disp + 4 )
   597         sh4r.pc += disp + 4;
   598         sh4r.new_pc = sh4r.pc + 2;
   599         return TRUE;
   600     }
   601 :}
   602 BT/S disp {:
   603     CHECKSLOTILLEGAL();
   604     if( sh4r.t ) {
   605         CHECKDEST( sh4r.pc + disp + 4 )
   606         sh4r.in_delay_slot = 1;
   607         sh4r.pc = sh4r.new_pc;
   608         sh4r.new_pc = pc + disp + 4;
   609         sh4r.in_delay_slot = 1;
   610         return TRUE;
   611     }
   612 :}
   613 BF/S disp {:
   614     CHECKSLOTILLEGAL();
   615     if( !sh4r.t ) {
   616         CHECKDEST( sh4r.pc + disp + 4 )
   617         sh4r.in_delay_slot = 1;
   618         sh4r.pc = sh4r.new_pc;
   619         sh4r.new_pc = pc + disp + 4;
   620         return TRUE;
   621     }
   622 :}
   623 BRA disp {:
   624     CHECKSLOTILLEGAL();
   625     CHECKDEST( sh4r.pc + disp + 4 );
   626     sh4r.in_delay_slot = 1;
   627     sh4r.pc = sh4r.new_pc;
   628     sh4r.new_pc = pc + 4 + disp;
   629     return TRUE;
   630 :}
   631 BSR disp {:
   632     CHECKDEST( sh4r.pc + disp + 4 );
   633     CHECKSLOTILLEGAL();
   634     sh4r.in_delay_slot = 1;
   635     sh4r.pr = pc + 4;
   636     sh4r.pc = sh4r.new_pc;
   637     sh4r.new_pc = pc + 4 + disp;
   638     TRACE_CALL( pc, sh4r.new_pc );
   639     return TRUE;
   640 :}
   641 TRAPA #imm {:
   642     CHECKSLOTILLEGAL();
   643     MMIO_WRITE( MMU, TRA, imm<<2 );
   644     sh4r.pc += 2;
   645     sh4_raise_exception( EXC_TRAP );
   646 :}
   647 RTS {: 
   648     CHECKSLOTILLEGAL();
   649     CHECKDEST( sh4r.pr );
   650     sh4r.in_delay_slot = 1;
   651     sh4r.pc = sh4r.new_pc;
   652     sh4r.new_pc = sh4r.pr;
   653     TRACE_RETURN( pc, sh4r.new_pc );
   654     return TRUE;
   655 :}
   656 SLEEP {:
   657     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   658 	sh4r.sh4_state = SH4_STATE_STANDBY;
   659     } else {
   660 	sh4r.sh4_state = SH4_STATE_SLEEP;
   661     }
   662     return FALSE; /* Halt CPU */
   663 :}
   664 RTE {:
   665     CHECKPRIV();
   666     CHECKDEST( sh4r.spc );
   667     CHECKSLOTILLEGAL();
   668     sh4r.in_delay_slot = 1;
   669     sh4r.pc = sh4r.new_pc;
   670     sh4r.new_pc = sh4r.spc;
   671     sh4_write_sr( sh4r.ssr );
   672     return TRUE;
   673 :}
   674 JMP @Rn {:
   675     CHECKDEST( sh4r.r[Rn] );
   676     CHECKSLOTILLEGAL();
   677     sh4r.in_delay_slot = 1;
   678     sh4r.pc = sh4r.new_pc;
   679     sh4r.new_pc = sh4r.r[Rn];
   680     return TRUE;
   681 :}
   682 JSR @Rn {:
   683     CHECKDEST( sh4r.r[Rn] );
   684     CHECKSLOTILLEGAL();
   685     sh4r.in_delay_slot = 1;
   686     sh4r.pc = sh4r.new_pc;
   687     sh4r.new_pc = sh4r.r[Rn];
   688     sh4r.pr = pc + 4;
   689     TRACE_CALL( pc, sh4r.new_pc );
   690     return TRUE;
   691 :}
   692 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   693 STS.L MACH, @-Rn {:
   694     sh4r.r[Rn] -= 4;
   695     CHECKWALIGN32( sh4r.r[Rn] );
   696     MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
   697 :}
   698 STC.L SR, @-Rn {:
   699     CHECKPRIV();
   700     sh4r.r[Rn] -= 4;
   701     CHECKWALIGN32( sh4r.r[Rn] );
   702     MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
   703 :}
   704 LDS.L @Rm+, MACH {:
   705     CHECKRALIGN32( sh4r.r[Rm] );
   706     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   707                (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
   708     sh4r.r[Rm] += 4;
   709 :}
   710 LDC.L @Rm+, SR {:
   711     CHECKSLOTILLEGAL();
   712     CHECKPRIV();
   713     CHECKWALIGN32( sh4r.r[Rm] );
   714     sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
   715     sh4r.r[Rm] +=4;
   716 :}
   717 LDS Rm, MACH {:
   718     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   719                (((uint64_t)sh4r.r[Rm])<<32);
   720 :}
   721 LDC Rm, SR {:
   722     CHECKSLOTILLEGAL();
   723     CHECKPRIV();
   724     sh4_write_sr( sh4r.r[Rm] );
   725 :}
   726 LDC Rm, SGR {:
   727     CHECKPRIV();
   728     sh4r.sgr = sh4r.r[Rm];
   729 :}
   730 LDC.L @Rm+, SGR {:
   731     CHECKPRIV();
   732     CHECKRALIGN32( sh4r.r[Rm] );
   733     sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
   734     sh4r.r[Rm] +=4;
   735 :}
   736 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   737 STS.L MACL, @-Rn {:
   738     sh4r.r[Rn] -= 4;
   739     CHECKWALIGN32( sh4r.r[Rn] );
   740     MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
   741 :}
   742 STC.L GBR, @-Rn {:
   743     sh4r.r[Rn] -= 4;
   744     CHECKWALIGN32( sh4r.r[Rn] );
   745     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
   746 :}
   747 LDS.L @Rm+, MACL {:
   748     CHECKRALIGN32( sh4r.r[Rm] );
   749     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   750                (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
   751     sh4r.r[Rm] += 4;
   752 :}
   753 LDC.L @Rm+, GBR {:
   754     CHECKRALIGN32( sh4r.r[Rm] );
   755     sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
   756     sh4r.r[Rm] +=4;
   757 :}
   758 LDS Rm, MACL {:
   759     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   760                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   761 :}
   762 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   763 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   764 STS.L PR, @-Rn {:
   765     sh4r.r[Rn] -= 4;
   766     CHECKWALIGN32( sh4r.r[Rn] );
   767     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
   768 :}
   769 STC.L VBR, @-Rn {:
   770     CHECKPRIV();
   771     sh4r.r[Rn] -= 4;
   772     CHECKWALIGN32( sh4r.r[Rn] );
   773     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
   774 :}
   775 LDS.L @Rm+, PR {:
   776     CHECKRALIGN32( sh4r.r[Rm] );
   777     sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
   778     sh4r.r[Rm] += 4;
   779 :}
   780 LDC.L @Rm+, VBR {:
   781     CHECKPRIV();
   782     CHECKRALIGN32( sh4r.r[Rm] );
   783     sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
   784     sh4r.r[Rm] +=4;
   785 :}
   786 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   787 LDC Rm, VBR {:
   788     CHECKPRIV();
   789     sh4r.vbr = sh4r.r[Rm];
   790 :}
   791 STC SGR, Rn {:
   792     CHECKPRIV();
   793     sh4r.r[Rn] = sh4r.sgr;
   794 :}
   795 STC.L SGR, @-Rn {:
   796     CHECKPRIV();
   797     sh4r.r[Rn] -= 4;
   798     CHECKWALIGN32( sh4r.r[Rn] );
   799     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
   800 :}
   801 STC.L SSR, @-Rn {:
   802     CHECKPRIV();
   803     sh4r.r[Rn] -= 4;
   804     CHECKWALIGN32( sh4r.r[Rn] );
   805     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
   806 :}
   807 LDC.L @Rm+, SSR {:
   808     CHECKPRIV();
   809     CHECKRALIGN32( sh4r.r[Rm] );
   810     sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
   811     sh4r.r[Rm] +=4;
   812 :}
   813 LDC Rm, SSR {:
   814     CHECKPRIV();
   815     sh4r.ssr = sh4r.r[Rm];
   816 :}
   817 STC.L SPC, @-Rn {:
   818     CHECKPRIV();
   819     sh4r.r[Rn] -= 4;
   820     CHECKWALIGN32( sh4r.r[Rn] );
   821     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
   822 :}
   823 LDC.L @Rm+, SPC {:
   824     CHECKPRIV();
   825     CHECKRALIGN32( sh4r.r[Rm] );
   826     sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
   827     sh4r.r[Rm] +=4;
   828 :}
   829 LDC Rm, SPC {:
   830     CHECKPRIV();
   831     sh4r.spc = sh4r.r[Rm];
   832 :}
   833 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
   834 STS.L FPUL, @-Rn {:
   835     sh4r.r[Rn] -= 4;
   836     CHECKWALIGN32( sh4r.r[Rn] );
   837     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
   838 :}
   839 LDS.L @Rm+, FPUL {:
   840     CHECKRALIGN32( sh4r.r[Rm] );
   841     sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
   842     sh4r.r[Rm] +=4;
   843 :}
   844 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
   845 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
   846 STS.L FPSCR, @-Rn {:
   847     sh4r.r[Rn] -= 4;
   848     CHECKWALIGN32( sh4r.r[Rn] );
   849     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
   850 :}
   851 LDS.L @Rm+, FPSCR {:
   852     CHECKRALIGN32( sh4r.r[Rm] );
   853     sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
   854     sh4r.r[Rm] +=4;
   855     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
   856 :}
   857 LDS Rm, FPSCR {: 
   858     sh4r.fpscr = sh4r.r[Rm]; 
   859     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
   860 :}
   861 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
   862 STC.L DBR, @-Rn {:
   863     CHECKPRIV();
   864     sh4r.r[Rn] -= 4;
   865     CHECKWALIGN32( sh4r.r[Rn] );
   866     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
   867 :}
   868 LDC.L @Rm+, DBR {:
   869     CHECKPRIV();
   870     CHECKRALIGN32( sh4r.r[Rm] );
   871     sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
   872     sh4r.r[Rm] +=4;
   873 :}
   874 LDC Rm, DBR {:
   875     CHECKPRIV();
   876     sh4r.dbr = sh4r.r[Rm];
   877 :}
   878 STC.L Rm_BANK, @-Rn {:
   879     CHECKPRIV();
   880     sh4r.r[Rn] -= 4;
   881     CHECKWALIGN32( sh4r.r[Rn] );
   882     MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
   883 :}
   884 LDC.L @Rm+, Rn_BANK {:
   885     CHECKPRIV();
   886     CHECKRALIGN32( sh4r.r[Rm] );
   887     sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
   888     sh4r.r[Rm] += 4;
   889 :}
   890 LDC Rm, Rn_BANK {:
   891     CHECKPRIV();
   892     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
   893 :}
   894 STC SR, Rn {: 
   895     CHECKPRIV();
   896     sh4r.r[Rn] = sh4_read_sr();
   897 :}
   898 STC GBR, Rn {:
   899     CHECKPRIV();
   900     sh4r.r[Rn] = sh4r.gbr;
   901 :}
   902 STC VBR, Rn {:
   903     CHECKPRIV();
   904     sh4r.r[Rn] = sh4r.vbr;
   905 :}
   906 STC SSR, Rn {:
   907     CHECKPRIV();
   908     sh4r.r[Rn] = sh4r.ssr;
   909 :}
   910 STC SPC, Rn {:
   911     CHECKPRIV();
   912     sh4r.r[Rn] = sh4r.spc;
   913 :}
   914 STC Rm_BANK, Rn {:
   915     CHECKPRIV();
   916     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   917 :}
   919 FADD FRm, FRn {:
   920     CHECKFPUEN();
   921     if( IS_FPU_DOUBLEPREC() ) {
   922 	DR(FRn) += DR(FRm);
   923     } else {
   924 	FR(FRn) += FR(FRm);
   925     }
   926 :}
   927 FSUB FRm, FRn {:
   928     CHECKFPUEN();
   929     if( IS_FPU_DOUBLEPREC() ) {
   930 	DR(FRn) -= DR(FRm);
   931     } else {
   932 	FR(FRn) -= FR(FRm);
   933     }
   934 :}
   936 FMUL FRm, FRn {:
   937     CHECKFPUEN();
   938     if( IS_FPU_DOUBLEPREC() ) {
   939 	DR(FRn) *= DR(FRm);
   940     } else {
   941 	FR(FRn) *= FR(FRm);
   942     }
   943 :}
   945 FDIV FRm, FRn {:
   946     CHECKFPUEN();
   947     if( IS_FPU_DOUBLEPREC() ) {
   948 	DR(FRn) /= DR(FRm);
   949     } else {
   950 	FR(FRn) /= FR(FRm);
   951     }
   952 :}
   954 FCMP/EQ FRm, FRn {:
   955     CHECKFPUEN();
   956     if( IS_FPU_DOUBLEPREC() ) {
   957 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
   958     } else {
   959 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
   960     }
   961 :}
   963 FCMP/GT FRm, FRn {:
   964     CHECKFPUEN();
   965     if( IS_FPU_DOUBLEPREC() ) {
   966 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
   967     } else {
   968 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
   969     }
   970 :}
   972 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
   973 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
   974 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
   975 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
   976 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   977 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   978 FMOV FRm, FRn {: 
   979     if( IS_FPU_DOUBLESIZE() )
   980 	DR(FRn) = DR(FRm);
   981     else
   982 	FR(FRn) = FR(FRm);
   983 :}
   984 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
   985 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
   986 FLOAT FPUL, FRn {: 
   987     CHECKFPUEN();
   988     if( IS_FPU_DOUBLEPREC() ) {
   989 	if( FRn&1 ) { // No, really...
   990 	    dtmp = (double)FPULi;
   991 	    FR(FRn) = *(((float *)&dtmp)+1);
   992 	} else {
   993 	    DRF(FRn>>1) = (double)FPULi;
   994 	}
   995     } else {
   996 	FR(FRn) = (float)FPULi;
   997     }
   998 :}
   999 FTRC FRm, FPUL {:
  1000     CHECKFPUEN();
  1001     if( IS_FPU_DOUBLEPREC() ) {
  1002 	if( FRm&1 ) {
  1003 	    dtmp = 0;
  1004 	    *(((float *)&dtmp)+1) = FR(FRm);
  1005 	} else {
  1006 	    dtmp = DRF(FRm>>1);
  1008         if( dtmp >= MAX_INTF )
  1009             FPULi = MAX_INT;
  1010         else if( dtmp <= MIN_INTF )
  1011             FPULi = MIN_INT;
  1012         else 
  1013             FPULi = (int32_t)dtmp;
  1014     } else {
  1015 	ftmp = FR(FRm);
  1016 	if( ftmp >= MAX_INTF )
  1017 	    FPULi = MAX_INT;
  1018 	else if( ftmp <= MIN_INTF )
  1019 	    FPULi = MIN_INT;
  1020 	else
  1021 	    FPULi = (int32_t)ftmp;
  1023 :}
  1024 FNEG FRn {:
  1025     CHECKFPUEN();
  1026     if( IS_FPU_DOUBLEPREC() ) {
  1027 	DR(FRn) = -DR(FRn);
  1028     } else {
  1029         FR(FRn) = -FR(FRn);
  1031 :}
  1032 FABS FRn {:
  1033     CHECKFPUEN();
  1034     if( IS_FPU_DOUBLEPREC() ) {
  1035 	DR(FRn) = fabs(DR(FRn));
  1036     } else {
  1037         FR(FRn) = fabsf(FR(FRn));
  1039 :}
  1040 FSQRT FRn {:
  1041     CHECKFPUEN();
  1042     if( IS_FPU_DOUBLEPREC() ) {
  1043 	DR(FRn) = sqrt(DR(FRn));
  1044     } else {
  1045         FR(FRn) = sqrtf(FR(FRn));
  1047 :}
  1048 FLDI0 FRn {:
  1049     CHECKFPUEN();
  1050     if( IS_FPU_DOUBLEPREC() ) {
  1051 	DR(FRn) = 0.0;
  1052     } else {
  1053         FR(FRn) = 0.0;
  1055 :}
  1056 FLDI1 FRn {:
  1057     CHECKFPUEN();
  1058     if( IS_FPU_DOUBLEPREC() ) {
  1059 	DR(FRn) = 1.0;
  1060     } else {
  1061         FR(FRn) = 1.0;
  1063 :}
  1064 FMAC FR0, FRm, FRn {:
  1065     CHECKFPUEN();
  1066     if( IS_FPU_DOUBLEPREC() ) {
  1067         DR(FRn) += DR(FRm)*DR(0);
  1068     } else {
  1069 	FR(FRn) += FR(FRm)*FR(0);
  1071 :}
  1072 FRCHG {: 
  1073     CHECKFPUEN(); 
  1074     sh4r.fpscr ^= FPSCR_FR; 
  1075     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1076 :}
  1077 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1078 FCNVSD FPUL, FRn {:
  1079     CHECKFPUEN();
  1080     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1081 	DR(FRn) = (double)FPULf;
  1083 :}
  1084 FCNVDS FRm, FPUL {:
  1085     CHECKFPUEN();
  1086     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1087 	FPULf = (float)DR(FRm);
  1089 :}
  1091 FSRRA FRn {:
  1092     CHECKFPUEN();
  1093     if( !IS_FPU_DOUBLEPREC() ) {
  1094 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1096 :}
  1097 FIPR FVm, FVn {:
  1098     CHECKFPUEN();
  1099     if( !IS_FPU_DOUBLEPREC() ) {
  1100         int tmp2 = FVn<<2;
  1101         tmp = FVm<<2;
  1102         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1103             FR(tmp+1)*FR(tmp2+1) +
  1104             FR(tmp+2)*FR(tmp2+2) +
  1105             FR(tmp+3)*FR(tmp2+3);
  1107 :}
  1108 FSCA FPUL, FRn {:
  1109     CHECKFPUEN();
  1110     if( !IS_FPU_DOUBLEPREC() ) {
  1111 	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
  1112 	/*
  1113         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  1114         FR(FRn) = sinf(angle);
  1115         FR((FRn)+1) = cosf(angle);
  1116 	*/
  1118 :}
  1119 FTRV XMTRX, FVn {:
  1120     CHECKFPUEN();
  1121     if( !IS_FPU_DOUBLEPREC() ) {
  1122 	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
  1123 	/*
  1124         tmp = FVn<<2;
  1125 	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
  1126         float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1127         FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
  1128 	    xf[9]*fv[2] + xf[13]*fv[3];
  1129         FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
  1130 	    xf[8]*fv[2] + xf[12]*fv[3];
  1131         FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
  1132 	    xf[11]*fv[2] + xf[15]*fv[3];
  1133         FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
  1134 	    xf[10]*fv[2] + xf[14]*fv[3];
  1135 	*/
  1137 :}
  1138 UNDEF {:
  1139     UNDEF(ir);
  1140 :}
  1141 %%
  1142     sh4r.pc = sh4r.new_pc;
  1143     sh4r.new_pc += 2;
  1144     sh4r.in_delay_slot = 0;
  1145     return TRUE;
.