4 * SH4 parent module for all CPU modes and SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
24 #include "dreamcast.h"
25 #include "sh4/sh4core.h"
26 #include "sh4/sh4mmio.h"
28 #include "sh4/xltcache.h"
29 #include "sh4/sh4stat.h"
30 #include "sh4/sh4trans.h"
35 void sh4_init( void );
36 void sh4_xlat_init( void );
37 void sh4_reset( void );
38 void sh4_start( void );
39 void sh4_stop( void );
40 void sh4_save_state( FILE *f );
41 int sh4_load_state( FILE *f );
43 uint32_t sh4_run_slice( uint32_t );
44 uint32_t sh4_xlat_run_slice( uint32_t );
46 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
47 sh4_start, sh4_run_slice, sh4_stop,
48 sh4_save_state, sh4_load_state };
50 struct sh4_registers sh4r;
51 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
52 int sh4_breakpoint_count = 0;
53 sh4ptr_t sh4_main_ram;
54 gboolean sh4_starting = FALSE;
55 static gboolean sh4_use_translator = FALSE;
56 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
58 void sh4_set_use_xlat( gboolean use )
60 // No-op if the translator was not built
65 sh4_module.run_time_slice = sh4_xlat_run_slice;
67 sh4_module.run_time_slice = sh4_run_slice;
69 sh4_use_translator = use;
73 gboolean sh4_is_using_xlat()
75 return sh4_use_translator;
80 register_io_regions( mmio_list_sh4mmio );
81 sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
93 if( sh4_use_translator ) {
97 /* zero everything out, for the sake of having a consistent state. */
98 memset( &sh4r, 0, sizeof(sh4r) );
100 /* Resume running if we were halted */
101 sh4r.sh4_state = SH4_STATE_RUNNING;
103 sh4r.pc = 0xA0000000;
104 sh4r.new_pc= 0xA0000002;
105 sh4r.vbr = 0x00000000;
106 sh4r.fpscr = 0x00040001;
107 sh4r.sr = 0x700000F0;
108 sh4r.fr_bank = &sh4r.fr[0][0];
110 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
111 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
113 /* Peripheral modules */
124 if( sh4_use_translator ) {
125 /* If we were running with the translator, update new_pc and in_delay_slot */
126 sh4r.new_pc = sh4r.pc+2;
127 sh4r.in_delay_slot = FALSE;
132 void sh4_save_state( FILE *f )
134 if( sh4_use_translator ) {
135 /* If we were running with the translator, update new_pc and in_delay_slot */
136 sh4r.new_pc = sh4r.pc+2;
137 sh4r.in_delay_slot = FALSE;
140 fwrite( &sh4r, sizeof(sh4r), 1, f );
142 INTC_save_state( f );
144 SCIF_save_state( f );
147 int sh4_load_state( FILE * f )
149 if( sh4_use_translator ) {
152 fread( &sh4r, sizeof(sh4r), 1, f );
153 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
155 INTC_load_state( f );
157 return SCIF_load_state( f );
161 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
163 sh4_breakpoints[sh4_breakpoint_count].address = pc;
164 sh4_breakpoints[sh4_breakpoint_count].type = type;
165 if( sh4_use_translator ) {
166 xlat_invalidate_word( pc );
168 sh4_breakpoint_count++;
171 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
175 for( i=0; i<sh4_breakpoint_count; i++ ) {
176 if( sh4_breakpoints[i].address == pc &&
177 sh4_breakpoints[i].type == type ) {
178 while( ++i < sh4_breakpoint_count ) {
179 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
180 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
182 if( sh4_use_translator ) {
183 xlat_invalidate_word( pc );
185 sh4_breakpoint_count--;
192 int sh4_get_breakpoint( uint32_t pc )
195 for( i=0; i<sh4_breakpoint_count; i++ ) {
196 if( sh4_breakpoints[i].address == pc )
197 return sh4_breakpoints[i].type;
202 void sh4_set_pc( int pc )
209 /******************************* Support methods ***************************/
211 static void sh4_switch_banks( )
215 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
216 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
217 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
220 void sh4_write_sr( uint32_t newval )
222 int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
223 int newbank = (newval&SR_MDRB) == SR_MDRB;
224 if( oldbank != newbank )
227 sh4r.t = (newval&SR_T) ? 1 : 0;
228 sh4r.s = (newval&SR_S) ? 1 : 0;
229 sh4r.m = (newval&SR_M) ? 1 : 0;
230 sh4r.q = (newval&SR_Q) ? 1 : 0;
234 uint32_t sh4_read_sr( void )
236 /* synchronize sh4r.sr with the various bitflags */
237 sh4r.sr &= SR_MQSTMASK;
238 if( sh4r.t ) sh4r.sr |= SR_T;
239 if( sh4r.s ) sh4r.sr |= SR_S;
240 if( sh4r.m ) sh4r.sr |= SR_M;
241 if( sh4r.q ) sh4r.sr |= SR_Q;
247 #define RAISE( x, v ) do{ \
248 if( sh4r.vbr == 0 ) { \
249 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
250 dreamcast_stop(); return FALSE; \
252 sh4r.spc = sh4r.pc; \
253 sh4r.ssr = sh4_read_sr(); \
254 sh4r.sgr = sh4r.r[15]; \
255 MMIO_WRITE(MMU,EXPEVT,x); \
256 sh4r.pc = sh4r.vbr + v; \
257 sh4r.new_pc = sh4r.pc + 2; \
258 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
259 if( sh4r.in_delay_slot ) { \
260 sh4r.in_delay_slot = 0; \
264 return TRUE; } while(0)
267 * Raise a general CPU exception for the specified exception code.
268 * (NOT for TRAPA or TLB exceptions)
270 gboolean sh4_raise_exception( int code )
272 RAISE( code, EXV_EXCEPTION );
276 * Raise a CPU reset exception with the specified exception code.
278 gboolean sh4_raise_reset( int code )
280 // FIXME: reset modules as per "manual reset"
282 MMIO_WRITE(MMU,EXPEVT,code);
284 sh4r.pc = 0xA0000000;
285 sh4r.new_pc = sh4r.pc + 2;
286 sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
290 gboolean sh4_raise_trap( int trap )
292 MMIO_WRITE( MMU, TRA, trap<<2 );
293 RAISE( EXC_TRAP, EXV_EXCEPTION );
296 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
297 if( sh4r.in_delay_slot ) {
298 return sh4_raise_exception(slot_code);
300 return sh4_raise_exception(normal_code);
304 gboolean sh4_raise_tlb_exception( int code )
306 RAISE( code, EXV_TLBMISS );
309 void sh4_accept_interrupt( void )
311 uint32_t code = intc_accept_interrupt();
312 sh4r.ssr = sh4_read_sr();
314 sh4r.sgr = sh4r.r[15];
315 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
316 MMIO_WRITE( MMU, INTEVT, code );
317 sh4r.pc = sh4r.vbr + 0x600;
318 sh4r.new_pc = sh4r.pc + 2;
319 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
322 void signsat48( void )
324 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
325 sh4r.mac = 0xFFFF800000000000LL;
326 else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
327 sh4r.mac = 0x00007FFFFFFFFFFFLL;
330 void sh4_fsca( uint32_t anglei, float *fr )
332 float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
338 * Enter sleep mode (eg by executing a SLEEP instruction).
339 * Sets sh4_state appropriately and ensures any stopping peripheral modules
344 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
345 sh4r.sh4_state = SH4_STATE_STANDBY;
346 /* Bring all running peripheral modules up to date, and then halt them. */
347 TMU_run_slice( sh4r.slice_cycle );
348 SCIF_run_slice( sh4r.slice_cycle );
350 if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
351 sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
352 /* Halt DMAC but other peripherals still running */
355 sh4r.sh4_state = SH4_STATE_SLEEP;
358 if( sh4_xlat_is_running() ) {
359 sh4_translate_exit( XLAT_EXIT_SLEEP );
364 * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
365 * and restarts any peripheral devices that were stopped.
367 void sh4_wakeup(void)
369 switch( sh4r.sh4_state ) {
370 case SH4_STATE_STANDBY:
372 case SH4_STATE_DEEP_SLEEP:
374 case SH4_STATE_SLEEP:
377 sh4r.sh4_state = SH4_STATE_RUNNING;
381 * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
382 * Returns when either the SH4 wakes up (interrupt received) or the end of
383 * the slice is reached. Updates sh4.slice_cycle with the exit time and
384 * returns the same value.
386 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
388 int sleep_state = sh4r.sh4_state;
389 assert( sleep_state != SH4_STATE_RUNNING );
390 while( sh4r.event_pending < nanosecs ) {
391 sh4r.slice_cycle = sh4r.event_pending;
392 if( sh4r.event_types & PENDING_EVENT ) {
395 if( sh4r.event_types & PENDING_IRQ ) {
397 nanosecs = sh4r.event_pending;
401 sh4r.slice_cycle = nanosecs;
402 if( sleep_state != SH4_STATE_STANDBY ) {
403 TMU_run_slice( nanosecs );
404 SCIF_run_slice( nanosecs );
406 return sh4r.slice_cycle;
411 * Compute the matrix tranform of fv given the matrix xf.
412 * Both fv and xf are word-swapped as per the sh4r.fr banks
414 void sh4_ftrv( float *target, float *xf )
416 float fv[4] = { target[1], target[0], target[3], target[2] };
417 target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
418 xf[9]*fv[2] + xf[13]*fv[3];
419 target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
420 xf[8]*fv[2] + xf[12]*fv[3];
421 target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
422 xf[11]*fv[2] + xf[15]*fv[3];
423 target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
424 xf[10]*fv[2] + xf[14]*fv[3];
427 gboolean sh4_has_page( sh4vma_t vma )
429 sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
430 return addr != MMU_VMA_ERROR && mem_has_page(addr);
.