4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
24 #include "dreamcast.h"
29 #include "sh4/sh4core.h"
30 #include "sh4/sh4mmio.h"
33 #define SH4_CALLTRACE 1
35 #define MAX_INT 0x7FFFFFFF
36 #define MIN_INT 0x80000000
37 #define MAX_INTF 2147483647.0
38 #define MIN_INTF -2147483648.0
40 /********************** SH4 Module Definition ****************************/
42 uint32_t sh4_run_slice( uint32_t nanosecs )
47 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
48 sh4_sleep_run_slice(nanosecs);
51 if( sh4_breakpoint_count == 0 ) {
52 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
53 if( SH4_EVENT_PENDING() ) {
54 if( sh4r.event_types & PENDING_EVENT ) {
57 /* Eventq execute may (quite likely) deliver an immediate IRQ */
58 if( sh4r.event_types & PENDING_IRQ ) {
59 sh4_accept_interrupt();
62 if( !sh4_execute_instruction() ) {
67 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
68 if( SH4_EVENT_PENDING() ) {
69 if( sh4r.event_types & PENDING_EVENT ) {
72 /* Eventq execute may (quite likely) deliver an immediate IRQ */
73 if( sh4r.event_types & PENDING_IRQ ) {
74 sh4_accept_interrupt();
78 if( !sh4_execute_instruction() )
80 #ifdef ENABLE_DEBUG_MODE
81 for( i=0; i<sh4_breakpoint_count; i++ ) {
82 if( sh4_breakpoints[i].address == sh4r.pc ) {
86 if( i != sh4_breakpoint_count ) {
88 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
89 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
96 /* If we aborted early, but the cpu is still technically running,
97 * we're doing a hard abort - cut the timeslice back to what we
100 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
101 nanosecs = sh4r.slice_cycle;
103 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
104 TMU_run_slice( nanosecs );
105 SCIF_run_slice( nanosecs );
110 /********************** SH4 emulation core ****************************/
112 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
113 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
115 #if(SH4_CALLTRACE == 1)
116 #define MAX_CALLSTACK 32
117 static struct call_stack {
119 sh4addr_t target_addr;
120 sh4addr_t stack_pointer;
121 } call_stack[MAX_CALLSTACK];
123 static int call_stack_depth = 0;
124 int sh4_call_trace_on = 0;
126 static inline void trace_call( sh4addr_t source, sh4addr_t dest )
128 if( call_stack_depth < MAX_CALLSTACK ) {
129 call_stack[call_stack_depth].call_addr = source;
130 call_stack[call_stack_depth].target_addr = dest;
131 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
136 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
138 if( call_stack_depth > 0 ) {
143 void fprint_stack_trace( FILE *f )
145 int i = call_stack_depth -1;
146 if( i >= MAX_CALLSTACK )
147 i = MAX_CALLSTACK - 1;
148 for( ; i >= 0; i-- ) {
149 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
150 (call_stack_depth - i), call_stack[i].call_addr,
151 call_stack[i].target_addr, call_stack[i].stack_pointer );
155 #define TRACE_CALL( source, dest ) trace_call(source, dest)
156 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
158 #define TRACE_CALL( dest, rts )
159 #define TRACE_RETURN( source, dest )
162 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
163 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
164 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
165 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
166 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
167 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
169 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
171 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
172 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
174 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
175 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
176 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
177 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
178 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
180 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
181 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
182 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
184 static void sh4_write_float( uint32_t addr, int reg )
186 if( IS_FPU_DOUBLESIZE() ) {
188 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
189 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
191 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
192 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
195 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
199 static void sh4_read_float( uint32_t addr, int reg )
201 if( IS_FPU_DOUBLESIZE() ) {
203 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
204 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
206 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
207 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
210 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
214 gboolean sh4_execute_instruction( void )
221 int64_t memtmp; // temporary holder for memory reads
225 if( pc > 0xFFFFFF00 ) {
227 syscall_invoke( pc );
228 sh4r.in_delay_slot = 0;
229 pc = sh4r.pc = sh4r.pr;
230 sh4r.new_pc = sh4r.pc + 2;
234 /* Read instruction */
235 if( !IS_IN_ICACHE(pc) ) {
236 if( !mmu_update_icache(pc) ) {
237 // Fault - look for the fault handler
238 if( !mmu_update_icache(sh4r.pc) ) {
239 // double fault - halt
240 ERROR( "Double fault - halting" );
247 assert( IS_IN_ICACHE(pc) );
248 ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
250 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
251 AND #imm, R0 {: R0 &= imm; :}
252 AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
253 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
254 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
255 OR #imm, R0 {: R0 |= imm; :}
256 OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
258 MEM_READ_BYTE( sh4r.r[Rn], tmp );
259 sh4r.t = ( tmp == 0 ? 1 : 0 );
260 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
262 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
263 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
264 TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
265 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
266 XOR #imm, R0 {: R0 ^= imm; :}
267 XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
268 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
271 sh4r.t = sh4r.r[Rn] >> 31;
273 sh4r.r[Rn] |= sh4r.t;
276 sh4r.t = sh4r.r[Rn] & 0x00000001;
278 sh4r.r[Rn] |= (sh4r.t << 31);
281 tmp = sh4r.r[Rn] >> 31;
283 sh4r.r[Rn] |= sh4r.t;
287 tmp = sh4r.r[Rn] & 0x00000001;
289 sh4r.r[Rn] |= (sh4r.t << 31 );
294 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
295 else if( (tmp & 0x1F) == 0 )
296 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
298 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
302 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
303 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
304 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
307 sh4r.t = sh4r.r[Rn] >> 31;
311 sh4r.t = sh4r.r[Rn] & 0x00000001;
312 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
314 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
315 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
316 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
317 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
318 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
319 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
320 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
321 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
323 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
324 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
325 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
326 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
327 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
328 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
330 CLRT {: sh4r.t = 0; :}
331 SETT {: sh4r.t = 1; :}
332 CLRMAC {: sh4r.mac = 0; :}
333 LDTLB {: MMU_ldtlb(); :}
334 CLRS {: sh4r.s = 0; :}
335 SETS {: sh4r.s = 1; :}
336 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
341 if( (tmp & 0xFC000000) == 0xE0000000 ) {
342 sh4_flush_store_queue(tmp);
351 MEM_WRITE_LONG( tmp, R0 );
353 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
354 MOV.W Rm, @(R0, Rn) {:
355 CHECKWALIGN16( R0 + sh4r.r[Rn] );
356 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
358 MOV.L Rm, @(R0, Rn) {:
359 CHECKWALIGN32( R0 + sh4r.r[Rn] );
360 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
362 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
363 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
364 MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
366 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
367 MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
369 MOV.L Rm, @(disp, Rn) {:
370 tmp = sh4r.r[Rn] + disp;
371 CHECKWALIGN32( tmp );
372 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
374 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
375 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
376 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
377 MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
378 MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
379 MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
380 MOV.L @(disp, Rm), Rn {:
381 tmp = sh4r.r[Rm] + disp;
382 CHECKRALIGN32( tmp );
383 MEM_READ_LONG( tmp, sh4r.r[Rn] );
385 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
386 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
387 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
388 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
389 MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
390 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
391 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
392 MOV.L @(disp, PC), Rn {:
394 tmp = (pc&0xFFFFFFFC) + disp + 4;
395 MEM_READ_LONG( tmp, sh4r.r[Rn] );
397 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
398 MOV.W R0, @(disp, GBR) {:
399 tmp = sh4r.gbr + disp;
400 CHECKWALIGN16( tmp );
401 MEM_WRITE_WORD( tmp, R0 );
403 MOV.L R0, @(disp, GBR) {:
404 tmp = sh4r.gbr + disp;
405 CHECKWALIGN32( tmp );
406 MEM_WRITE_LONG( tmp, R0 );
408 MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
409 MOV.W @(disp, GBR), R0 {:
410 tmp = sh4r.gbr + disp;
411 CHECKRALIGN16( tmp );
412 MEM_READ_WORD( tmp, R0 );
414 MOV.L @(disp, GBR), R0 {:
415 tmp = sh4r.gbr + disp;
416 CHECKRALIGN32( tmp );
417 MEM_READ_LONG( tmp, R0 );
419 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
420 MOV.W R0, @(disp, Rn) {:
421 tmp = sh4r.r[Rn] + disp;
422 CHECKWALIGN16( tmp );
423 MEM_WRITE_WORD( tmp, R0 );
425 MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
426 MOV.W @(disp, Rm), R0 {:
427 tmp = sh4r.r[Rm] + disp;
428 CHECKRALIGN16( tmp );
429 MEM_READ_WORD( tmp, R0 );
431 MOV.W @(disp, PC), Rn {:
434 MEM_READ_WORD( tmp, sh4r.r[Rn] );
436 MOVA @(disp, PC), R0 {:
438 R0 = (pc&0xFFFFFFFC) + disp + 4;
440 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
442 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
443 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
444 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
445 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
446 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
447 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
448 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
449 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
451 /* set T = 1 if any byte in RM & RN is the same */
452 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
453 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
454 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
457 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
458 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
461 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
462 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
465 tmp = sh4r.r[Rn] + sh4r.r[Rm];
466 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
469 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
471 sh4r.q = sh4r.r[Rn]>>31;
472 sh4r.m = sh4r.r[Rm]>>31;
473 sh4r.t = sh4r.q ^ sh4r.m;
476 /* This is derived from the sh4 manual with some simplifications */
477 uint32_t tmp0, tmp1, tmp2, dir;
479 dir = sh4r.q ^ sh4r.m;
480 sh4r.q = (sh4r.r[Rn] >> 31);
482 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
486 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
489 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
491 sh4r.q ^= sh4r.m ^ tmp1;
492 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
494 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
495 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
498 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
503 CHECKRALIGN16(sh4r.r[Rn]);
504 MEM_READ_WORD( sh4r.r[Rn], tmp );
505 stmp = SIGNEXT16(tmp);
506 MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
507 stmp *= SIGNEXT16(tmp);
510 CHECKRALIGN16( sh4r.r[Rn] );
511 CHECKRALIGN16( sh4r.r[Rm] );
512 MEM_READ_WORD(sh4r.r[Rn], tmp);
513 stmp = SIGNEXT16(tmp);
514 MEM_READ_WORD(sh4r.r[Rm], tmp);
515 stmp = stmp * SIGNEXT16(tmp);
520 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
521 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
522 sh4r.mac = 0x000000017FFFFFFFLL;
523 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
524 sh4r.mac = 0x0000000180000000LL;
526 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
527 ((uint32_t)(sh4r.mac + stmp));
530 sh4r.mac += SIGNEXT32(stmp);
536 CHECKRALIGN32( sh4r.r[Rn] );
537 MEM_READ_LONG(sh4r.r[Rn], tmp);
538 tmpl = SIGNEXT32(tmp);
539 MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
540 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
543 CHECKRALIGN32( sh4r.r[Rm] );
544 CHECKRALIGN32( sh4r.r[Rn] );
545 MEM_READ_LONG(sh4r.r[Rn], tmp);
546 tmpl = SIGNEXT32(tmp);
547 MEM_READ_LONG(sh4r.r[Rm], tmp);
548 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
553 /* 48-bit Saturation. Yuch */
554 if( tmpl < (int64_t)0xFFFF800000000000LL )
555 tmpl = 0xFFFF800000000000LL;
556 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
557 tmpl = 0x00007FFFFFFFFFFFLL;
561 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
562 (sh4r.r[Rm] * sh4r.r[Rn]); :}
564 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
565 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
568 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
569 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
572 tmp = 0 - sh4r.r[Rm];
573 sh4r.r[Rn] = tmp - sh4r.t;
574 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
576 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
577 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
580 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
581 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
586 CHECKDEST( pc + 4 + sh4r.r[Rn] );
587 sh4r.in_delay_slot = 1;
588 sh4r.pc = sh4r.new_pc;
589 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
594 CHECKDEST( pc + 4 + sh4r.r[Rn] );
595 sh4r.in_delay_slot = 1;
596 sh4r.pr = sh4r.pc + 4;
597 sh4r.pc = sh4r.new_pc;
598 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
599 TRACE_CALL( pc, sh4r.new_pc );
605 CHECKDEST( sh4r.pc + disp + 4 )
607 sh4r.new_pc = sh4r.pc + 2;
614 CHECKDEST( sh4r.pc + disp + 4 )
616 sh4r.new_pc = sh4r.pc + 2;
623 CHECKDEST( sh4r.pc + disp + 4 )
624 sh4r.in_delay_slot = 1;
625 sh4r.pc = sh4r.new_pc;
626 sh4r.new_pc = pc + disp + 4;
627 sh4r.in_delay_slot = 1;
634 CHECKDEST( sh4r.pc + disp + 4 )
635 sh4r.in_delay_slot = 1;
636 sh4r.pc = sh4r.new_pc;
637 sh4r.new_pc = pc + disp + 4;
643 CHECKDEST( sh4r.pc + disp + 4 );
644 sh4r.in_delay_slot = 1;
645 sh4r.pc = sh4r.new_pc;
646 sh4r.new_pc = pc + 4 + disp;
650 CHECKDEST( sh4r.pc + disp + 4 );
652 sh4r.in_delay_slot = 1;
654 sh4r.pc = sh4r.new_pc;
655 sh4r.new_pc = pc + 4 + disp;
656 TRACE_CALL( pc, sh4r.new_pc );
662 sh4_raise_trap( imm );
667 CHECKDEST( sh4r.pr );
668 sh4r.in_delay_slot = 1;
669 sh4r.pc = sh4r.new_pc;
670 sh4r.new_pc = sh4r.pr;
671 TRACE_RETURN( pc, sh4r.new_pc );
675 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
676 sh4r.sh4_state = SH4_STATE_STANDBY;
678 sh4r.sh4_state = SH4_STATE_SLEEP;
680 return FALSE; /* Halt CPU */
684 CHECKDEST( sh4r.spc );
686 sh4r.in_delay_slot = 1;
687 sh4r.pc = sh4r.new_pc;
688 sh4r.new_pc = sh4r.spc;
689 sh4_write_sr( sh4r.ssr );
693 CHECKDEST( sh4r.r[Rn] );
695 sh4r.in_delay_slot = 1;
696 sh4r.pc = sh4r.new_pc;
697 sh4r.new_pc = sh4r.r[Rn];
701 CHECKDEST( sh4r.r[Rn] );
703 sh4r.in_delay_slot = 1;
704 sh4r.pc = sh4r.new_pc;
705 sh4r.new_pc = sh4r.r[Rn];
707 TRACE_CALL( pc, sh4r.new_pc );
710 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
712 CHECKWALIGN32( sh4r.r[Rn] );
713 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
718 CHECKWALIGN32( sh4r.r[Rn] );
719 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
723 CHECKRALIGN32( sh4r.r[Rm] );
724 MEM_READ_LONG(sh4r.r[Rm], tmp);
725 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
726 (((uint64_t)tmp)<<32);
732 CHECKWALIGN32( sh4r.r[Rm] );
733 MEM_READ_LONG(sh4r.r[Rm], tmp);
738 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
739 (((uint64_t)sh4r.r[Rm])<<32);
744 sh4_write_sr( sh4r.r[Rm] );
748 sh4r.sgr = sh4r.r[Rm];
752 CHECKRALIGN32( sh4r.r[Rm] );
753 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
756 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
758 CHECKWALIGN32( sh4r.r[Rn] );
759 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
763 CHECKWALIGN32( sh4r.r[Rn] );
764 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
768 CHECKRALIGN32( sh4r.r[Rm] );
769 MEM_READ_LONG(sh4r.r[Rm], tmp);
770 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
771 (uint64_t)((uint32_t)tmp);
775 CHECKRALIGN32( sh4r.r[Rm] );
776 MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
780 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
781 (uint64_t)((uint32_t)(sh4r.r[Rm]));
783 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
784 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
786 CHECKWALIGN32( sh4r.r[Rn] );
787 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
792 CHECKWALIGN32( sh4r.r[Rn] );
793 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
797 CHECKRALIGN32( sh4r.r[Rm] );
798 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
803 CHECKRALIGN32( sh4r.r[Rm] );
804 MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
807 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
810 sh4r.vbr = sh4r.r[Rm];
814 sh4r.r[Rn] = sh4r.sgr;
818 CHECKWALIGN32( sh4r.r[Rn] );
819 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
824 CHECKWALIGN32( sh4r.r[Rn] );
825 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
830 CHECKRALIGN32( sh4r.r[Rm] );
831 MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
836 sh4r.ssr = sh4r.r[Rm];
840 CHECKWALIGN32( sh4r.r[Rn] );
841 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
846 CHECKRALIGN32( sh4r.r[Rm] );
847 MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
852 sh4r.spc = sh4r.r[Rm];
854 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
856 CHECKWALIGN32( sh4r.r[Rn] );
857 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
861 CHECKRALIGN32( sh4r.r[Rm] );
862 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
865 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
866 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
868 CHECKWALIGN32( sh4r.r[Rn] );
869 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
873 CHECKRALIGN32( sh4r.r[Rm] );
874 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
876 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
879 sh4r.fpscr = sh4r.r[Rm];
880 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
882 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
885 CHECKWALIGN32( sh4r.r[Rn] );
886 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
891 CHECKRALIGN32( sh4r.r[Rm] );
892 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
897 sh4r.dbr = sh4r.r[Rm];
899 STC.L Rm_BANK, @-Rn {:
901 CHECKWALIGN32( sh4r.r[Rn] );
902 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
905 LDC.L @Rm+, Rn_BANK {:
907 CHECKRALIGN32( sh4r.r[Rm] );
908 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
913 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
917 sh4r.r[Rn] = sh4_read_sr();
921 sh4r.r[Rn] = sh4r.gbr;
925 sh4r.r[Rn] = sh4r.vbr;
929 sh4r.r[Rn] = sh4r.ssr;
933 sh4r.r[Rn] = sh4r.spc;
937 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
942 if( IS_FPU_DOUBLEPREC() ) {
950 if( IS_FPU_DOUBLEPREC() ) {
959 if( IS_FPU_DOUBLEPREC() ) {
968 if( IS_FPU_DOUBLEPREC() ) {
977 if( IS_FPU_DOUBLEPREC() ) {
978 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
980 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
986 if( IS_FPU_DOUBLEPREC() ) {
987 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
989 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
993 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
994 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
995 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
996 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
997 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
998 FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
1000 if( IS_FPU_DOUBLESIZE() )
1005 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
1006 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
1009 if( IS_FPU_DOUBLEPREC() ) {
1010 if( FRn&1 ) { // No, really...
1011 dtmp = (double)FPULi;
1012 FR(FRn) = *(((float *)&dtmp)+1);
1014 DRF(FRn>>1) = (double)FPULi;
1017 FR(FRn) = (float)FPULi;
1022 if( IS_FPU_DOUBLEPREC() ) {
1025 *(((float *)&dtmp)+1) = FR(FRm);
1029 if( dtmp >= MAX_INTF )
1031 else if( dtmp <= MIN_INTF )
1034 FPULi = (int32_t)dtmp;
1037 if( ftmp >= MAX_INTF )
1039 else if( ftmp <= MIN_INTF )
1042 FPULi = (int32_t)ftmp;
1047 if( IS_FPU_DOUBLEPREC() ) {
1055 if( IS_FPU_DOUBLEPREC() ) {
1056 DR(FRn) = fabs(DR(FRn));
1058 FR(FRn) = fabsf(FR(FRn));
1063 if( IS_FPU_DOUBLEPREC() ) {
1064 DR(FRn) = sqrt(DR(FRn));
1066 FR(FRn) = sqrtf(FR(FRn));
1071 if( IS_FPU_DOUBLEPREC() ) {
1079 if( IS_FPU_DOUBLEPREC() ) {
1085 FMAC FR0, FRm, FRn {:
1087 if( IS_FPU_DOUBLEPREC() ) {
1088 DR(FRn) += DR(FRm)*DR(0);
1090 FR(FRn) += FR(FRm)*FR(0);
1095 sh4r.fpscr ^= FPSCR_FR;
1096 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1098 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1101 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1102 DR(FRn) = (double)FPULf;
1107 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1108 FPULf = (float)DR(FRm);
1114 if( !IS_FPU_DOUBLEPREC() ) {
1115 FR(FRn) = 1.0/sqrtf(FR(FRn));
1120 if( !IS_FPU_DOUBLEPREC() ) {
1123 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1124 FR(tmp+1)*FR(tmp2+1) +
1125 FR(tmp+2)*FR(tmp2+2) +
1126 FR(tmp+3)*FR(tmp2+3);
1131 if( !IS_FPU_DOUBLEPREC() ) {
1132 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
1134 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1135 FR(FRn) = sinf(angle);
1136 FR((FRn)+1) = cosf(angle);
1142 if( !IS_FPU_DOUBLEPREC() ) {
1143 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
1146 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
1147 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1148 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
1149 xf[9]*fv[2] + xf[13]*fv[3];
1150 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
1151 xf[8]*fv[2] + xf[12]*fv[3];
1152 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
1153 xf[11]*fv[2] + xf[15]*fv[3];
1154 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
1155 xf[10]*fv[2] + xf[14]*fv[3];
1163 sh4r.pc = sh4r.new_pc;
1165 sh4r.in_delay_slot = 0;
.