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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 273:48eb3304a41e
prev265:5daf59b7f31b
next302:96b5cc24309c
author nkeynes
date Thu Jan 11 12:14:11 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Always return TRUE at end of execute instruction (oops)
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     1 /**
     2  * $Id: sh4core.c,v 1.38 2007-01-11 12:14:11 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 /* CPU-generated exception code/vector pairs */
    38 #define EXC_POWER_RESET  0x000 /* vector special */
    39 #define EXC_MANUAL_RESET 0x020
    40 #define EXC_READ_ADDR_ERR 0x0E0
    41 #define EXC_WRITE_ADDR_ERR 0x100
    42 #define EXC_SLOT_ILLEGAL 0x1A0
    43 #define EXC_ILLEGAL      0x180
    44 #define EXC_TRAP         0x160
    45 #define EXC_FPDISABLE    0x800
    46 #define EXC_SLOT_FPDISABLE 0x820
    48 #define EXV_EXCEPTION    0x100  /* General exception vector */
    49 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    50 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    52 /********************** SH4 Module Definition ****************************/
    54 void sh4_init( void );
    55 void sh4_reset( void );
    56 uint32_t sh4_run_slice( uint32_t );
    57 void sh4_start( void );
    58 void sh4_stop( void );
    59 void sh4_save_state( FILE *f );
    60 int sh4_load_state( FILE *f );
    61 static void sh4_accept_interrupt( void );
    63 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    64 				       NULL, sh4_run_slice, sh4_stop,
    65 				       sh4_save_state, sh4_load_state };
    67 struct sh4_registers sh4r;
    69 void sh4_init(void)
    70 {
    71     register_io_regions( mmio_list_sh4mmio );
    72     mmu_init();
    73     sh4_reset();
    74 }
    76 void sh4_reset(void)
    77 {
    78     /* zero everything out, for the sake of having a consistent state. */
    79     memset( &sh4r, 0, sizeof(sh4r) );
    81     /* Resume running if we were halted */
    82     sh4r.sh4_state = SH4_STATE_RUNNING;
    84     sh4r.pc    = 0xA0000000;
    85     sh4r.new_pc= 0xA0000002;
    86     sh4r.vbr   = 0x00000000;
    87     sh4r.fpscr = 0x00040001;
    88     sh4r.sr    = 0x700000F0;
    90     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    91     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    93     /* Peripheral modules */
    94     CPG_reset();
    95     INTC_reset();
    96     TMU_reset();
    97     SCIF_reset();
    98 }
   100 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
   101 static int sh4_breakpoint_count = 0;
   102 static uint16_t *sh4_icache = NULL;
   103 static uint32_t sh4_icache_addr = 0;
   105 void sh4_set_breakpoint( uint32_t pc, int type )
   106 {
   107     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   108     sh4_breakpoints[sh4_breakpoint_count].type = type;
   109     sh4_breakpoint_count++;
   110 }
   112 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   113 {
   114     int i;
   116     for( i=0; i<sh4_breakpoint_count; i++ ) {
   117 	if( sh4_breakpoints[i].address == pc && 
   118 	    sh4_breakpoints[i].type == type ) {
   119 	    while( ++i < sh4_breakpoint_count ) {
   120 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   121 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   122 	    }
   123 	    sh4_breakpoint_count--;
   124 	    return TRUE;
   125 	}
   126     }
   127     return FALSE;
   128 }
   130 int sh4_get_breakpoint( uint32_t pc )
   131 {
   132     int i;
   133     for( i=0; i<sh4_breakpoint_count; i++ ) {
   134 	if( sh4_breakpoints[i].address == pc )
   135 	    return sh4_breakpoints[i].type;
   136     }
   137     return 0;
   138 }
   140 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   141 {
   142     int i;
   143     sh4r.slice_cycle = 0;
   145     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   146 	if( sh4r.event_pending < nanosecs ) {
   147 	    sh4r.sh4_state = SH4_STATE_RUNNING;
   148 	    sh4r.slice_cycle = sh4r.event_pending;
   149 	}
   150     }
   152     if( sh4_breakpoint_count == 0 ) {
   153 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   154 	    if( SH4_EVENT_PENDING() ) {
   155 		if( sh4r.event_types & PENDING_EVENT ) {
   156 		    event_execute();
   157 		}
   158 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   159 		if( sh4r.event_types & PENDING_IRQ ) {
   160 		    sh4_accept_interrupt();
   161 		}
   162 	    }
   163 	    if( !sh4_execute_instruction() ) {
   164 		break;
   165 	    }
   166 	}
   167     } else {
   168 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   169 	    if( SH4_EVENT_PENDING() ) {
   170 		if( sh4r.event_types & PENDING_EVENT ) {
   171 		    event_execute();
   172 		}
   173 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   174 		if( sh4r.event_types & PENDING_IRQ ) {
   175 		    sh4_accept_interrupt();
   176 		}
   177 	    }
   179 	    if( !sh4_execute_instruction() )
   180 		break;
   181 #ifdef ENABLE_DEBUG_MODE
   182 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
   183 		if( sh4_breakpoints[i].address == sh4r.pc ) {
   184 		    break;
   185 		}
   186 	    }
   187 	    if( i != sh4_breakpoint_count ) {
   188 		dreamcast_stop();
   189 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   190 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   191 		break;
   192 	    }
   193 #endif	
   194 	}
   195     }
   197     /* If we aborted early, but the cpu is still technically running,
   198      * we're doing a hard abort - cut the timeslice back to what we
   199      * actually executed
   200      */
   201     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   202 	nanosecs = sh4r.slice_cycle;
   203     }
   204     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   205 	TMU_run_slice( nanosecs );
   206 	SCIF_run_slice( nanosecs );
   207     }
   208     sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
   209     return nanosecs;
   210 }
   212 void sh4_stop(void)
   213 {
   215 }
   217 void sh4_save_state( FILE *f )
   218 {
   219     fwrite( &sh4r, sizeof(sh4r), 1, f );
   220     INTC_save_state( f );
   221     TMU_save_state( f );
   222     SCIF_save_state( f );
   223 }
   225 int sh4_load_state( FILE * f )
   226 {
   227     fread( &sh4r, sizeof(sh4r), 1, f );
   228     INTC_load_state( f );
   229     TMU_load_state( f );
   230     return SCIF_load_state( f );
   231 }
   233 /********************** SH4 emulation core  ****************************/
   235 void sh4_set_pc( int pc )
   236 {
   237     sh4r.pc = pc;
   238     sh4r.new_pc = pc+2;
   239 }
   241 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   242 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   244 #if(SH4_CALLTRACE == 1)
   245 #define MAX_CALLSTACK 32
   246 static struct call_stack {
   247     sh4addr_t call_addr;
   248     sh4addr_t target_addr;
   249     sh4addr_t stack_pointer;
   250 } call_stack[MAX_CALLSTACK];
   252 static int call_stack_depth = 0;
   253 int sh4_call_trace_on = 0;
   255 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   256 {
   257     if( call_stack_depth < MAX_CALLSTACK ) {
   258 	call_stack[call_stack_depth].call_addr = source;
   259 	call_stack[call_stack_depth].target_addr = dest;
   260 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   261     }
   262     call_stack_depth++;
   263 }
   265 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   266 {
   267     if( call_stack_depth > 0 ) {
   268 	call_stack_depth--;
   269     }
   270 }
   272 void fprint_stack_trace( FILE *f )
   273 {
   274     int i = call_stack_depth -1;
   275     if( i >= MAX_CALLSTACK )
   276 	i = MAX_CALLSTACK - 1;
   277     for( ; i >= 0; i-- ) {
   278 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   279 		 (call_stack_depth - i), call_stack[i].call_addr,
   280 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   281     }
   282 }
   284 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   285 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   286 #else
   287 #define TRACE_CALL( dest, rts ) 
   288 #define TRACE_RETURN( source, dest )
   289 #endif
   291 #define RAISE( x, v ) do{			\
   292     if( sh4r.vbr == 0 ) { \
   293         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   294         dreamcast_stop(); return FALSE;	\
   295     } else { \
   296         sh4r.spc = sh4r.pc;	\
   297         sh4r.ssr = sh4_read_sr(); \
   298         sh4r.sgr = sh4r.r[15]; \
   299         MMIO_WRITE(MMU,EXPEVT,x); \
   300         sh4r.pc = sh4r.vbr + v; \
   301         sh4r.new_pc = sh4r.pc + 2; \
   302         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   303 	if( sh4r.in_delay_slot ) { \
   304 	    sh4r.in_delay_slot = 0; \
   305 	    sh4r.spc -= 2; \
   306 	} \
   307     } \
   308     return TRUE; } while(0)
   310 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   311 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   312 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   313 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   314 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   315 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   317 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   319 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   320 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   322 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   323 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
   324 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_READ_ADDR_ERR )
   325 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
   326 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR )
   328 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE )
   329 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   330 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   332 static void sh4_switch_banks( )
   333 {
   334     uint32_t tmp[8];
   336     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   337     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   338     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   339 }
   341 static void sh4_load_sr( uint32_t newval )
   342 {
   343     if( (newval ^ sh4r.sr) & SR_RB )
   344         sh4_switch_banks();
   345     sh4r.sr = newval;
   346     sh4r.t = (newval&SR_T) ? 1 : 0;
   347     sh4r.s = (newval&SR_S) ? 1 : 0;
   348     sh4r.m = (newval&SR_M) ? 1 : 0;
   349     sh4r.q = (newval&SR_Q) ? 1 : 0;
   350     intc_mask_changed();
   351 }
   353 static void sh4_write_float( uint32_t addr, int reg )
   354 {
   355     if( IS_FPU_DOUBLESIZE() ) {
   356 	if( reg & 1 ) {
   357 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   358 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   359 	} else {
   360 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   361 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   362 	}
   363     } else {
   364 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   365     }
   366 }
   368 static void sh4_read_float( uint32_t addr, int reg )
   369 {
   370     if( IS_FPU_DOUBLESIZE() ) {
   371 	if( reg & 1 ) {
   372 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   373 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   374 	} else {
   375 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   376 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   377 	}
   378     } else {
   379 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   380     }
   381 }
   383 static uint32_t sh4_read_sr( void )
   384 {
   385     /* synchronize sh4r.sr with the various bitflags */
   386     sh4r.sr &= SR_MQSTMASK;
   387     if( sh4r.t ) sh4r.sr |= SR_T;
   388     if( sh4r.s ) sh4r.sr |= SR_S;
   389     if( sh4r.m ) sh4r.sr |= SR_M;
   390     if( sh4r.q ) sh4r.sr |= SR_Q;
   391     return sh4r.sr;
   392 }
   394 /**
   395  * Raise a general CPU exception for the specified exception code.
   396  * (NOT for TRAPA or TLB exceptions)
   397  */
   398 gboolean sh4_raise_exception( int code )
   399 {
   400     RAISE( code, EXV_EXCEPTION );
   401 }
   403 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   404     if( sh4r.in_delay_slot ) {
   405 	return sh4_raise_exception(slot_code);
   406     } else {
   407 	return sh4_raise_exception(normal_code);
   408     }
   409 }
   411 gboolean sh4_raise_tlb_exception( int code )
   412 {
   413     RAISE( code, EXV_TLBMISS );
   414 }
   416 static void sh4_accept_interrupt( void )
   417 {
   418     uint32_t code = intc_accept_interrupt();
   419     sh4r.ssr = sh4_read_sr();
   420     sh4r.spc = sh4r.pc;
   421     sh4r.sgr = sh4r.r[15];
   422     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   423     MMIO_WRITE( MMU, INTEVT, code );
   424     sh4r.pc = sh4r.vbr + 0x600;
   425     sh4r.new_pc = sh4r.pc + 2;
   426     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   427 }
   429 gboolean sh4_execute_instruction( void )
   430 {
   431     uint32_t pc;
   432     unsigned short ir;
   433     uint32_t tmp;
   434     uint64_t tmpl;
   435     float ftmp;
   436     double dtmp;
   438 #define R0 sh4r.r[0]
   439 #define FR0 FR(0)
   440 #define DR0 DR(0)
   441 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   442 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   443 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   444 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   445 #define DISP8(ir) (ir&0x00FF)
   446 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   447 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   448 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   449 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   450 #define FRNn(ir) ((ir&0x0F00)>>8)
   451 #define FRMn(ir) ((ir&0x00F0)>>4)
   452 #define DRNn(ir) ((ir&0x0E00)>>9)
   453 #define DRMn(ir) ((ir&0x00E0)>>5)
   454 #define FVN(ir) ((ir&0x0C00)>>8)
   455 #define FVM(ir) ((ir&0x0300)>>6)
   456 #define FRN(ir) FR(FRNn(ir))
   457 #define FRM(ir) FR(FRMn(ir))
   458 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
   459 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
   460 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
   461 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
   462 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
   463 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
   464 #define FPULf   *((float *)&sh4r.fpul)
   465 #define FPULi    (sh4r.fpul)
   467     pc = sh4r.pc;
   468     if( pc > 0xFFFFFF00 ) {
   469 	/* SYSCALL Magic */
   470 	syscall_invoke( pc );
   471 	sh4r.in_delay_slot = 0;
   472 	pc = sh4r.pc = sh4r.pr;
   473 	sh4r.new_pc = sh4r.pc + 2;
   474     }
   475     CHECKRALIGN16(pc);
   477     /* Read instruction */
   478     uint32_t pageaddr = pc >> 12;
   479     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   480 	ir = sh4_icache[(pc&0xFFF)>>1];
   481     } else {
   482 	sh4_icache = (uint16_t *)mem_get_page(pc);
   483 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   484 	    /* If someone's actually been so daft as to try to execute out of an IO
   485 	     * region, fallback on the full-blown memory read
   486 	     */
   487 	    sh4_icache = NULL;
   488 	    ir = MEM_READ_WORD(pc);
   489 	} else {
   490 	    sh4_icache_addr = pageaddr;
   491 	    ir = sh4_icache[(pc&0xFFF)>>1];
   492 	}
   493     }
   494     sh4r.icount++;
   496     switch( (ir&0xF000)>>12 ) {
   497         case 0: /* 0000nnnnmmmmxxxx */
   498             switch( ir&0x000F ) {
   499                 case 2:
   500                     switch( (ir&0x00F0)>>4 ) {
   501                         case 0: /* STC     SR, Rn */
   502                             CHECKPRIV();
   503                             RN(ir) = sh4_read_sr();
   504                             break;
   505                         case 1: /* STC     GBR, Rn */
   506                             RN(ir) = sh4r.gbr;
   507                             break;
   508                         case 2: /* STC     VBR, Rn */
   509                             CHECKPRIV();
   510                             RN(ir) = sh4r.vbr;
   511                             break;
   512                         case 3: /* STC     SSR, Rn */
   513                             CHECKPRIV();
   514                             RN(ir) = sh4r.ssr;
   515                             break;
   516                         case 4: /* STC     SPC, Rn */
   517                             CHECKPRIV();
   518                             RN(ir) = sh4r.spc;
   519                             break;
   520                         case 8: case 9: case 10: case 11: case 12: case 13:
   521                         case 14: case 15:/* STC     Rm_bank, Rn */
   522                             CHECKPRIV();
   523                             RN(ir) = RN_BANK(ir);
   524                             break;
   525                         default: UNDEF(ir);
   526                     }
   527                     break;
   528                 case 3:
   529                     switch( (ir&0x00F0)>>4 ) {
   530                         case 0: /* BSRF    Rn */
   531                             CHECKSLOTILLEGAL();
   532                             CHECKDEST( pc + 4 + RN(ir) );
   533                             sh4r.in_delay_slot = 1;
   534                             sh4r.pr = sh4r.pc + 4;
   535                             sh4r.pc = sh4r.new_pc;
   536                             sh4r.new_pc = pc + 4 + RN(ir);
   537 			    TRACE_CALL( pc, sh4r.new_pc );
   538                             return TRUE;
   539                         case 2: /* BRAF    Rn */
   540                             CHECKSLOTILLEGAL();
   541                             CHECKDEST( pc + 4 + RN(ir) );
   542                             sh4r.in_delay_slot = 1;
   543                             sh4r.pc = sh4r.new_pc;
   544                             sh4r.new_pc = pc + 4 + RN(ir);
   545                             return TRUE;
   546                         case 8: /* PREF    [Rn] */
   547                             tmp = RN(ir);
   548                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   549                                 /* Store queue operation */
   550                                 int queue = (tmp&0x20)>>2;
   551                                 int32_t *src = &sh4r.store_queue[queue];
   552                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   553                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   554                                 mem_copy_to_sh4( target, src, 32 );
   555                             }
   556                             break;
   557                         case 9: /* OCBI    [Rn] */
   558                         case 10:/* OCBP    [Rn] */
   559                         case 11:/* OCBWB   [Rn] */
   560                             /* anything? */
   561                             break;
   562                         case 12:/* MOVCA.L R0, [Rn] */
   563 			    tmp = RN(ir);
   564 			    CHECKWALIGN32(tmp);
   565 			    MEM_WRITE_LONG( tmp, R0 );
   566 			    break;
   567                         default: UNDEF(ir);
   568                     }
   569                     break;
   570                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   571                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   572                     break;
   573                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   574 		    CHECKWALIGN16( R0 + RN(ir) );
   575                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   576                     break;
   577                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   578 		    CHECKWALIGN32( R0 + RN(ir) );
   579                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   580                     break;
   581                 case 7: /* MUL.L   Rm, Rn */
   582                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   583                         (RM(ir) * RN(ir));
   584                     break;
   585                 case 8: 
   586                     switch( (ir&0x0FF0)>>4 ) {
   587                         case 0: /* CLRT    */
   588                             sh4r.t = 0;
   589                             break;
   590                         case 1: /* SETT    */
   591                             sh4r.t = 1;
   592                             break;
   593                         case 2: /* CLRMAC  */
   594                             sh4r.mac = 0;
   595                             break;
   596                         case 3: /* LDTLB   */
   597                             break;
   598                         case 4: /* CLRS    */
   599                             sh4r.s = 0;
   600                             break;
   601                         case 5: /* SETS    */
   602                             sh4r.s = 1;
   603                             break;
   604                         default: UNDEF(ir);
   605                     }
   606                     break;
   607                 case 9: 
   608                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   609                         RN(ir) = sh4r.t;
   610                     else if( ir == 0x0019 ) /* DIV0U   */
   611                         sh4r.m = sh4r.q = sh4r.t = 0;
   612                     else if( ir == 0x0009 )
   613                         /* NOP     */;
   614                     else UNDEF(ir);
   615                     break;
   616                 case 10:
   617                     switch( (ir&0x00F0) >> 4 ) {
   618                         case 0: /* STS     MACH, Rn */
   619                             RN(ir) = sh4r.mac >> 32;
   620                             break;
   621                         case 1: /* STS     MACL, Rn */
   622                             RN(ir) = (uint32_t)sh4r.mac;
   623                             break;
   624                         case 2: /* STS     PR, Rn */
   625                             RN(ir) = sh4r.pr;
   626                             break;
   627                         case 3: /* STC     SGR, Rn */
   628                             CHECKPRIV();
   629                             RN(ir) = sh4r.sgr;
   630                             break;
   631                         case 5:/* STS      FPUL, Rn */
   632                             RN(ir) = sh4r.fpul;
   633                             break;
   634                         case 6: /* STS     FPSCR, Rn */
   635                             RN(ir) = sh4r.fpscr;
   636                             break;
   637                         case 15:/* STC     DBR, Rn */
   638                             CHECKPRIV();
   639                             RN(ir) = sh4r.dbr;
   640                             break;
   641                         default: UNDEF(ir);
   642                     }
   643                     break;
   644                 case 11:
   645                     switch( (ir&0x0FF0)>>4 ) {
   646                         case 0: /* RTS     */
   647                             CHECKSLOTILLEGAL();
   648                             CHECKDEST( sh4r.pr );
   649                             sh4r.in_delay_slot = 1;
   650                             sh4r.pc = sh4r.new_pc;
   651                             sh4r.new_pc = sh4r.pr;
   652                             TRACE_RETURN( pc, sh4r.new_pc );
   653                             return TRUE;
   654                         case 1: /* SLEEP   */
   655 			    if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   656 				sh4r.sh4_state = SH4_STATE_STANDBY;
   657 			    } else {
   658 				sh4r.sh4_state = SH4_STATE_SLEEP;
   659 			    }
   660 			    return FALSE; /* Halt CPU */
   661                         case 2: /* RTE     */
   662                             CHECKPRIV();
   663                             CHECKDEST( sh4r.spc );
   664                             CHECKSLOTILLEGAL();
   665                             sh4r.in_delay_slot = 1;
   666                             sh4r.pc = sh4r.new_pc;
   667                             sh4r.new_pc = sh4r.spc;
   668                             sh4_load_sr( sh4r.ssr );
   669                             return TRUE;
   670                         default:UNDEF(ir);
   671                     }
   672                     break;
   673                 case 12:/* MOV.B   [R0+R%d], R%d */
   674                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   675                     break;
   676                 case 13:/* MOV.W   [R0+R%d], R%d */
   677 		    CHECKRALIGN16( R0 + RM(ir) );
   678                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   679                     break;
   680                 case 14:/* MOV.L   [R0+R%d], R%d */
   681 		    CHECKRALIGN32( R0 + RM(ir) );
   682                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   683                     break;
   684                 case 15:/* MAC.L   [Rm++], [Rn++] */
   685 		    CHECKRALIGN32( RM(ir) );
   686 		    CHECKRALIGN32( RN(ir) );
   687                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   688                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   689                     if( sh4r.s ) {
   690                         /* 48-bit Saturation. Yuch */
   691                         tmpl += SIGNEXT48(sh4r.mac);
   692                         if( tmpl < 0xFFFF800000000000LL )
   693                             tmpl = 0xFFFF800000000000LL;
   694                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   695                             tmpl = 0x00007FFFFFFFFFFFLL;
   696                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   697                             (tmpl&0x0000FFFFFFFFFFFFLL);
   698                     } else sh4r.mac = tmpl;
   700                     RM(ir) += 4;
   701                     RN(ir) += 4;
   703                     break;
   704                 default: UNDEF(ir);
   705             }
   706             break;
   707         case 1: /* 0001nnnnmmmmdddd */
   708             /* MOV.L   Rm, [Rn + disp4*4] */
   709 	    tmp = RN(ir) + (DISP4(ir)<<2);
   710 	    CHECKWALIGN32( tmp );
   711             MEM_WRITE_LONG( tmp, RM(ir) );
   712             break;
   713         case 2: /* 0010nnnnmmmmxxxx */
   714             switch( ir&0x000F ) {
   715                 case 0: /* MOV.B   Rm, [Rn] */
   716                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   717                     break;
   718                 case 1: /* MOV.W   Rm, [Rn] */
   719                	    CHECKWALIGN16( RN(ir) );
   720 		    MEM_WRITE_WORD( RN(ir), RM(ir) );
   721                     break;
   722                 case 2: /* MOV.L   Rm, [Rn] */
   723 		    CHECKWALIGN32( RN(ir) );
   724                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   725                     break;
   726                 case 3: UNDEF(ir);
   727                     break;
   728                 case 4: /* MOV.B   Rm, [--Rn] */
   729                     RN(ir) --;
   730                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   731                     break;
   732                 case 5: /* MOV.W   Rm, [--Rn] */
   733                     RN(ir) -= 2;
   734 		    CHECKWALIGN16( RN(ir) );
   735                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   736                     break;
   737                 case 6: /* MOV.L   Rm, [--Rn] */
   738                     RN(ir) -= 4;
   739 		    CHECKWALIGN32( RN(ir) );
   740                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   741                     break;
   742                 case 7: /* DIV0S   Rm, Rn */
   743                     sh4r.q = RN(ir)>>31;
   744                     sh4r.m = RM(ir)>>31;
   745                     sh4r.t = sh4r.q ^ sh4r.m;
   746                     break;
   747                 case 8: /* TST     Rm, Rn */
   748                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   749                     break;
   750                 case 9: /* AND     Rm, Rn */
   751                     RN(ir) &= RM(ir);
   752                     break;
   753                 case 10:/* XOR     Rm, Rn */
   754                     RN(ir) ^= RM(ir);
   755                     break;
   756                 case 11:/* OR      Rm, Rn */
   757                     RN(ir) |= RM(ir);
   758                     break;
   759                 case 12:/* CMP/STR Rm, Rn */
   760                     /* set T = 1 if any byte in RM & RN is the same */
   761                     tmp = RM(ir) ^ RN(ir);
   762                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   763                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   764                     break;
   765                 case 13:/* XTRCT   Rm, Rn */
   766                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   767                     break;
   768                 case 14:/* MULU.W  Rm, Rn */
   769                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   770                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   771                     break;
   772                 case 15:/* MULS.W  Rm, Rn */
   773                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   774                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   775                     break;
   776             }
   777             break;
   778         case 3: /* 0011nnnnmmmmxxxx */
   779             switch( ir&0x000F ) {
   780                 case 0: /* CMP/EQ  Rm, Rn */
   781                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   782                     break;
   783                 case 2: /* CMP/HS  Rm, Rn */
   784                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   785                     break;
   786                 case 3: /* CMP/GE  Rm, Rn */
   787                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   788                     break;
   789                 case 4: { /* DIV1    Rm, Rn */
   790                     /* This is just from the sh4p manual with some
   791                      * simplifications (someone want to check it's correct? :)
   792                      * Why they couldn't just provide a real DIV instruction...
   793                      * Please oh please let the translator batch these things
   794                      * up into a single DIV... */
   795                     uint32_t tmp0, tmp1, tmp2, dir;
   797                     dir = sh4r.q ^ sh4r.m;
   798                     sh4r.q = (RN(ir) >> 31);
   799                     tmp2 = RM(ir);
   800                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   801                     tmp0 = RN(ir);
   802                     if( dir ) {
   803                         RN(ir) += tmp2;
   804                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   805                     } else {
   806                         RN(ir) -= tmp2;
   807                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   808                     }
   809                     sh4r.q ^= sh4r.m ^ tmp1;
   810                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   811                     break; }
   812                 case 5: /* DMULU.L Rm, Rn */
   813                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   814                     break;
   815                 case 6: /* CMP/HI  Rm, Rn */
   816                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   817                     break;
   818                 case 7: /* CMP/GT  Rm, Rn */
   819                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   820                     break;
   821                 case 8: /* SUB     Rm, Rn */
   822                     RN(ir) -= RM(ir);
   823                     break;
   824                 case 10:/* SUBC    Rm, Rn */
   825                     tmp = RN(ir);
   826                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   827                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   828                     break;
   829                 case 11:/* SUBV    Rm, Rn */
   830                     UNIMP(ir);
   831                     break;
   832                 case 12:/* ADD     Rm, Rn */
   833                     RN(ir) += RM(ir);
   834                     break;
   835                 case 13:/* DMULS.L Rm, Rn */
   836                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   837                     break;
   838                 case 14:/* ADDC    Rm, Rn */
   839                     tmp = RN(ir);
   840                     RN(ir) += RM(ir) + sh4r.t;
   841                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   842                     break;
   843                 case 15:/* ADDV    Rm, Rn */
   844 		    tmp = RN(ir) + RM(ir);
   845 		    sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
   846 		    RN(ir) = tmp;
   847                     break;
   848                 default: UNDEF(ir);
   849             }
   850             break;
   851         case 4: /* 0100nnnnxxxxxxxx */
   852             switch( ir&0x00FF ) {
   853                 case 0x00: /* SHLL    Rn */
   854                     sh4r.t = RN(ir) >> 31;
   855                     RN(ir) <<= 1;
   856                     break;
   857                 case 0x01: /* SHLR    Rn */
   858                     sh4r.t = RN(ir) & 0x00000001;
   859                     RN(ir) >>= 1;
   860                     break;
   861                 case 0x02: /* STS.L   MACH, [--Rn] */
   862                     RN(ir) -= 4;
   863 		    CHECKWALIGN32( RN(ir) );
   864                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   865                     break;
   866                 case 0x03: /* STC.L   SR, [--Rn] */
   867                     CHECKPRIV();
   868                     RN(ir) -= 4;
   869 		    CHECKWALIGN32( RN(ir) );
   870                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   871                     break;
   872                 case 0x04: /* ROTL    Rn */
   873                     sh4r.t = RN(ir) >> 31;
   874                     RN(ir) <<= 1;
   875                     RN(ir) |= sh4r.t;
   876                     break;
   877                 case 0x05: /* ROTR    Rn */
   878                     sh4r.t = RN(ir) & 0x00000001;
   879                     RN(ir) >>= 1;
   880                     RN(ir) |= (sh4r.t << 31);
   881                     break;
   882                 case 0x06: /* LDS.L   [Rn++], MACH */
   883 		    CHECKRALIGN32( RN(ir) );
   884                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   885                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   886                     RN(ir) += 4;
   887                     break;
   888                 case 0x07: /* LDC.L   [Rn++], SR */
   889 		    CHECKSLOTILLEGAL();
   890                     CHECKPRIV();
   891 		    CHECKWALIGN32( RN(ir) );
   892                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   893                     RN(ir) +=4;
   894                     break;
   895                 case 0x08: /* SHLL2   Rn */
   896                     RN(ir) <<= 2;
   897                     break;
   898                 case 0x09: /* SHLR2   Rn */
   899                     RN(ir) >>= 2;
   900                     break;
   901                 case 0x0A: /* LDS     Rn, MACH */
   902                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   903                         (((uint64_t)RN(ir))<<32);
   904                     break;
   905                 case 0x0B: /* JSR     [Rn] */
   906                     CHECKDEST( RN(ir) );
   907                     CHECKSLOTILLEGAL();
   908                     sh4r.in_delay_slot = 1;
   909                     sh4r.pc = sh4r.new_pc;
   910                     sh4r.new_pc = RN(ir);
   911                     sh4r.pr = pc + 4;
   912 		    TRACE_CALL( pc, sh4r.new_pc );
   913                     return TRUE;
   914                 case 0x0E: /* LDC     Rn, SR */
   915 		    CHECKSLOTILLEGAL();
   916                     CHECKPRIV();
   917                     sh4_load_sr( RN(ir) );
   918                     break;
   919                 case 0x10: /* DT      Rn */
   920                     RN(ir) --;
   921                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   922                     break;
   923                 case 0x11: /* CMP/PZ  Rn */
   924                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   925                     break;
   926                 case 0x12: /* STS.L   MACL, [--Rn] */
   927                     RN(ir) -= 4;
   928 		    CHECKWALIGN32( RN(ir) );
   929                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   930                     break;
   931                 case 0x13: /* STC.L   GBR, [--Rn] */
   932                     RN(ir) -= 4;
   933 		    CHECKWALIGN32( RN(ir) );
   934                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   935                     break;
   936                 case 0x15: /* CMP/PL  Rn */
   937                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   938                     break;
   939                 case 0x16: /* LDS.L   [Rn++], MACL */
   940 		    CHECKRALIGN32( RN(ir) );
   941                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   942                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   943                     RN(ir) += 4;
   944                     break;
   945                 case 0x17: /* LDC.L   [Rn++], GBR */
   946 		    CHECKRALIGN32( RN(ir) );
   947                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   948                     RN(ir) +=4;
   949                     break;
   950                 case 0x18: /* SHLL8   Rn */
   951                     RN(ir) <<= 8;
   952                     break;
   953                 case 0x19: /* SHLR8   Rn */
   954                     RN(ir) >>= 8;
   955                     break;
   956                 case 0x1A: /* LDS     Rn, MACL */
   957                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   958                         (uint64_t)((uint32_t)(RN(ir)));
   959                     break;
   960                 case 0x1B: /* TAS.B   [Rn] */
   961                     tmp = MEM_READ_BYTE( RN(ir) );
   962                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   963                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   964                     break;
   965                 case 0x1E: /* LDC     Rn, GBR */
   966                     sh4r.gbr = RN(ir);
   967                     break;
   968                 case 0x20: /* SHAL    Rn */
   969                     sh4r.t = RN(ir) >> 31;
   970                     RN(ir) <<= 1;
   971                     break;
   972                 case 0x21: /* SHAR    Rn */
   973                     sh4r.t = RN(ir) & 0x00000001;
   974                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   975                     break;
   976                 case 0x22: /* STS.L   PR, [--Rn] */
   977                     RN(ir) -= 4;
   978 		    CHECKWALIGN32( RN(ir) );
   979                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   980                     break;
   981                 case 0x23: /* STC.L   VBR, [--Rn] */
   982                     CHECKPRIV();
   983                     RN(ir) -= 4;
   984 		    CHECKWALIGN32( RN(ir) );
   985                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   986                     break;
   987                 case 0x24: /* ROTCL   Rn */
   988                     tmp = RN(ir) >> 31;
   989                     RN(ir) <<= 1;
   990                     RN(ir) |= sh4r.t;
   991                     sh4r.t = tmp;
   992                     break;
   993                 case 0x25: /* ROTCR   Rn */
   994                     tmp = RN(ir) & 0x00000001;
   995                     RN(ir) >>= 1;
   996                     RN(ir) |= (sh4r.t << 31 );
   997                     sh4r.t = tmp;
   998                     break;
   999                 case 0x26: /* LDS.L   [Rn++], PR */
  1000 		    CHECKRALIGN32( RN(ir) );
  1001                     sh4r.pr = MEM_READ_LONG( RN(ir) );
  1002                     RN(ir) += 4;
  1003                     break;
  1004                 case 0x27: /* LDC.L   [Rn++], VBR */
  1005                     CHECKPRIV();
  1006 		    CHECKRALIGN32( RN(ir) );
  1007                     sh4r.vbr = MEM_READ_LONG(RN(ir));
  1008                     RN(ir) +=4;
  1009                     break;
  1010                 case 0x28: /* SHLL16  Rn */
  1011                     RN(ir) <<= 16;
  1012                     break;
  1013                 case 0x29: /* SHLR16  Rn */
  1014                     RN(ir) >>= 16;
  1015                     break;
  1016                 case 0x2A: /* LDS     Rn, PR */
  1017                     sh4r.pr = RN(ir);
  1018                     break;
  1019                 case 0x2B: /* JMP     [Rn] */
  1020                     CHECKDEST( RN(ir) );
  1021                     CHECKSLOTILLEGAL();
  1022                     sh4r.in_delay_slot = 1;
  1023                     sh4r.pc = sh4r.new_pc;
  1024                     sh4r.new_pc = RN(ir);
  1025                     return TRUE;
  1026                 case 0x2E: /* LDC     Rn, VBR */
  1027                     CHECKPRIV();
  1028                     sh4r.vbr = RN(ir);
  1029                     break;
  1030                 case 0x32: /* STC.L   SGR, [--Rn] */
  1031                     CHECKPRIV();
  1032                     RN(ir) -= 4;
  1033 		    CHECKWALIGN32( RN(ir) );
  1034                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
  1035                     break;
  1036                 case 0x33: /* STC.L   SSR, [--Rn] */
  1037                     CHECKPRIV();
  1038                     RN(ir) -= 4;
  1039 		    CHECKWALIGN32( RN(ir) );
  1040                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
  1041                     break;
  1042                 case 0x37: /* LDC.L   [Rn++], SSR */
  1043                     CHECKPRIV();
  1044 		    CHECKRALIGN32( RN(ir) );
  1045                     sh4r.ssr = MEM_READ_LONG(RN(ir));
  1046                     RN(ir) +=4;
  1047                     break;
  1048                 case 0x3E: /* LDC     Rn, SSR */
  1049                     CHECKPRIV();
  1050                     sh4r.ssr = RN(ir);
  1051                     break;
  1052                 case 0x43: /* STC.L   SPC, [--Rn] */
  1053                     CHECKPRIV();
  1054                     RN(ir) -= 4;
  1055 		    CHECKWALIGN32( RN(ir) );
  1056                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
  1057                     break;
  1058                 case 0x47: /* LDC.L   [Rn++], SPC */
  1059                     CHECKPRIV();
  1060 		    CHECKRALIGN32( RN(ir) );
  1061                     sh4r.spc = MEM_READ_LONG(RN(ir));
  1062                     RN(ir) +=4;
  1063                     break;
  1064                 case 0x4E: /* LDC     Rn, SPC */
  1065                     CHECKPRIV();
  1066                     sh4r.spc = RN(ir);
  1067                     break;
  1068                 case 0x52: /* STS.L   FPUL, [--Rn] */
  1069                     RN(ir) -= 4;
  1070 		    CHECKWALIGN32( RN(ir) );
  1071                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
  1072                     break;
  1073                 case 0x56: /* LDS.L   [Rn++], FPUL */
  1074 		    CHECKRALIGN32( RN(ir) );
  1075                     sh4r.fpul = MEM_READ_LONG(RN(ir));
  1076                     RN(ir) +=4;
  1077                     break;
  1078                 case 0x5A: /* LDS     Rn, FPUL */
  1079                     sh4r.fpul = RN(ir);
  1080                     break;
  1081                 case 0x62: /* STS.L   FPSCR, [--Rn] */
  1082                     RN(ir) -= 4;
  1083 		    CHECKWALIGN32( RN(ir) );
  1084                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
  1085                     break;
  1086                 case 0x66: /* LDS.L   [Rn++], FPSCR */
  1087 		    CHECKRALIGN32( RN(ir) );
  1088                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
  1089                     RN(ir) +=4;
  1090                     break;
  1091                 case 0x6A: /* LDS     Rn, FPSCR */
  1092                     sh4r.fpscr = RN(ir);
  1093                     break;
  1094                 case 0xF2: /* STC.L   DBR, [--Rn] */
  1095                     CHECKPRIV();
  1096                     RN(ir) -= 4;
  1097 		    CHECKWALIGN32( RN(ir) );
  1098                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
  1099                     break;
  1100                 case 0xF6: /* LDC.L   [Rn++], DBR */
  1101                     CHECKPRIV();
  1102 		    CHECKRALIGN32( RN(ir) );
  1103                     sh4r.dbr = MEM_READ_LONG(RN(ir));
  1104                     RN(ir) +=4;
  1105                     break;
  1106                 case 0xFA: /* LDC     Rn, DBR */
  1107                     CHECKPRIV();
  1108                     sh4r.dbr = RN(ir);
  1109                     break;
  1110                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
  1111                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
  1112                     CHECKPRIV();
  1113                     RN(ir) -= 4;
  1114 		    CHECKWALIGN32( RN(ir) );
  1115                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
  1116                     break;
  1117                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
  1118                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
  1119                     CHECKPRIV();
  1120 		    CHECKRALIGN32( RN(ir) );
  1121                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
  1122                     RN(ir) += 4;
  1123                     break;
  1124                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
  1125                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
  1126                     CHECKPRIV();
  1127                     RN_BANK(ir) = RM(ir);
  1128                     break;
  1129                 default:
  1130                     if( (ir&0x000F) == 0x0F ) {
  1131                         /* MAC.W   [Rm++], [Rn++] */
  1132 			CHECKRALIGN16( RN(ir) );
  1133 			CHECKRALIGN16( RM(ir) );
  1134                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
  1135                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
  1136                         if( sh4r.s ) {
  1137                             /* FIXME */
  1138                             UNIMP(ir);
  1139                         } else sh4r.mac += SIGNEXT32(tmp);
  1140                         RM(ir) += 2;
  1141                         RN(ir) += 2;
  1142                     } else if( (ir&0x000F) == 0x0C ) {
  1143                         /* SHAD    Rm, Rn */
  1144                         tmp = RM(ir);
  1145                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1146                         else if( (tmp & 0x1F) == 0 )  
  1147 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
  1148                         else 
  1149 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
  1150                     } else if( (ir&0x000F) == 0x0D ) {
  1151                         /* SHLD    Rm, Rn */
  1152                         tmp = RM(ir);
  1153                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
  1154                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
  1155                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
  1156                     } else UNDEF(ir);
  1158             break;
  1159         case 5: /* 0101nnnnmmmmdddd */
  1160             /* MOV.L   [Rm + disp4*4], Rn */
  1161 	    tmp = RM(ir) + (DISP4(ir)<<2);
  1162 	    CHECKRALIGN32( tmp );
  1163             RN(ir) = MEM_READ_LONG( tmp );
  1164             break;
  1165         case 6: /* 0110xxxxxxxxxxxx */
  1166             switch( ir&0x000f ) {
  1167                 case 0: /* MOV.B   [Rm], Rn */
  1168                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1169                     break;
  1170                 case 1: /* MOV.W   [Rm], Rn */
  1171 		    CHECKRALIGN16( RM(ir) );
  1172                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1173                     break;
  1174                 case 2: /* MOV.L   [Rm], Rn */
  1175 		    CHECKRALIGN32( RM(ir) );
  1176                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1177                     break;
  1178                 case 3: /* MOV     Rm, Rn */
  1179                     RN(ir) = RM(ir);
  1180                     break;
  1181                 case 4: /* MOV.B   [Rm++], Rn */
  1182                     RN(ir) = MEM_READ_BYTE( RM(ir) );
  1183                     RM(ir) ++;
  1184                     break;
  1185                 case 5: /* MOV.W   [Rm++], Rn */
  1186 		    CHECKRALIGN16( RM(ir) );
  1187                     RN(ir) = MEM_READ_WORD( RM(ir) );
  1188                     RM(ir) += 2;
  1189                     break;
  1190                 case 6: /* MOV.L   [Rm++], Rn */
  1191 		    CHECKRALIGN32( RM(ir) );
  1192                     RN(ir) = MEM_READ_LONG( RM(ir) );
  1193                     RM(ir) += 4;
  1194                     break;
  1195                 case 7: /* NOT     Rm, Rn */
  1196                     RN(ir) = ~RM(ir);
  1197                     break;
  1198                 case 8: /* SWAP.B  Rm, Rn */
  1199                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
  1200                         ((RM(ir)&0x000000FF)<<8);
  1201                     break;
  1202                 case 9: /* SWAP.W  Rm, Rn */
  1203                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
  1204                     break;
  1205                 case 10:/* NEGC    Rm, Rn */
  1206                     tmp = 0 - RM(ir);
  1207                     RN(ir) = tmp - sh4r.t;
  1208                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
  1209                     break;
  1210                 case 11:/* NEG     Rm, Rn */
  1211                     RN(ir) = 0 - RM(ir);
  1212                     break;
  1213                 case 12:/* EXTU.B  Rm, Rn */
  1214                     RN(ir) = RM(ir)&0x000000FF;
  1215                     break;
  1216                 case 13:/* EXTU.W  Rm, Rn */
  1217                     RN(ir) = RM(ir)&0x0000FFFF;
  1218                     break;
  1219                 case 14:/* EXTS.B  Rm, Rn */
  1220                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
  1221                     break;
  1222                 case 15:/* EXTS.W  Rm, Rn */
  1223                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
  1224                     break;
  1226             break;
  1227         case 7: /* 0111nnnniiiiiiii */
  1228             /* ADD    imm8, Rn */
  1229             RN(ir) += IMM8(ir);
  1230             break;
  1231         case 8: /* 1000xxxxxxxxxxxx */
  1232             switch( (ir&0x0F00) >> 8 ) {
  1233                 case 0: /* MOV.B   R0, [Rm + disp4] */
  1234                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
  1235                     break;
  1236                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
  1237 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1238 		    CHECKWALIGN16( tmp );
  1239                     MEM_WRITE_WORD( tmp, R0 );
  1240                     break;
  1241                 case 4: /* MOV.B   [Rm + disp4], R0 */
  1242                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
  1243                     break;
  1244                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
  1245 		    tmp = RM(ir) + (DISP4(ir)<<1);
  1246 		    CHECKRALIGN16( tmp );
  1247                     R0 = MEM_READ_WORD( tmp );
  1248                     break;
  1249                 case 8: /* CMP/EQ  imm, R0 */
  1250                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
  1251                     break;
  1252                 case 9: /* BT      disp8 */
  1253                     CHECKSLOTILLEGAL();
  1254                     if( sh4r.t ) {
  1255                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1256                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1257                         sh4r.new_pc = sh4r.pc + 2;
  1258                         return TRUE;
  1260                     break;
  1261                 case 11:/* BF      disp8 */
  1262                     CHECKSLOTILLEGAL();
  1263                     if( !sh4r.t ) {
  1264                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1265                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
  1266                         sh4r.new_pc = sh4r.pc + 2;
  1267                         return TRUE;
  1269                     break;
  1270                 case 13:/* BT/S    disp8 */
  1271                     CHECKSLOTILLEGAL();
  1272                     if( sh4r.t ) {
  1273                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1274                         sh4r.in_delay_slot = 1;
  1275                         sh4r.pc = sh4r.new_pc;
  1276                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1277                         sh4r.in_delay_slot = 1;
  1278                         return TRUE;
  1280                     break;
  1281                 case 15:/* BF/S    disp8 */
  1282                     CHECKSLOTILLEGAL();
  1283                     if( !sh4r.t ) {
  1284                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
  1285                         sh4r.in_delay_slot = 1;
  1286                         sh4r.pc = sh4r.new_pc;
  1287                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
  1288                         return TRUE;
  1290                     break;
  1291                 default: UNDEF(ir);
  1293             break;
  1294         case 9: /* 1001xxxxxxxxxxxx */
  1295             /* MOV.W   [disp8*2 + pc + 4], Rn */
  1296 	    CHECKSLOTILLEGAL();
  1297 	    tmp = pc + 4 + (DISP8(ir)<<1);
  1298             RN(ir) = MEM_READ_WORD( tmp );
  1299             break;
  1300         case 10:/* 1010dddddddddddd */
  1301             /* BRA     disp12 */
  1302             CHECKSLOTILLEGAL();
  1303             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
  1304             sh4r.in_delay_slot = 1;
  1305             sh4r.pc = sh4r.new_pc;
  1306             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1307             return TRUE;
  1308         case 11:/* 1011dddddddddddd */
  1309             /* BSR     disp12 */
  1310             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
  1311 	    CHECKSLOTILLEGAL();
  1312             sh4r.in_delay_slot = 1;
  1313             sh4r.pr = pc + 4;
  1314             sh4r.pc = sh4r.new_pc;
  1315             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1316 	    TRACE_CALL( pc, sh4r.new_pc );
  1317             return TRUE;
  1318         case 12:/* 1100xxxxdddddddd */
  1319         switch( (ir&0x0F00)>>8 ) {
  1320                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1321                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1322                     break;
  1323                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1324 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1325 		    CHECKWALIGN16( tmp );
  1326                     MEM_WRITE_WORD( tmp, R0 );
  1327                     break;
  1328                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1329 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1330 		    CHECKWALIGN32( tmp );
  1331                     MEM_WRITE_LONG( tmp, R0 );
  1332                     break;
  1333                 case 3: /* TRAPA   imm8 */
  1334                     CHECKSLOTILLEGAL();
  1335                     MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
  1336 		    sh4r.pc += 2;
  1337                     sh4_raise_exception( EXC_TRAP );
  1338                     break;
  1339                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1340                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1341                     break;
  1342                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1343 		    tmp = sh4r.gbr + (DISP8(ir)<<1);
  1344 		    CHECKRALIGN16( tmp );
  1345                     R0 = MEM_READ_WORD( tmp );
  1346                     break;
  1347                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1348 		    tmp = sh4r.gbr + (DISP8(ir)<<2);
  1349 		    CHECKRALIGN32( tmp );
  1350                     R0 = MEM_READ_LONG( tmp );
  1351                     break;
  1352                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1353 		    CHECKSLOTILLEGAL();
  1354                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1355                     break;
  1356                 case 8: /* TST     imm8, R0 */
  1357                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1358                     break;
  1359                 case 9: /* AND     imm8, R0 */
  1360                     R0 &= UIMM8(ir);
  1361                     break;
  1362                 case 10:/* XOR     imm8, R0 */
  1363                     R0 ^= UIMM8(ir);
  1364                     break;
  1365                 case 11:/* OR      imm8, R0 */
  1366                     R0 |= UIMM8(ir);
  1367                     break;
  1368                 case 12:/* TST.B   imm8, [R0+GBR] */		    
  1369                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1370                     break;
  1371                 case 13:/* AND.B   imm8, [R0+GBR] */
  1372                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1373                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1374                     break;
  1375                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1376                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1377                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1378                     break;
  1379                 case 15:/* OR.B    imm8, [R0+GBR] */
  1380                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1381                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1382                     break;
  1384             break;
  1385         case 13:/* 1101nnnndddddddd */
  1386             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1387 	    CHECKSLOTILLEGAL();
  1388 	    tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1389             RN(ir) = MEM_READ_LONG( tmp );
  1390             break;
  1391         case 14:/* 1110nnnniiiiiiii */
  1392             /* MOV     imm8, Rn */
  1393             RN(ir) = IMM8(ir);
  1394             break;
  1395         case 15:/* 1111xxxxxxxxxxxx */
  1396             CHECKFPUEN();
  1397 	    if( IS_FPU_DOUBLEPREC() ) {
  1398 		switch( ir&0x000F ) {
  1399                 case 0: /* FADD    FRm, FRn */
  1400                     DRN(ir) += DRM(ir);
  1401                     break;
  1402                 case 1: /* FSUB    FRm, FRn */
  1403                     DRN(ir) -= DRM(ir);
  1404                     break;
  1405                 case 2: /* FMUL    FRm, FRn */
  1406                     DRN(ir) = DRN(ir) * DRM(ir);
  1407                     break;
  1408                 case 3: /* FDIV    FRm, FRn */
  1409                     DRN(ir) = DRN(ir) / DRM(ir);
  1410                     break;
  1411                 case 4: /* FCMP/EQ FRm, FRn */
  1412                     sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
  1413                     break;
  1414                 case 5: /* FCMP/GT FRm, FRn */
  1415                     sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
  1416                     break;
  1417                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1418                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1419                     break;
  1420                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1421                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1422                     break;
  1423                 case 8: /* FMOV.S  [Rm], FRn */
  1424                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1425                     break;
  1426                 case 9: /* FMOV.S  [Rm++], FRn */
  1427                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1428                     RM(ir) += FP_WIDTH;
  1429                     break;
  1430                 case 10:/* FMOV.S  FRm, [Rn] */
  1431                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1432                     break;
  1433                 case 11:/* FMOV.S  FRm, [--Rn] */
  1434                     RN(ir) -= FP_WIDTH;
  1435                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1436                     break;
  1437                 case 12:/* FMOV    FRm, FRn */
  1438 		    if( IS_FPU_DOUBLESIZE() )
  1439 			DRN(ir) = DRM(ir);
  1440 		    else
  1441 			FRN(ir) = FRM(ir);
  1442                     break;
  1443                 case 13:
  1444                     switch( (ir&0x00F0) >> 4 ) {
  1445 		    case 0: /* FSTS    FPUL, FRn */
  1446 			FRN(ir) = FPULf;
  1447 			break;
  1448 		    case 1: /* FLDS    FRn,FPUL */
  1449 			FPULf = FRN(ir);
  1450 			break;
  1451 		    case 2: /* FLOAT   FPUL, FRn */
  1452 			DRN(ir) = (float)FPULi;
  1453 			break;
  1454 		    case 3: /* FTRC    FRn, FPUL */
  1455 			dtmp = DRN(ir);
  1456 			if( dtmp >= MAX_INTF )
  1457 			    FPULi = MAX_INT;
  1458 			else if( dtmp <= MIN_INTF )
  1459 			    FPULi = MIN_INT;
  1460 			else 
  1461 			    FPULi = (int32_t)dtmp;
  1462 			break;
  1463 		    case 4: /* FNEG    FRn */
  1464 			DRN(ir) = -DRN(ir);
  1465 			break;
  1466 		    case 5: /* FABS    FRn */
  1467 			DRN(ir) = fabs(DRN(ir));
  1468 			break;
  1469 		    case 6: /* FSQRT   FRn */
  1470 			DRN(ir) = sqrt(DRN(ir));
  1471 			break;
  1472 		    case 7: /* FSRRA FRn */
  1473 			/* NO-OP when PR=1 */
  1474 			break;
  1475 		    case 8: /* FLDI0   FRn */
  1476 			DRN(ir) = 0.0;
  1477 			break;
  1478 		    case 9: /* FLDI1   FRn */
  1479 			DRN(ir) = 1.0;
  1480 			break;
  1481 		    case 10: /* FCNVSD FPUL, DRn */
  1482 			if( ! IS_FPU_DOUBLESIZE() )
  1483 			    DRN(ir) = (double)FPULf;
  1484 			break;
  1485 		    case 11: /* FCNVDS DRn, FPUL */
  1486 			if( ! IS_FPU_DOUBLESIZE() )
  1487 			    FPULf = (float)DRN(ir);
  1488 			break;
  1489 		    case 14:/* FIPR    FVm, FVn */
  1490 			/* NO-OP when PR=1 */
  1491 			break;
  1492 		    case 15:
  1493 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1494 			    /* NO-OP when PR=1 */
  1495 			    break;
  1497 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */	
  1498 			    /* NO-OP when PR=1 */
  1499 			    break;
  1501 			else if( ir == 0xFBFD ) {
  1502 			    /* FRCHG   */
  1503 			    sh4r.fpscr ^= FPSCR_FR;
  1504 			    break;
  1506 			else if( ir == 0xF3FD ) {
  1507 			    /* FSCHG   */
  1508 			    sh4r.fpscr ^= FPSCR_SZ;
  1509 			    break;
  1511 		    default: UNDEF(ir);
  1513                     break;
  1514                 case 14:/* FMAC    FR0, FRm, FRn */
  1515                     DRN(ir) += DRM(ir)*DR0;
  1516                     break;
  1517                 default: UNDEF(ir);
  1519 	    } else { /* Single precision */
  1520 		switch( ir&0x000F ) {
  1521                 case 0: /* FADD    FRm, FRn */
  1522                     FRN(ir) += FRM(ir);
  1523                     break;
  1524                 case 1: /* FSUB    FRm, FRn */
  1525                     FRN(ir) -= FRM(ir);
  1526                     break;
  1527                 case 2: /* FMUL    FRm, FRn */
  1528                     FRN(ir) = FRN(ir) * FRM(ir);
  1529                     break;
  1530                 case 3: /* FDIV    FRm, FRn */
  1531                     FRN(ir) = FRN(ir) / FRM(ir);
  1532                     break;
  1533                 case 4: /* FCMP/EQ FRm, FRn */
  1534                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1535                     break;
  1536                 case 5: /* FCMP/GT FRm, FRn */
  1537                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1538                     break;
  1539                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1540                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1541                     break;
  1542                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1543                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1544                     break;
  1545                 case 8: /* FMOV.S  [Rm], FRn */
  1546                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1547                     break;
  1548                 case 9: /* FMOV.S  [Rm++], FRn */
  1549                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1550                     RM(ir) += FP_WIDTH;
  1551                     break;
  1552                 case 10:/* FMOV.S  FRm, [Rn] */
  1553                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1554                     break;
  1555                 case 11:/* FMOV.S  FRm, [--Rn] */
  1556                     RN(ir) -= FP_WIDTH;
  1557                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1558                     break;
  1559                 case 12:/* FMOV    FRm, FRn */
  1560 		    if( IS_FPU_DOUBLESIZE() )
  1561 			DRN(ir) = DRM(ir);
  1562 		    else
  1563 			FRN(ir) = FRM(ir);
  1564                     break;
  1565                 case 13:
  1566                     switch( (ir&0x00F0) >> 4 ) {
  1567 		    case 0: /* FSTS    FPUL, FRn */
  1568 			FRN(ir) = FPULf;
  1569 			break;
  1570 		    case 1: /* FLDS    FRn,FPUL */
  1571 			FPULf = FRN(ir);
  1572 			break;
  1573 		    case 2: /* FLOAT   FPUL, FRn */
  1574 			FRN(ir) = (float)FPULi;
  1575 			break;
  1576 		    case 3: /* FTRC    FRn, FPUL */
  1577 			ftmp = FRN(ir);
  1578 			if( ftmp >= MAX_INTF )
  1579 			    FPULi = MAX_INT;
  1580 			else if( ftmp <= MIN_INTF )
  1581 			    FPULi = MIN_INT;
  1582 			else
  1583 			    FPULi = (int32_t)ftmp;
  1584 			break;
  1585 		    case 4: /* FNEG    FRn */
  1586 			FRN(ir) = -FRN(ir);
  1587 			break;
  1588 		    case 5: /* FABS    FRn */
  1589 			FRN(ir) = fabsf(FRN(ir));
  1590 			break;
  1591 		    case 6: /* FSQRT   FRn */
  1592 			FRN(ir) = sqrtf(FRN(ir));
  1593 			break;
  1594 		    case 7: /* FSRRA FRn */
  1595 			FRN(ir) = 1.0/sqrtf(FRN(ir));
  1596 			break;
  1597 		    case 8: /* FLDI0   FRn */
  1598 			FRN(ir) = 0.0;
  1599 			break;
  1600 		    case 9: /* FLDI1   FRn */
  1601 			FRN(ir) = 1.0;
  1602 			break;
  1603 		    case 10: /* FCNVSD FPUL, DRn */
  1604 			break;
  1605 		    case 11: /* FCNVDS DRn, FPUL */
  1606 			break;
  1607 		    case 14:/* FIPR    FVm, FVn */
  1608                             /* FIXME: This is not going to be entirely accurate
  1609                              * as the SH4 instruction is less precise. Also
  1610                              * need to check for 0s and infinities.
  1611                              */
  1613                             int tmp2 = FVN(ir);
  1614                             tmp = FVM(ir);
  1615                             FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1616                                 FR(tmp+1)*FR(tmp2+1) +
  1617                                 FR(tmp+2)*FR(tmp2+2) +
  1618                                 FR(tmp+3)*FR(tmp2+3);
  1619                             break;
  1621 		    case 15:
  1622 			if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1623 			    tmp = FVN(ir);
  1624 			    float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  1625 			    FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
  1626 				XF(8)*fv[2] + XF(12)*fv[3];
  1627 			    FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
  1628 				XF(9)*fv[2] + XF(13)*fv[3];
  1629 			    FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
  1630 				XF(10)*fv[2] + XF(14)*fv[3];
  1631 			    FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
  1632 				XF(11)*fv[2] + XF(15)*fv[3];
  1633 			    break;
  1635 			else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1636 			    float angle = (((float)(short)(FPULi>>16)) +
  1637 					   (((float)(FPULi&0xFFFF))/65536.0)) *
  1638 				2 * M_PI;
  1639 			    int reg = FRNn(ir);
  1640 			    FR(reg) = sinf(angle);
  1641 			    FR(reg+1) = cosf(angle);
  1642 			    break;
  1644 			else if( ir == 0xFBFD ) {
  1645 			    /* FRCHG   */
  1646 			    sh4r.fpscr ^= FPSCR_FR;
  1647 			    break;
  1649 			else if( ir == 0xF3FD ) {
  1650 			    /* FSCHG   */
  1651 			    sh4r.fpscr ^= FPSCR_SZ;
  1652 			    break;
  1654 		    default: UNDEF(ir);
  1656                     break;
  1657                 case 14:/* FMAC    FR0, FRm, FRn */
  1658                     FRN(ir) += FRM(ir)*FR0;
  1659                     break;
  1660                 default: UNDEF(ir);
  1663 	    break;
  1665     sh4r.pc = sh4r.new_pc;
  1666     sh4r.new_pc += 2;
  1667     sh4r.in_delay_slot = 0;
  1668     return TRUE;
.