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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 1173:49207ef698e1
prev1090:71e28626b358
next1198:407659e01ef0
author nkeynes
date Wed May 11 19:20:42 2011 +1000 (11 years ago)
permissions -rw-r--r--
last change Unprotect TLB entries for all systems, not just 64-bit (seems to be needed
on some 32-bit machines)
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     1 /**
     2  * $Id$
     3  *
     4  * SH4 MMU implementation based on address space page maps. This module
     5  * is responsible for all address decoding functions. 
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    19 #define MODULE sh4_module
    21 #include <stdio.h>
    22 #include <assert.h>
    23 #include "sh4/sh4mmio.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4trans.h"
    26 #include "dreamcast.h"
    27 #include "mem.h"
    28 #include "mmu.h"
    30 #define RAISE_TLB_ERROR(code, vpn) sh4_raise_tlb_exception(code, vpn)
    31 #define RAISE_MEM_ERROR(code, vpn) \
    32     MMIO_WRITE(MMU, TEA, vpn); \
    33     MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
    34     sh4_raise_exception(code);
    35 #define RAISE_TLB_MULTIHIT_ERROR(vpn) sh4_raise_tlb_multihit(vpn)
    37 /* An entry is a 1K entry if it's one of the mmu_utlb_1k_pages entries */
    38 #define IS_1K_PAGE_ENTRY(ent)  ( ((uintptr_t)(((struct utlb_1k_entry *)ent) - &mmu_utlb_1k_pages[0])) < UTLB_ENTRY_COUNT )
    40 /* Primary address space (used directly by SH4 cores) */
    41 mem_region_fn_t *sh4_address_space;
    42 mem_region_fn_t *sh4_user_address_space;
    44 /* Accessed from the UTLB accessor methods */
    45 uint32_t mmu_urc;
    46 uint32_t mmu_urb;
    47 static gboolean mmu_urc_overflow; /* If true, urc was set >= urb */  
    49 /* Module globals */
    50 static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
    51 static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
    52 static struct utlb_page_entry mmu_utlb_pages[UTLB_ENTRY_COUNT];
    53 static uint32_t mmu_lrui;
    54 static uint32_t mmu_asid; // current asid
    55 static struct utlb_default_regions *mmu_user_storequeue_regions;
    57 /* Structures for 1K page handling */
    58 static struct utlb_1k_entry mmu_utlb_1k_pages[UTLB_ENTRY_COUNT];
    59 static int mmu_utlb_1k_free_list[UTLB_ENTRY_COUNT];
    60 static int mmu_utlb_1k_free_index;
    63 /* Function prototypes */
    64 static void mmu_invalidate_tlb();
    65 static void mmu_utlb_register_all();
    66 static void mmu_utlb_remove_entry(int);
    67 static void mmu_utlb_insert_entry(int);
    68 static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
    69 static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn );
    70 static void mmu_set_tlb_enabled( int tlb_on );
    71 static void mmu_set_tlb_asid( uint32_t asid );
    72 static void mmu_set_storequeue_protected( int protected, int tlb_on );
    73 static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages );
    74 static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo );
    75 static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages );
    76 static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data );
    77 static void mmu_utlb_1k_init();
    78 static struct utlb_1k_entry *mmu_utlb_1k_alloc();
    79 static void mmu_utlb_1k_free( struct utlb_1k_entry *entry );
    80 static int mmu_read_urc();
    82 static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc );
    83 static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc );
    84 static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc );
    85 static int32_t FASTCALL tlb_protected_read_for_write( sh4addr_t addr, void *exc );
    86 static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc );
    87 static int32_t FASTCALL tlb_initial_read_for_write( sh4addr_t addr, void *exc );
    88 static uint32_t get_tlb_size_mask( uint32_t flags );
    89 static uint32_t get_tlb_size_pages( uint32_t flags );
    91 #define DEFAULT_REGIONS 0
    92 #define DEFAULT_STOREQUEUE_REGIONS 1
    93 #define DEFAULT_STOREQUEUE_SQMD_REGIONS 2
    95 static struct utlb_default_regions mmu_default_regions[3] = {
    96         { &mem_region_tlb_miss, &mem_region_tlb_protected, &mem_region_tlb_multihit },
    97         { &p4_region_storequeue_miss, &p4_region_storequeue_protected, &p4_region_storequeue_multihit },
    98         { &p4_region_storequeue_sqmd_miss, &p4_region_storequeue_sqmd_protected, &p4_region_storequeue_sqmd_multihit } };
   100 #define IS_STOREQUEUE_PROTECTED() (mmu_user_storequeue_regions == &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS])
   102 /*********************** Module public functions ****************************/
   104 /**
   105  * Allocate memory for the address space maps, and initialize them according
   106  * to the default (reset) values. (TLB is disabled by default)
   107  */
   109 void MMU_init()
   110 {
   111     sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
   112     sh4_user_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
   113     mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   115     mmu_set_tlb_enabled(0);
   116     mmu_register_user_mem_region( 0x80000000, 0x00000000, &mem_region_address_error );
   117     mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );                                
   119     /* Setup P4 tlb/cache access regions */
   120     mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   121     mmu_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
   122     mmu_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
   123     mmu_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
   124     mmu_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
   125     mmu_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
   126     mmu_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
   127     mmu_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
   128     mmu_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
   129     mmu_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
   130     mmu_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
   132     /* Setup P4 control region */
   133     mmu_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
   134     mmu_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
   135     mmu_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
   136     mmu_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
   137     mmu_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
   138     mmu_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
   139     mmu_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
   140     mmu_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
   141     mmu_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
   142     mmu_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
   143     mmu_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
   144     mmu_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
   145     mmu_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
   147     register_mem_page_remapped_hook( mmu_ext_page_remapped, NULL );
   148     mmu_utlb_1k_init();
   150     /* Ensure the code regions are executable. Although it might
   151      * be more portable to mmap these at runtime rather than using static decls
   152      */
   153     mem_unprotect( mmu_utlb_pages, sizeof(mmu_utlb_pages) );
   154     mem_unprotect( mmu_utlb_1k_pages, sizeof(mmu_utlb_1k_pages) );
   155 }
   157 void MMU_reset()
   158 {
   159     mmio_region_MMU_write( CCR, 0 );
   160     mmio_region_MMU_write( MMUCR, 0 );
   161 }
   163 void MMU_save_state( FILE *f )
   164 {
   165     mmu_read_urc();   
   166     fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
   167     fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
   168     fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
   169     fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
   170     fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
   171     fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
   172 }
   174 int MMU_load_state( FILE *f )
   175 {
   176     if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
   177         return 1;
   178     }
   179     if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
   180         return 1;
   181     }
   182     if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
   183         return 1;
   184     }
   185     if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
   186         return 1;
   187     }
   188     if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
   189         return 1;
   190     }
   191     if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
   192         return 1;
   193     }
   195     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
   196     mmu_urc_overflow = mmu_urc >= mmu_urb;
   197     mmu_set_tlb_enabled(mmucr&MMUCR_AT);
   198     mmu_set_storequeue_protected(mmucr&MMUCR_SQMD, mmucr&MMUCR_AT);
   199     return 0;
   200 }
   202 /**
   203  * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
   204  * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
   205  */
   206 void MMU_ldtlb()
   207 {
   208     int urc = mmu_read_urc();
   209     if( IS_TLB_ENABLED() && mmu_utlb[urc].flags & TLB_VALID )
   210         mmu_utlb_remove_entry( urc );
   211     mmu_utlb[urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
   212     mmu_utlb[urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
   213     mmu_utlb[urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
   214     mmu_utlb[urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
   215     mmu_utlb[urc].pcmcia = MMIO_READ(MMU, PTEA);
   216     mmu_utlb[urc].mask = get_tlb_size_mask(mmu_utlb[urc].flags);
   217     if( IS_TLB_ENABLED() && mmu_utlb[urc].flags & TLB_VALID )
   218         mmu_utlb_insert_entry( urc );
   219 }
   222 MMIO_REGION_READ_FN( MMU, reg )
   223 {
   224     reg &= 0xFFF;
   225     switch( reg ) {
   226     case MMUCR:
   227         return MMIO_READ( MMU, MMUCR) | (mmu_read_urc()<<10) | ((mmu_urb&0x3F)<<18) | (mmu_lrui<<26);
   228     default:
   229         return MMIO_READ( MMU, reg );
   230     }
   231 }
   233 MMIO_REGION_READ_DEFSUBFNS(MMU)
   235 MMIO_REGION_WRITE_FN( MMU, reg, val )
   236 {
   237     uint32_t tmp;
   238     reg &= 0xFFF;
   239     switch(reg) {
   240     case SH4VER:
   241         return;
   242     case PTEH:
   243         val &= 0xFFFFFCFF;
   244         if( (val & 0xFF) != mmu_asid ) {
   245             mmu_set_tlb_asid( val&0xFF );
   246         }
   247         break;
   248     case PTEL:
   249         val &= 0x1FFFFDFF;
   250         break;
   251     case PTEA:
   252         val &= 0x0000000F;
   253         break;
   254     case TRA:
   255         val &= 0x000003FC;
   256         break;
   257     case EXPEVT:
   258     case INTEVT:
   259         val &= 0x00000FFF;
   260         break;
   261     case MMUCR:
   262         if( val & MMUCR_TI ) {
   263             mmu_invalidate_tlb();
   264         }
   265         mmu_urc = (val >> 10) & 0x3F;
   266         mmu_urb = (val >> 18) & 0x3F;
   267         if( mmu_urb == 0 ) {
   268             mmu_urb = 0x40;
   269         } else if( mmu_urc >= mmu_urb ) {
   270             mmu_urc_overflow = TRUE;
   271         }
   272         mmu_lrui = (val >> 26) & 0x3F;
   273         val &= 0x00000301;
   274         tmp = MMIO_READ( MMU, MMUCR );
   275         if( (val ^ tmp) & (MMUCR_SQMD) ) {
   276             mmu_set_storequeue_protected( val & MMUCR_SQMD, val&MMUCR_AT );
   277         }
   278         if( (val ^ tmp) & (MMUCR_AT) ) {
   279             // AT flag has changed state - flush the xlt cache as all bets
   280             // are off now. We also need to force an immediate exit from the
   281             // current block
   282             mmu_set_tlb_enabled( val & MMUCR_AT );
   283             MMIO_WRITE( MMU, MMUCR, val );
   284             sh4_core_exit( CORE_EXIT_FLUSH_ICACHE );
   285             xlat_flush_cache(); // If we're not running, flush the cache anyway
   286         }
   287         break;
   288     case CCR:
   289         CCN_set_cache_control( val );
   290         val &= 0x81A7;
   291         break;
   292     case MMUUNK1:
   293         /* Note that if the high bit is set, this appears to reset the machine.
   294          * Not emulating this behaviour yet until we know why...
   295          */
   296         val &= 0x00010007;
   297         break;
   298     case QACR0:
   299     case QACR1:
   300         val &= 0x0000001C;
   301         break;
   302     case PMCR1:
   303         PMM_write_control(0, val);
   304         val &= 0x0000C13F;
   305         break;
   306     case PMCR2:
   307         PMM_write_control(1, val);
   308         val &= 0x0000C13F;
   309         break;
   310     default:
   311         break;
   312     }
   313     MMIO_WRITE( MMU, reg, val );
   314 }
   316 /********************** 1K Page handling ***********************/
   317 /* Since we use 4K pages as our native page size, 1K pages need a bit of extra
   318  * effort to manage - we justify this on the basis that most programs won't
   319  * actually use 1K pages, so we may as well optimize for the common case.
   320  * 
   321  * Implementation uses an intermediate page entry (the utlb_1k_entry) that
   322  * redirects requests to the 'real' page entry. These are allocated on an
   323  * as-needed basis, and returned to the pool when all subpages are empty.
   324  */ 
   325 static void mmu_utlb_1k_init()
   326 {
   327     int i;
   328     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   329         mmu_utlb_1k_free_list[i] = i;
   330         mmu_utlb_1k_init_vtable( &mmu_utlb_1k_pages[i] );
   331     }
   332     mmu_utlb_1k_free_index = 0;
   333 }
   335 static struct utlb_1k_entry *mmu_utlb_1k_alloc()
   336 {
   337     assert( mmu_utlb_1k_free_index < UTLB_ENTRY_COUNT );
   338     struct utlb_1k_entry *entry = &mmu_utlb_1k_pages[mmu_utlb_1k_free_list[mmu_utlb_1k_free_index++]];
   339     return entry;
   340 }    
   342 static void mmu_utlb_1k_free( struct utlb_1k_entry *ent )
   343 {
   344     unsigned int entryNo = ent - &mmu_utlb_1k_pages[0];
   345     assert( entryNo < UTLB_ENTRY_COUNT );
   346     assert( mmu_utlb_1k_free_index > 0 );
   347     mmu_utlb_1k_free_list[--mmu_utlb_1k_free_index] = entryNo;
   348 }
   351 /********************** Address space maintenance *************************/
   353 /**
   354  * MMU accessor functions just increment URC - fixup here if necessary
   355  */
   356 static int mmu_read_urc()
   357 {
   358     if( mmu_urc_overflow ) {
   359         if( mmu_urc >= 0x40 ) {
   360             mmu_urc_overflow = FALSE;
   361             mmu_urc -= 0x40;
   362             mmu_urc %= mmu_urb;
   363         }
   364     } else {
   365         mmu_urc %= mmu_urb;
   366     }
   367     return mmu_urc;
   368 }
   370 static void mmu_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
   371 {
   372     int count = (end - start) >> 12;
   373     mem_region_fn_t *ptr = &sh4_address_space[start>>12];
   374     while( count-- > 0 ) {
   375         *ptr++ = fn;
   376     }
   377 }
   378 static void mmu_register_user_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
   379 {
   380     int count = (end - start) >> 12;
   381     mem_region_fn_t *ptr = &sh4_user_address_space[start>>12];
   382     while( count-- > 0 ) {
   383         *ptr++ = fn;
   384     }
   385 }
   387 static gboolean mmu_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
   388 {
   389     unsigned int i;
   390     if( (MMIO_READ(MMU,MMUCR)) & MMUCR_AT ) {
   391         /* TLB on */
   392         sh4_address_space[(page|0x80000000)>>12] = fn; /* Direct map to P1 and P2 */
   393         sh4_address_space[(page|0xA0000000)>>12] = fn;
   394         /* Scan UTLB and update any direct-referencing entries */
   395     } else {
   396         /* Direct map to U0, P0, P1, P2, P3 */
   397         for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
   398             sh4_address_space[(page|i)>>12] = fn;
   399         }
   400         for( i=0; i < 0x80000000; i+= 0x20000000 ) {
   401             sh4_user_address_space[(page|i)>>12] = fn;
   402         }
   403     }
   404     return TRUE;
   405 }
   407 static void mmu_set_tlb_enabled( int tlb_on )
   408 {
   409     mem_region_fn_t *ptr, *uptr;
   410     int i;
   412     /* Reset the storequeue area */
   414     if( tlb_on ) {
   415         mmu_register_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
   416         mmu_register_mem_region(0xC0000000, 0xE0000000, &mem_region_tlb_miss );
   417         mmu_register_user_mem_region(0x00000000, 0x80000000, &mem_region_tlb_miss );
   419         /* Default SQ prefetch goes to TLB miss (?) */
   420         mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_miss );
   421         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
   422         mmu_utlb_register_all();
   423     } else {
   424         for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
   425             memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
   426         }
   427         for( i=0, ptr = sh4_user_address_space; i<4; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
   428             memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
   429         }
   431         mmu_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   432         if( IS_STOREQUEUE_PROTECTED() ) {
   433             mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue_sqmd );
   434         } else {
   435             mmu_register_user_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
   436         }
   437     }
   439 }
   441 /**
   442  * Flip the SQMD switch - this is rather expensive, so will need to be changed if
   443  * anything expects to do this frequently.
   444  */
   445 static void mmu_set_storequeue_protected( int protected, int tlb_on ) 
   446 {
   447     mem_region_fn_t nontlb_region;
   448     int i;
   450     if( protected ) {
   451         mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_SQMD_REGIONS];
   452         nontlb_region = &p4_region_storequeue_sqmd;
   453     } else {
   454         mmu_user_storequeue_regions = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   455         nontlb_region = &p4_region_storequeue; 
   456     }
   458     if( tlb_on ) {
   459         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, mmu_user_storequeue_regions->tlb_miss );
   460         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   461             if( (mmu_utlb[i].vpn & 0xFC000000) == 0xE0000000 ) {
   462                 mmu_utlb_insert_entry(i);
   463             }
   464         }
   465     } else {
   466         mmu_register_user_mem_region( 0xE0000000, 0xE4000000, nontlb_region ); 
   467     }
   469 }
   471 static void mmu_set_tlb_asid( uint32_t asid )
   472 {
   473     if( IS_TLB_ENABLED() ) {
   474         /* Scan for pages that need to be remapped */
   475         int i;
   476         if( IS_SV_ENABLED() ) {
   477             for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   478                 if( mmu_utlb[i].asid == mmu_asid &&
   479                         (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
   480                     // Matches old ASID - unmap out
   481                     if( !mmu_utlb_unmap_pages( FALSE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
   482                             get_tlb_size_pages(mmu_utlb[i].flags) ) )
   483                         mmu_utlb_remap_pages( FALSE, TRUE, i );
   484                 }
   485             }
   486             for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   487                 if( mmu_utlb[i].asid == asid &&
   488                         (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
   489                     // Matches new ASID - map in
   490                     mmu_utlb_map_pages( NULL, mmu_utlb_pages[i].user_fn,
   491                             mmu_utlb[i].vpn&mmu_utlb[i].mask,
   492                             get_tlb_size_pages(mmu_utlb[i].flags) );
   493                 }
   494             }
   495         } else {
   496             // Remap both Priv+user pages
   497             for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   498                 if( mmu_utlb[i].asid == mmu_asid &&
   499                         (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
   500                     if( !mmu_utlb_unmap_pages( TRUE, TRUE, mmu_utlb[i].vpn&mmu_utlb[i].mask,
   501                             get_tlb_size_pages(mmu_utlb[i].flags) ) )
   502                         mmu_utlb_remap_pages( TRUE, TRUE, i );
   503                 }
   504             }
   505             for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   506                 if( mmu_utlb[i].asid == asid &&
   507                         (mmu_utlb[i].flags & (TLB_VALID|TLB_SHARE)) == (TLB_VALID) ) {
   508                     mmu_utlb_map_pages( &mmu_utlb_pages[i].fn, mmu_utlb_pages[i].user_fn,
   509                             mmu_utlb[i].vpn&mmu_utlb[i].mask,
   510                             get_tlb_size_pages(mmu_utlb[i].flags) );
   511                 }
   512             }
   513         }
   514         sh4_icache.page_vma = -1; // invalidate icache as asid has changed
   515     }
   516     mmu_asid = asid;
   517 }
   519 static uint32_t get_tlb_size_mask( uint32_t flags )
   520 {
   521     switch( flags & TLB_SIZE_MASK ) {
   522     case TLB_SIZE_1K: return MASK_1K;
   523     case TLB_SIZE_4K: return MASK_4K;
   524     case TLB_SIZE_64K: return MASK_64K;
   525     case TLB_SIZE_1M: return MASK_1M;
   526     default: return 0; /* Unreachable */
   527     }
   528 }
   529 static uint32_t get_tlb_size_pages( uint32_t flags )
   530 {
   531     switch( flags & TLB_SIZE_MASK ) {
   532     case TLB_SIZE_1K: return 0;
   533     case TLB_SIZE_4K: return 1;
   534     case TLB_SIZE_64K: return 16;
   535     case TLB_SIZE_1M: return 256;
   536     default: return 0; /* Unreachable */
   537     }
   538 }
   540 /**
   541  * Add a new TLB entry mapping to the address space table. If any of the pages
   542  * are already mapped, they are mapped to the TLB multi-hit page instead.
   543  * @return FALSE if a TLB multihit situation was detected, otherwise TRUE.
   544  */ 
   545 static gboolean mmu_utlb_map_pages( mem_region_fn_t priv_page, mem_region_fn_t user_page, sh4addr_t start_addr, int npages )
   546 {
   547     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   548     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   549     struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
   550     struct utlb_default_regions *userdefs = privdefs;    
   552     gboolean mapping_ok = TRUE;
   553     int i;
   555     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   556         /* Storequeue mapping */
   557         privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   558         userdefs = mmu_user_storequeue_regions;
   559     } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
   560         user_page = NULL; /* No user access to P3 region */
   561     } else if( start_addr >= 0x80000000 ) {
   562         return TRUE; // No mapping - legal but meaningless
   563     }
   565     if( npages == 0 ) {
   566         struct utlb_1k_entry *ent;
   567         int i, idx = (start_addr >> 10) & 0x03;
   568         if( IS_1K_PAGE_ENTRY(*ptr) ) {
   569             ent = (struct utlb_1k_entry *)*ptr;
   570         } else {
   571             ent = mmu_utlb_1k_alloc();
   572             /* New 1K struct - init to previous contents of region */
   573             for( i=0; i<4; i++ ) {
   574                 ent->subpages[i] = *ptr;
   575                 ent->user_subpages[i] = *uptr;
   576             }
   577             *ptr = &ent->fn;
   578             *uptr = &ent->user_fn;
   579         }
   581         if( priv_page != NULL ) {
   582             if( ent->subpages[idx] == privdefs->tlb_miss ) {
   583                 ent->subpages[idx] = priv_page;
   584             } else {
   585                 mapping_ok = FALSE;
   586                 ent->subpages[idx] = privdefs->tlb_multihit;
   587             }
   588         }
   589         if( user_page != NULL ) {
   590             if( ent->user_subpages[idx] == userdefs->tlb_miss ) {
   591                 ent->user_subpages[idx] = user_page;
   592             } else {
   593                 mapping_ok = FALSE;
   594                 ent->user_subpages[idx] = userdefs->tlb_multihit;
   595             }
   596         }
   598     } else {
   599         if( priv_page != NULL ) {
   600             /* Privileged mapping only */
   601             for( i=0; i<npages; i++ ) {
   602                 if( *ptr == privdefs->tlb_miss ) {
   603                     *ptr++ = priv_page;
   604                 } else {
   605                     mapping_ok = FALSE;
   606                     *ptr++ = privdefs->tlb_multihit;
   607                 }
   608             }
   609         }
   610         if( user_page != NULL ) {
   611             /* User mapping only (eg ASID change remap w/ SV=1) */
   612             for( i=0; i<npages; i++ ) {
   613                 if( *uptr == userdefs->tlb_miss ) {
   614                     *uptr++ = user_page;
   615                 } else {
   616                     mapping_ok = FALSE;
   617                     *uptr++ = userdefs->tlb_multihit;
   618                 }
   619             }        
   620         }
   621     }
   623     return mapping_ok;
   624 }
   626 /**
   627  * Remap any pages within the region covered by entryNo, but not including 
   628  * entryNo itself. This is used to reestablish pages that were previously
   629  * covered by a multi-hit exception region when one of the pages is removed.
   630  */
   631 static void mmu_utlb_remap_pages( gboolean remap_priv, gboolean remap_user, int entryNo )
   632 {
   633     int mask = mmu_utlb[entryNo].mask;
   634     uint32_t remap_addr = mmu_utlb[entryNo].vpn & mask;
   635     int i;
   637     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   638         if( i != entryNo && (mmu_utlb[i].vpn & mask) == remap_addr && (mmu_utlb[i].flags & TLB_VALID) ) {
   639             /* Overlapping region */
   640             mem_region_fn_t priv_page = (remap_priv ? &mmu_utlb_pages[i].fn : NULL);
   641             mem_region_fn_t user_page = (remap_priv ? mmu_utlb_pages[i].user_fn : NULL);
   642             uint32_t start_addr;
   643             int npages;
   645             if( mmu_utlb[i].mask >= mask ) {
   646                 /* entry is no larger than the area we're replacing - map completely */
   647                 start_addr = mmu_utlb[i].vpn & mmu_utlb[i].mask;
   648                 npages = get_tlb_size_pages( mmu_utlb[i].flags );
   649             } else {
   650                 /* Otherwise map subset - region covered by removed page */
   651                 start_addr = remap_addr;
   652                 npages = get_tlb_size_pages( mmu_utlb[entryNo].flags );
   653             }
   655             if( (mmu_utlb[i].flags & TLB_SHARE) || mmu_utlb[i].asid == mmu_asid ) { 
   656                 mmu_utlb_map_pages( priv_page, user_page, start_addr, npages );
   657             } else if( IS_SV_ENABLED() ) {
   658                 mmu_utlb_map_pages( priv_page, NULL, start_addr, npages );
   659             }
   661         }
   662     }
   663 }
   665 /**
   666  * Remove a previous TLB mapping (replacing them with the TLB miss region).
   667  * @return FALSE if any pages were previously mapped to the TLB multihit page, 
   668  * otherwise TRUE. In either case, all pages in the region are cleared to TLB miss.
   669  */
   670 static gboolean mmu_utlb_unmap_pages( gboolean unmap_priv, gboolean unmap_user, sh4addr_t start_addr, int npages )
   671 {
   672     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   673     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   674     struct utlb_default_regions *privdefs = &mmu_default_regions[DEFAULT_REGIONS];
   675     struct utlb_default_regions *userdefs = privdefs;
   677     gboolean unmapping_ok = TRUE;
   678     int i;
   680     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   681         /* Storequeue mapping */
   682         privdefs = &mmu_default_regions[DEFAULT_STOREQUEUE_REGIONS];
   683         userdefs = mmu_user_storequeue_regions;
   684     } else if( (start_addr & 0xE0000000) == 0xC0000000 ) {
   685         unmap_user = FALSE;
   686     } else if( start_addr >= 0x80000000 ) {
   687         return TRUE; // No mapping - legal but meaningless
   688     }
   690     if( npages == 0 ) { // 1K page
   691         assert( IS_1K_PAGE_ENTRY( *ptr ) );
   692         struct utlb_1k_entry *ent = (struct utlb_1k_entry *)*ptr;
   693         int i, idx = (start_addr >> 10) & 0x03, mergeable=1;
   694         if( ent->subpages[idx] == privdefs->tlb_multihit ) {
   695             unmapping_ok = FALSE;
   696         }
   697         if( unmap_priv )
   698             ent->subpages[idx] = privdefs->tlb_miss;
   699         if( unmap_user )
   700             ent->user_subpages[idx] = userdefs->tlb_miss;
   702         /* If all 4 subpages have the same content, merge them together and
   703          * release the 1K entry
   704          */
   705         mem_region_fn_t priv_page = ent->subpages[0];
   706         mem_region_fn_t user_page = ent->user_subpages[0];
   707         for( i=1; i<4; i++ ) {
   708             if( priv_page != ent->subpages[i] || user_page != ent->user_subpages[i] ) {
   709                 mergeable = 0;
   710                 break;
   711             }
   712         }
   713         if( mergeable ) {
   714             mmu_utlb_1k_free(ent);
   715             *ptr = priv_page;
   716             *uptr = user_page;
   717         }
   718     } else {
   719         if( unmap_priv ) {
   720             /* Privileged (un)mapping */
   721             for( i=0; i<npages; i++ ) {
   722                 if( *ptr == privdefs->tlb_multihit ) {
   723                     unmapping_ok = FALSE;
   724                 }
   725                 *ptr++ = privdefs->tlb_miss;
   726             }
   727         }
   728         if( unmap_user ) {
   729             /* User (un)mapping */
   730             for( i=0; i<npages; i++ ) {
   731                 if( *uptr == userdefs->tlb_multihit ) {
   732                     unmapping_ok = FALSE;
   733                 }
   734                 *uptr++ = userdefs->tlb_miss;
   735             }            
   736         }
   737     }
   739     return unmapping_ok;
   740 }
   742 static void mmu_utlb_insert_entry( int entry )
   743 {
   744     struct utlb_entry *ent = &mmu_utlb[entry];
   745     mem_region_fn_t page = &mmu_utlb_pages[entry].fn;
   746     mem_region_fn_t upage;
   747     sh4addr_t start_addr = ent->vpn & ent->mask;
   748     int npages = get_tlb_size_pages(ent->flags);
   750     if( (start_addr & 0xFC000000) == 0xE0000000 ) {
   751         /* Store queue mappings are a bit different - normal access is fixed to
   752          * the store queue register block, and we only map prefetches through
   753          * the TLB 
   754          */
   755         mmu_utlb_init_storequeue_vtable( ent, &mmu_utlb_pages[entry] );
   757         if( (ent->flags & TLB_USERMODE) == 0 ) {
   758             upage = mmu_user_storequeue_regions->tlb_prot;
   759         } else if( IS_STOREQUEUE_PROTECTED() ) {
   760             upage = &p4_region_storequeue_sqmd;
   761         } else {
   762             upage = page;
   763         }
   765     }  else {
   767         if( (ent->flags & TLB_USERMODE) == 0 ) {
   768             upage = &mem_region_tlb_protected;
   769         } else {        
   770             upage = page;
   771         }
   773         if( (ent->flags & TLB_WRITABLE) == 0 ) {
   774             page->write_long = (mem_write_fn_t)tlb_protected_write;
   775             page->write_word = (mem_write_fn_t)tlb_protected_write;
   776             page->write_byte = (mem_write_fn_t)tlb_protected_write;
   777             page->write_burst = (mem_write_burst_fn_t)tlb_protected_write;
   778             page->read_byte_for_write = (mem_read_fn_t)tlb_protected_read_for_write;
   779             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
   780         } else if( (ent->flags & TLB_DIRTY) == 0 ) {
   781             page->write_long = (mem_write_fn_t)tlb_initial_write;
   782             page->write_word = (mem_write_fn_t)tlb_initial_write;
   783             page->write_byte = (mem_write_fn_t)tlb_initial_write;
   784             page->write_burst = (mem_write_burst_fn_t)tlb_initial_write;
   785             page->read_byte_for_write = (mem_read_fn_t)tlb_initial_read_for_write;
   786             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], FALSE );
   787         } else {
   788             mmu_utlb_init_vtable( ent, &mmu_utlb_pages[entry], TRUE );
   789         }
   790     }
   792     mmu_utlb_pages[entry].user_fn = upage;
   794     /* Is page visible? */
   795     if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) { 
   796         mmu_utlb_map_pages( page, upage, start_addr, npages );
   797     } else if( IS_SV_ENABLED() ) {
   798         mmu_utlb_map_pages( page, NULL, start_addr, npages );
   799     }
   800 }
   802 static void mmu_utlb_remove_entry( int entry )
   803 {
   804     int i, j;
   805     struct utlb_entry *ent = &mmu_utlb[entry];
   806     sh4addr_t start_addr = ent->vpn&ent->mask;
   807     mem_region_fn_t *ptr = &sh4_address_space[start_addr >> 12];
   808     mem_region_fn_t *uptr = &sh4_user_address_space[start_addr >> 12];
   809     gboolean unmap_user;
   810     int npages = get_tlb_size_pages(ent->flags);
   812     if( (ent->flags & TLB_SHARE) || ent->asid == mmu_asid ) {
   813         unmap_user = TRUE;
   814     } else if( IS_SV_ENABLED() ) {
   815         unmap_user = FALSE;
   816     } else {
   817         return; // Not mapped
   818     }
   820     gboolean clean_unmap = mmu_utlb_unmap_pages( TRUE, unmap_user, start_addr, npages );
   822     if( !clean_unmap ) {
   823         mmu_utlb_remap_pages( TRUE, unmap_user, entry );
   824     }
   825 }
   827 static void mmu_utlb_register_all()
   828 {
   829     int i;
   830     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   831         if( mmu_utlb[i].flags & TLB_VALID ) 
   832             mmu_utlb_insert_entry( i );
   833     }
   834 }
   836 static void mmu_invalidate_tlb()
   837 {
   838     int i;
   839     for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
   840         mmu_itlb[i].flags &= (~TLB_VALID);
   841     }
   842     if( IS_TLB_ENABLED() ) {
   843         for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   844             if( mmu_utlb[i].flags & TLB_VALID ) {
   845                 mmu_utlb_remove_entry( i );
   846             }
   847         }
   848     }
   849     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
   850         mmu_utlb[i].flags &= (~TLB_VALID);
   851     }
   852 }
   854 /******************************************************************************/
   855 /*                        MMU TLB address translation                         */
   856 /******************************************************************************/
   858 /**
   859  * Translate a 32-bit address into a UTLB entry number. Does not check for
   860  * page protection etc.
   861  * @return the entryNo if found, -1 if not found, and -2 for a multi-hit.
   862  */
   863 int mmu_utlb_entry_for_vpn( uint32_t vpn )
   864 {
   865     mmu_urc++;
   866     mem_region_fn_t fn = sh4_address_space[vpn>>12];
   867     if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
   868         return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
   869     } else if( fn >= &mmu_utlb_1k_pages[0].fn && fn < &mmu_utlb_1k_pages[UTLB_ENTRY_COUNT].fn ) {
   870         struct utlb_1k_entry *ent = (struct utlb_1k_entry *)fn;
   871         fn = ent->subpages[(vpn>>10)&0x03];
   872         if( fn >= &mmu_utlb_pages[0].fn && fn < &mmu_utlb_pages[UTLB_ENTRY_COUNT].fn ) {
   873             return ((struct utlb_page_entry *)fn) - &mmu_utlb_pages[0];
   874         }            
   875     } 
   876     if( fn == &mem_region_tlb_multihit ) {
   877         return -2;
   878     } else {
   879         return -1;
   880     }
   881 }
   884 /**
   885  * Perform the actual utlb lookup w/ asid matching.
   886  * Possible utcomes are:
   887  *   0..63 Single match - good, return entry found
   888  *   -1 No match - raise a tlb data miss exception
   889  *   -2 Multiple matches - raise a multi-hit exception (reset)
   890  * @param vpn virtual address to resolve
   891  * @return the resultant UTLB entry, or an error.
   892  */
   893 static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
   894 {
   895     int result = -1;
   896     unsigned int i;
   898     mmu_urc++;
   899     if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
   900         mmu_urc = 0;
   901     }
   903     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   904         if( (mmu_utlb[i].flags & TLB_VALID) &&
   905                 ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
   906                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   907             if( result != -1 ) {
   908                 return -2;
   909             }
   910             result = i;
   911         }
   912     }
   913     return result;
   914 }
   916 /**
   917  * Perform the actual utlb lookup matching on vpn only
   918  * Possible utcomes are:
   919  *   0..63 Single match - good, return entry found
   920  *   -1 No match - raise a tlb data miss exception
   921  *   -2 Multiple matches - raise a multi-hit exception (reset)
   922  * @param vpn virtual address to resolve
   923  * @return the resultant UTLB entry, or an error.
   924  */
   925 static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
   926 {
   927     int result = -1;
   928     unsigned int i;
   930     mmu_urc++;
   931     if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
   932         mmu_urc = 0;
   933     }
   935     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
   936         if( (mmu_utlb[i].flags & TLB_VALID) &&
   937                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
   938             if( result != -1 ) {
   939                 return -2;
   940             }
   941             result = i;
   942         }
   943     }
   945     return result;
   946 }
   948 /**
   949  * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
   950  * @return the number (0-3) of the replaced entry.
   951  */
   952 static int inline mmu_itlb_update_from_utlb( int entryNo )
   953 {
   954     int replace;
   955     /* Determine entry to replace based on lrui */
   956     if( (mmu_lrui & 0x38) == 0x38 ) {
   957         replace = 0;
   958         mmu_lrui = mmu_lrui & 0x07;
   959     } else if( (mmu_lrui & 0x26) == 0x06 ) {
   960         replace = 1;
   961         mmu_lrui = (mmu_lrui & 0x19) | 0x20;
   962     } else if( (mmu_lrui & 0x15) == 0x01 ) {
   963         replace = 2;
   964         mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
   965     } else { // Note - gets invalid entries too
   966         replace = 3;
   967         mmu_lrui = (mmu_lrui | 0x0B);
   968     }
   970     mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
   971     mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
   972     mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
   973     mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
   974     mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
   975     return replace;
   976 }
   978 /**
   979  * Perform the actual itlb lookup w/ asid protection
   980  * Possible utcomes are:
   981  *   0..63 Single match - good, return entry found
   982  *   -1 No match - raise a tlb data miss exception
   983  *   -2 Multiple matches - raise a multi-hit exception (reset)
   984  * @param vpn virtual address to resolve
   985  * @return the resultant ITLB entry, or an error.
   986  */
   987 static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
   988 {
   989     int result = -1;
   990     unsigned int i;
   992     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
   993         if( (mmu_itlb[i].flags & TLB_VALID) &&
   994                 ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
   995                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
   996             if( result != -1 ) {
   997                 return -2;
   998             }
   999             result = i;
  1003     if( result == -1 ) {
  1004         int utlbEntry = mmu_utlb_entry_for_vpn( vpn );
  1005         if( utlbEntry < 0 ) {
  1006             return utlbEntry;
  1007         } else {
  1008             return mmu_itlb_update_from_utlb( utlbEntry );
  1012     switch( result ) {
  1013     case 0: mmu_lrui = (mmu_lrui & 0x07); break;
  1014     case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
  1015     case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
  1016     case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
  1019     return result;
  1022 /**
  1023  * Perform the actual itlb lookup on vpn only
  1024  * Possible utcomes are:
  1025  *   0..63 Single match - good, return entry found
  1026  *   -1 No match - raise a tlb data miss exception
  1027  *   -2 Multiple matches - raise a multi-hit exception (reset)
  1028  * @param vpn virtual address to resolve
  1029  * @return the resultant ITLB entry, or an error.
  1030  */
  1031 static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
  1033     int result = -1;
  1034     unsigned int i;
  1036     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
  1037         if( (mmu_itlb[i].flags & TLB_VALID) &&
  1038                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
  1039             if( result != -1 ) {
  1040                 return -2;
  1042             result = i;
  1046     if( result == -1 ) {
  1047         int utlbEntry = mmu_utlb_lookup_vpn( vpn );
  1048         if( utlbEntry < 0 ) {
  1049             return utlbEntry;
  1050         } else {
  1051             return mmu_itlb_update_from_utlb( utlbEntry );
  1055     switch( result ) {
  1056     case 0: mmu_lrui = (mmu_lrui & 0x07); break;
  1057     case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
  1058     case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
  1059     case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
  1062     return result;
  1065 /**
  1066  * Update the icache for an untranslated address
  1067  */
  1068 static inline void mmu_update_icache_phys( sh4addr_t addr )
  1070     if( (addr & 0x1C000000) == 0x0C000000 ) {
  1071         /* Main ram */
  1072         sh4_icache.page_vma = addr & 0xFF000000;
  1073         sh4_icache.page_ppa = 0x0C000000;
  1074         sh4_icache.mask = 0xFF000000;
  1075         sh4_icache.page = dc_main_ram;
  1076     } else if( (addr & 0x1FE00000) == 0 ) {
  1077         /* BIOS ROM */
  1078         sh4_icache.page_vma = addr & 0xFFE00000;
  1079         sh4_icache.page_ppa = 0;
  1080         sh4_icache.mask = 0xFFE00000;
  1081         sh4_icache.page = dc_boot_rom;
  1082     } else {
  1083         /* not supported */
  1084         sh4_icache.page_vma = -1;
  1088 /**
  1089  * Update the sh4_icache structure to describe the page(s) containing the
  1090  * given vma. If the address does not reference a RAM/ROM region, the icache
  1091  * will be invalidated instead.
  1092  * If AT is on, this method will raise TLB exceptions normally
  1093  * (hence this method should only be used immediately prior to execution of
  1094  * code), and otherwise will set the icache according to the matching TLB entry.
  1095  * If AT is off, this method will set the entire referenced RAM/ROM region in
  1096  * the icache.
  1097  * @return TRUE if the update completed (successfully or otherwise), FALSE
  1098  * if an exception was raised.
  1099  */
  1100 gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
  1102     int entryNo;
  1103     if( IS_SH4_PRIVMODE()  ) {
  1104         if( addr & 0x80000000 ) {
  1105             if( addr < 0xC0000000 ) {
  1106                 /* P1, P2 and P4 regions are pass-through (no translation) */
  1107                 mmu_update_icache_phys(addr);
  1108                 return TRUE;
  1109             } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
  1110                 RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1111                 return FALSE;
  1115         uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1116         if( (mmucr & MMUCR_AT) == 0 ) {
  1117             mmu_update_icache_phys(addr);
  1118             return TRUE;
  1121         if( (mmucr & MMUCR_SV) == 0 )
  1122         	entryNo = mmu_itlb_lookup_vpn_asid( addr );
  1123         else
  1124         	entryNo = mmu_itlb_lookup_vpn( addr );
  1125     } else {
  1126         if( addr & 0x80000000 ) {
  1127             RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1128             return FALSE;
  1131         uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1132         if( (mmucr & MMUCR_AT) == 0 ) {
  1133             mmu_update_icache_phys(addr);
  1134             return TRUE;
  1137         entryNo = mmu_itlb_lookup_vpn_asid( addr );
  1139         if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
  1140             RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1141             return FALSE;
  1145     switch(entryNo) {
  1146     case -1:
  1147     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1148     return FALSE;
  1149     case -2:
  1150     RAISE_TLB_MULTIHIT_ERROR(addr);
  1151     return FALSE;
  1152     default:
  1153         sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
  1154         sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
  1155         if( sh4_icache.page == NULL ) {
  1156             sh4_icache.page_vma = -1;
  1157         } else {
  1158             sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
  1159             sh4_icache.mask = mmu_itlb[entryNo].mask;
  1161         return TRUE;
  1165 /**
  1166  * Translate address for disassembly purposes (ie performs an instruction
  1167  * lookup) - does not raise exceptions or modify any state, and ignores
  1168  * protection bits. Returns the translated address, or MMU_VMA_ERROR
  1169  * on translation failure.
  1170  */
  1171 sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
  1173     if( vma & 0x80000000 ) {
  1174         if( vma < 0xC0000000 ) {
  1175             /* P1, P2 and P4 regions are pass-through (no translation) */
  1176             return VMA_TO_EXT_ADDR(vma);
  1177         } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
  1178             /* Not translatable */
  1179             return MMU_VMA_ERROR;
  1183     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
  1184     if( (mmucr & MMUCR_AT) == 0 ) {
  1185         return VMA_TO_EXT_ADDR(vma);
  1188     int entryNo = mmu_itlb_lookup_vpn( vma );
  1189     if( entryNo == -2 ) {
  1190         entryNo = mmu_itlb_lookup_vpn_asid( vma );
  1192     if( entryNo < 0 ) {
  1193         return MMU_VMA_ERROR;
  1194     } else {
  1195         return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
  1196         (vma & (~mmu_itlb[entryNo].mask));
  1200 /********************** TLB Direct-Access Regions ***************************/
  1201 #ifdef HAVE_FRAME_ADDRESS
  1202 #define EXCEPTION_EXIT() do{ *(((void **)__builtin_frame_address(0))+1) = exc; } while(0)
  1203 #else
  1204 #define EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
  1205 #endif
  1208 #define ITLB_ENTRY(addr) ((addr>>7)&0x03)
  1210 int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
  1212     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1213     return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
  1216 void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
  1218     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1219     ent->vpn = val & 0xFFFFFC00;
  1220     ent->asid = val & 0x000000FF;
  1221     ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
  1224 int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
  1226     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1227     return (ent->ppn & 0x1FFFFC00) | ent->flags;
  1230 void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
  1232     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
  1233     ent->ppn = val & 0x1FFFFC00;
  1234     ent->flags = val & 0x00001DA;
  1235     ent->mask = get_tlb_size_mask(val);
  1236     if( ent->ppn >= 0x1C000000 )
  1237         ent->ppn |= 0xE0000000;
  1240 #define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
  1241 #define UTLB_ASSOC(addr) (addr&0x80)
  1242 #define UTLB_DATA2(addr) (addr&0x00800000)
  1244 int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
  1246     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1247     return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
  1248     ((ent->flags & TLB_DIRTY)<<7);
  1250 int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
  1252     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1253     if( UTLB_DATA2(addr) ) {
  1254         return ent->pcmcia;
  1255     } else {
  1256         return (ent->ppn&0x1FFFFC00) | ent->flags;
  1260 /**
  1261  * Find a UTLB entry for the associative TLB write - same as the normal
  1262  * lookup but ignores the valid bit.
  1263  */
  1264 static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
  1266     int result = -1;
  1267     unsigned int i;
  1268     for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
  1269         if( (mmu_utlb[i].flags & TLB_VALID) &&
  1270                 ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
  1271                 ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
  1272             if( result != -1 ) {
  1273                 fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
  1274                 return -2;
  1276             result = i;
  1279     return result;
  1282 /**
  1283  * Find a ITLB entry for the associative TLB write - same as the normal
  1284  * lookup but ignores the valid bit.
  1285  */
  1286 static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
  1288     int result = -1;
  1289     unsigned int i;
  1290     for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
  1291         if( (mmu_itlb[i].flags & TLB_VALID) &&
  1292                 ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
  1293                 ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
  1294             if( result != -1 ) {
  1295                 return -2;
  1297             result = i;
  1300     return result;
  1303 void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val, void *exc )
  1305     if( UTLB_ASSOC(addr) ) {
  1306         int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
  1307         if( utlb >= 0 ) {
  1308             struct utlb_entry *ent = &mmu_utlb[utlb];
  1309             uint32_t old_flags = ent->flags;
  1310             ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
  1311             ent->flags |= (val & TLB_VALID);
  1312             ent->flags |= ((val & 0x200)>>7);
  1313             if( IS_TLB_ENABLED() && ((old_flags^ent->flags) & (TLB_VALID|TLB_DIRTY)) != 0 ) {
  1314                 if( old_flags & TLB_VALID )
  1315                     mmu_utlb_remove_entry( utlb );
  1316                 if( ent->flags & TLB_VALID )
  1317                     mmu_utlb_insert_entry( utlb );
  1321         int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
  1322         if( itlb >= 0 ) {
  1323             struct itlb_entry *ent = &mmu_itlb[itlb];
  1324             ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
  1327         if( itlb == -2 || utlb == -2 ) {
  1328             RAISE_TLB_MULTIHIT_ERROR(addr); /* FIXME: should this only be raised if TLB is enabled? */
  1329             EXCEPTION_EXIT();
  1330             return;
  1332     } else {
  1333         struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1334         if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
  1335             mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
  1336         ent->vpn = (val & 0xFFFFFC00);
  1337         ent->asid = (val & 0xFF);
  1338         ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
  1339         ent->flags |= (val & TLB_VALID);
  1340         ent->flags |= ((val & 0x200)>>7);
  1341         if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
  1342             mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
  1346 void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
  1348     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
  1349     if( UTLB_DATA2(addr) ) {
  1350         ent->pcmcia = val & 0x0000000F;
  1351     } else {
  1352         if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
  1353             mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
  1354         ent->ppn = (val & 0x1FFFFC00);
  1355         ent->flags = (val & 0x000001FF);
  1356         ent->mask = get_tlb_size_mask(val);
  1357         if( IS_TLB_ENABLED() && ent->flags & TLB_VALID )
  1358             mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
  1362 struct mem_region_fn p4_region_itlb_addr = {
  1363         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1364         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1365         mmu_itlb_addr_read, mmu_itlb_addr_write,
  1366         unmapped_read_burst, unmapped_write_burst,
  1367         unmapped_prefetch, mmu_itlb_addr_read };
  1368 struct mem_region_fn p4_region_itlb_data = {
  1369         mmu_itlb_data_read, mmu_itlb_data_write,
  1370         mmu_itlb_data_read, mmu_itlb_data_write,
  1371         mmu_itlb_data_read, mmu_itlb_data_write,
  1372         unmapped_read_burst, unmapped_write_burst,
  1373         unmapped_prefetch, mmu_itlb_data_read };
  1374 struct mem_region_fn p4_region_utlb_addr = {
  1375         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1376         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1377         mmu_utlb_addr_read, (mem_write_fn_t)mmu_utlb_addr_write,
  1378         unmapped_read_burst, unmapped_write_burst,
  1379         unmapped_prefetch, mmu_utlb_addr_read };
  1380 struct mem_region_fn p4_region_utlb_data = {
  1381         mmu_utlb_data_read, mmu_utlb_data_write,
  1382         mmu_utlb_data_read, mmu_utlb_data_write,
  1383         mmu_utlb_data_read, mmu_utlb_data_write,
  1384         unmapped_read_burst, unmapped_write_burst,
  1385         unmapped_prefetch, mmu_utlb_data_read };
  1387 /********************** Error regions **************************/
  1389 static void FASTCALL address_error_read( sh4addr_t addr, void *exc ) 
  1391     RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1392     EXCEPTION_EXIT();
  1395 static void FASTCALL address_error_read_for_write( sh4addr_t addr, void *exc ) 
  1397     RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
  1398     EXCEPTION_EXIT();
  1401 static void FASTCALL address_error_read_burst( unsigned char *dest, sh4addr_t addr, void *exc ) 
  1403     RAISE_MEM_ERROR(EXC_DATA_ADDR_READ, addr);
  1404     EXCEPTION_EXIT();
  1407 static void FASTCALL address_error_write( sh4addr_t addr, uint32_t val, void *exc )
  1409     RAISE_MEM_ERROR(EXC_DATA_ADDR_WRITE, addr);
  1410     EXCEPTION_EXIT();
  1413 static void FASTCALL tlb_miss_read( sh4addr_t addr, void *exc )
  1415     mmu_urc++;
  1416     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1417     EXCEPTION_EXIT();
  1420 static void FASTCALL tlb_miss_read_for_write( sh4addr_t addr, void *exc )
  1422     mmu_urc++;
  1423     RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
  1424     EXCEPTION_EXIT();
  1427 static void FASTCALL tlb_miss_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1429     mmu_urc++;
  1430     RAISE_TLB_ERROR(EXC_TLB_MISS_READ, addr);
  1431     EXCEPTION_EXIT();
  1434 static void FASTCALL tlb_miss_write( sh4addr_t addr, uint32_t val, void *exc )
  1436     mmu_urc++;
  1437     RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, addr);
  1438     EXCEPTION_EXIT();
  1441 static int32_t FASTCALL tlb_protected_read( sh4addr_t addr, void *exc )
  1443     mmu_urc++;
  1444     RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1445     EXCEPTION_EXIT();
  1446     return 0; 
  1449 static int32_t FASTCALL tlb_protected_read_for_write( sh4addr_t addr, void *exc )
  1451     mmu_urc++;
  1452     RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
  1453     EXCEPTION_EXIT();
  1454     return 0;
  1457 static int32_t FASTCALL tlb_protected_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1459     mmu_urc++;
  1460     RAISE_MEM_ERROR(EXC_TLB_PROT_READ, addr);
  1461     EXCEPTION_EXIT();
  1462     return 0;
  1465 static void FASTCALL tlb_protected_write( sh4addr_t addr, uint32_t val, void *exc )
  1467     mmu_urc++;
  1468     RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, addr);
  1469     EXCEPTION_EXIT();
  1472 static void FASTCALL tlb_initial_write( sh4addr_t addr, uint32_t val, void *exc )
  1474     mmu_urc++;
  1475     RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
  1476     EXCEPTION_EXIT();
  1479 static int32_t FASTCALL tlb_initial_read_for_write( sh4addr_t addr, void *exc )
  1481     mmu_urc++;
  1482     RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, addr);
  1483     EXCEPTION_EXIT();
  1484     return 0;
  1487 static int32_t FASTCALL tlb_multi_hit_read( sh4addr_t addr, void *exc )
  1489     sh4_raise_tlb_multihit(addr);
  1490     EXCEPTION_EXIT();
  1491     return 0; 
  1494 static int32_t FASTCALL tlb_multi_hit_read_burst( unsigned char *dest, sh4addr_t addr, void *exc )
  1496     sh4_raise_tlb_multihit(addr);
  1497     EXCEPTION_EXIT();
  1498     return 0; 
  1500 static void FASTCALL tlb_multi_hit_write( sh4addr_t addr, uint32_t val, void *exc )
  1502     sh4_raise_tlb_multihit(addr);
  1503     EXCEPTION_EXIT();
  1506 /**
  1507  * Note: Per sec 4.6.4 of the SH7750 manual, SQ 
  1508  */
  1509 struct mem_region_fn mem_region_address_error = {
  1510         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1511         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1512         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1513         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1514         unmapped_prefetch, (mem_read_fn_t)address_error_read_for_write };
  1516 struct mem_region_fn mem_region_tlb_miss = {
  1517         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1518         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1519         (mem_read_fn_t)tlb_miss_read, (mem_write_fn_t)tlb_miss_write,
  1520         (mem_read_burst_fn_t)tlb_miss_read_burst, (mem_write_burst_fn_t)tlb_miss_write,
  1521         unmapped_prefetch, (mem_read_fn_t)tlb_miss_read_for_write };
  1523 struct mem_region_fn mem_region_tlb_protected = {
  1524         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1525         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1526         (mem_read_fn_t)tlb_protected_read, (mem_write_fn_t)tlb_protected_write,
  1527         (mem_read_burst_fn_t)tlb_protected_read_burst, (mem_write_burst_fn_t)tlb_protected_write,
  1528         unmapped_prefetch, (mem_read_fn_t)tlb_protected_read_for_write };
  1530 struct mem_region_fn mem_region_tlb_multihit = {
  1531         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1532         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1533         (mem_read_fn_t)tlb_multi_hit_read, (mem_write_fn_t)tlb_multi_hit_write,
  1534         (mem_read_burst_fn_t)tlb_multi_hit_read_burst, (mem_write_burst_fn_t)tlb_multi_hit_write,
  1535         (mem_prefetch_fn_t)tlb_multi_hit_read, (mem_read_fn_t)tlb_multi_hit_read };
  1538 /* Store-queue regions */
  1539 /* These are a bit of a pain - the first 8 fields are controlled by SQMD, while 
  1540  * the final (prefetch) is controlled by the actual TLB settings (plus SQMD in
  1541  * some cases), in contrast to the ordinary fields above.
  1543  * There is probably a simpler way to do this.
  1544  */
  1546 struct mem_region_fn p4_region_storequeue = { 
  1547         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1548         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1549         unmapped_read_long, unmapped_write_long,
  1550         unmapped_read_burst, unmapped_write_burst,
  1551         ccn_storequeue_prefetch, unmapped_read_long }; 
  1553 struct mem_region_fn p4_region_storequeue_miss = { 
  1554         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1555         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1556         unmapped_read_long, unmapped_write_long,
  1557         unmapped_read_burst, unmapped_write_burst,
  1558         (mem_prefetch_fn_t)tlb_miss_read, unmapped_read_long }; 
  1560 struct mem_region_fn p4_region_storequeue_multihit = { 
  1561         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1562         unmapped_read_long, unmapped_write_long, /* TESTME: Officially only long access is supported */
  1563         unmapped_read_long, unmapped_write_long,
  1564         unmapped_read_burst, unmapped_write_burst,
  1565         (mem_prefetch_fn_t)tlb_multi_hit_read, unmapped_read_long }; 
  1567 struct mem_region_fn p4_region_storequeue_protected = {
  1568         ccn_storequeue_read_long, ccn_storequeue_write_long,
  1569         unmapped_read_long, unmapped_write_long,
  1570         unmapped_read_long, unmapped_write_long,
  1571         unmapped_read_burst, unmapped_write_burst,
  1572         (mem_prefetch_fn_t)tlb_protected_read, unmapped_read_long };
  1574 struct mem_region_fn p4_region_storequeue_sqmd = {
  1575         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1576         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1577         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1578         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1579         (mem_prefetch_fn_t)address_error_read, (mem_read_fn_t)address_error_read_for_write };
  1581 struct mem_region_fn p4_region_storequeue_sqmd_miss = { 
  1582         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1583         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1584         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1585         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1586         (mem_prefetch_fn_t)tlb_miss_read, (mem_read_fn_t)address_error_read_for_write }; 
  1588 struct mem_region_fn p4_region_storequeue_sqmd_multihit = {
  1589         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1590         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1591         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1592         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1593         (mem_prefetch_fn_t)tlb_multi_hit_read, (mem_read_fn_t)address_error_read_for_write };
  1595 struct mem_region_fn p4_region_storequeue_sqmd_protected = {
  1596         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1597         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1598         (mem_read_fn_t)address_error_read, (mem_write_fn_t)address_error_write,
  1599         (mem_read_burst_fn_t)address_error_read_burst, (mem_write_burst_fn_t)address_error_write,
  1600         (mem_prefetch_fn_t)tlb_protected_read, (mem_read_fn_t)address_error_read_for_write };
.