Search
lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/asic.c
changeset 31:495e480360d7
prev25:fa2d21d57942
next35:21a4be098304
author nkeynes
date Sun Dec 25 08:24:11 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Finish adding header blocks to all files
view annotate diff log raw
     1 /**
     2  * $Id: asic.c,v 1.7 2005-12-25 08:24:07 nkeynes Exp $
     3  *
     4  * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
     5  * and DMA). 
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    19 #include <assert.h>
    20 #include "dream.h"
    21 #include "mem.h"
    22 #include "sh4/intc.h"
    23 #include "dreamcast.h"
    24 #include "modules.h"
    25 #include "maple/maple.h"
    26 #include "gdrom/ide.h"
    27 #include "asic.h"
    28 #define MMIO_IMPL
    29 #include "asic.h"
    30 /*
    31  * Open questions:
    32  *   1) Does changing the mask after event occurance result in the
    33  *      interrupt being delivered immediately?
    34  * TODO: Logic diagram of ASIC event/interrupt logic.
    35  *
    36  * ... don't even get me started on the "EXTDMA" page, about which, apparently,
    37  * practically nothing is publicly known...
    38  */
    40 struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
    41 					NULL, NULL, NULL };
    43 void asic_check_cleared_events( void );
    45 void asic_init( void )
    46 {
    47     register_io_region( &mmio_region_ASIC );
    48     register_io_region( &mmio_region_EXTDMA );
    49     mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
    50     asic_event( EVENT_GDROM_CMD );
    51 }
    53 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
    54 {
    55     switch( reg ) {
    56         case PIRQ0:
    57         case PIRQ1:
    58         case PIRQ2:
    59             /* Clear any interrupts */
    60             MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
    61 	    DEBUG( "ASIC Write %08X => %08X", val, reg );
    62 	    asic_check_cleared_events();
    63             break;
    64         case MAPLE_STATE:
    65             MMIO_WRITE( ASIC, reg, val );
    66             if( val & 1 ) {
    67                 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
    68 		WARN( "Maple request initiated at %08X, halting", maple_addr );
    69                 maple_handle_buffer( maple_addr );
    70                 MMIO_WRITE( ASIC, reg, 0 );
    71 //                dreamcast_stop();
    72             }
    73             break;
    74         default:
    75             MMIO_WRITE( ASIC, reg, val );
    76             WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
    77                   reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
    78     }
    79 }
    81 int32_t mmio_region_ASIC_read( uint32_t reg )
    82 {
    83     int32_t val;
    84     switch( reg ) {
    85         /*
    86         case 0x89C:
    87             sh4_stop();
    88             return 0x000000B;
    89         */     
    90         case PIRQ0:
    91         case PIRQ1:
    92         case PIRQ2:
    93             val = MMIO_READ(ASIC, reg);
    94 //            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
    95 //                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
    96             return val;            
    97         case G2STATUS:
    98             return 0; /* find out later if there's any cases we actually need to care about */
    99         default:
   100             val = MMIO_READ(ASIC, reg);
   101             WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
   102                   reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
   103             return val;
   104     }
   106 }
   108 void asic_event( int event )
   109 {
   110     int offset = ((event&0x60)>>3);
   111     int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
   113     if( result & MMIO_READ(ASIC, IRQA0 + offset) )
   114         intc_raise_interrupt( INT_IRQ13 );
   115     if( result & MMIO_READ(ASIC, IRQB0 + offset) )
   116         intc_raise_interrupt( INT_IRQ11 );
   117     if( result & MMIO_READ(ASIC, IRQC0 + offset) )
   118         intc_raise_interrupt( INT_IRQ9 );
   119 }
   121 void asic_check_cleared_events( )
   122 {
   123     int i, setA = 0, setB = 0, setC = 0;
   124     uint32_t bits;
   125     for( i=0; i<3; i++ ) {
   126 	bits = MMIO_READ( ASIC, PIRQ0 + i );
   127 	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
   128 	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
   129 	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
   130     }
   131     if( setA == 0 )
   132 	intc_clear_interrupt( INT_IRQ13 );
   133     if( setB == 0 )
   134 	intc_clear_interrupt( INT_IRQ11 );
   135     if( setC == 0 )
   136 	intc_clear_interrupt( INT_IRQ9 );
   137 }
   140 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
   141 {
   142     switch( reg ) {
   143         case IDEALTSTATUS: /* Device control */
   144             ide_write_control( val );
   145             break;
   146         case IDEDATA:
   147             ide_write_data_pio( val );
   148             break;
   149         case IDEFEAT:
   150             if( ide_can_write_regs() )
   151                 idereg.feature = (uint8_t)val;
   152             break;
   153         case IDECOUNT:
   154             if( ide_can_write_regs() )
   155                 idereg.count = (uint8_t)val;
   156             break;
   157         case IDELBA0:
   158             if( ide_can_write_regs() )
   159                 idereg.lba0 = (uint8_t)val;
   160             break;
   161         case IDELBA1:
   162             if( ide_can_write_regs() )
   163                 idereg.lba1 = (uint8_t)val;
   164             break;
   165         case IDELBA2:
   166             if( ide_can_write_regs() )
   167                 idereg.lba2 = (uint8_t)val;
   168             break;
   169         case IDEDEV:
   170             if( ide_can_write_regs() )
   171                 idereg.device = (uint8_t)val;
   172             break;
   173         case IDECMD:
   174             if( ide_can_write_regs() ) {
   175                 ide_clear_interrupt();
   176                 ide_write_command( (uint8_t)val );
   177             }
   178             break;
   180         default:
   181             MMIO_WRITE( EXTDMA, reg, val );
   182     }
   183 }
   185 MMIO_REGION_READ_FN( EXTDMA, reg )
   186 {
   187     switch( reg ) {
   188         case IDEALTSTATUS: return idereg.status;
   189         case IDEDATA: return ide_read_data_pio( );
   190         case IDEFEAT: return idereg.error;
   191         case IDECOUNT:return idereg.count;
   192         case IDELBA0: return idereg.disc;
   193         case IDELBA1: return idereg.lba1;
   194         case IDELBA2: return idereg.lba2;
   195         case IDEDEV: return idereg.device;
   196         case IDECMD:
   197             ide_clear_interrupt();
   198             return idereg.status;
   199         default:
   200             return MMIO_READ( EXTDMA, reg );
   201     }
   202 }
.