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lxdream.org :: lxdream/src/sh4/intc.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/intc.c
changeset 31:495e480360d7
prev20:3ffb66aa25c7
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author nkeynes
date Sun Dec 25 08:24:11 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Finish adding header blocks to all files
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     1 /**
     2  * $Id: intc.c,v 1.4 2005-12-25 08:24:11 nkeynes Exp $
     3  *
     4  * SH4 onboard interrupt controller (INTC) implementation
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    19 #include <assert.h>
    20 #include "sh4mmio.h"
    21 #include "sh4core.h"
    22 #include "intc.h"
    24 int priorities[12] = {0,0,0,0,0,0,0,0,0,0,0,0};
    26 struct intc_sources_t {
    27     char *name;
    28     uint32_t code;
    29     int priority;
    30 };
    32 #define PRIORITY(which) intc_sources[which].priority
    33 #define INTCODE(which) intc_sources[which].code
    35 static struct intc_sources_t intc_sources[] = {
    36     { "IRQ0", 0x200, 15 }, { "IRQ1", 0x220, 14 }, { "IRQ2", 0x240, 13 },
    37     { "IRQ3", 0x260, 12 }, { "IRQ4", 0x280, 11 }, { "IRQ5", 0x2A0, 10 },
    38     { "IRQ6", 0x2C0, 9 },  { "IRQ7", 0x2E0, 8 },  { "IRQ8", 0x300, 7 },
    39     { "IRQ9", 0x320, 6 },  { "IRQ10",0x340, 5 },  { "IRQ11",0x360, 4 },
    40     { "IRQ12",0x380, 3 },  { "IRQ13",0x3A0, 2 },  { "IRQ14",0x3C0, 1 },
    41     { "NMI", 0x1C0, 16 },  { "H-UDI",0x600, 0 },  { "GPIOI",0x620, 0 },
    42     { "DMTE0",0x640, 0 },  { "DMTE1",0x660, 0 },  { "DMTE2",0x680, 0 },
    43     { "DMTE3",0x6A0, 0 },  { "DMTAE",0x6C0, 0 },  { "TUNI0",0x400, 0 },
    44     { "TUNI1",0x420, 0 },  { "TUNI2",0x440, 0 },  { "TICPI2",0x460, 0 },
    45     { "RTC_ATI",0x480, 0 },{ "RTC_PRI",0x4A0, 0 },{ "RTC_CUI",0x4C0, 0 },
    46     { "SCI_ERI",0x4E0, 0 },{ "SCI_RXI",0x500, 0 },{ "SCI_TXI",0x520, 0 },
    47     { "SCI_TEI",0x540, 0 },
    48     { "SCIF_ERI",0x700, 0 },{ "SCIF_RXI",0x720, 0 },{ "SCIF_BRI",0x740, 0 },
    49     { "SCIF_TXI",0x760, 0 },
    50     { "WDT_ITI",0x560, 0 },{ "RCMI",0x580, 0 },   { "ROVI",0x5A0, 0 } };
    52 int intc_pending[INT_NUM_SOURCES];
    53 int intc_num_pending = 0;
    55 void mmio_region_INTC_write( uint32_t reg, uint32_t val )
    56 {
    57     /* Well it saves having to use an intermediate table... */
    58     switch( reg ) {
    59         case ICR: /* care about this later */
    60             break;
    61         case IPRA:
    62             PRIORITY(INT_TMU_TUNI0) = (val>>12)&0x000F;
    63             PRIORITY(INT_TMU_TUNI1) = (val>>8)&0x000F;
    64             PRIORITY(INT_TMU_TUNI2) =
    65                 PRIORITY(INT_TMU_TICPI2) = (val>>4)&0x000F;
    66             PRIORITY(INT_RTC_ATI) =
    67                 PRIORITY(INT_RTC_PRI) =
    68                 PRIORITY(INT_RTC_CUI) = val&0x000F;
    69             break;
    70         case IPRB:
    71             PRIORITY(INT_WDT_ITI) = (val>>12)&0x000F;
    72             PRIORITY(INT_REF_RCMI) =
    73                 PRIORITY(INT_REF_ROVI) = (val>>8)&0x000F;
    74             PRIORITY(INT_SCI_ERI) =
    75                 PRIORITY(INT_SCI_RXI) =
    76                 PRIORITY(INT_SCI_TXI) =
    77                 PRIORITY(INT_SCI_TEI) = (val>>4)&0x000F;
    78             /* Bits 0-3 reserved */
    79             break;
    80         case IPRC:
    81             PRIORITY(INT_GPIO) = (val>>12)&0x000F;
    82             PRIORITY(INT_DMA_DMTE0) =
    83                 PRIORITY(INT_DMA_DMTE1) =
    84                 PRIORITY(INT_DMA_DMTE2) =
    85                 PRIORITY(INT_DMA_DMTE3) =
    86                 PRIORITY(INT_DMA_DMAE) = (val>>8)&0x000F;
    87             PRIORITY(INT_SCIF_ERI) =
    88                 PRIORITY(INT_SCIF_RXI) =
    89                 PRIORITY(INT_SCIF_BRI) =
    90                 PRIORITY(INT_SCIF_TXI) = (val>>4)&0x000F;
    91             PRIORITY(INT_HUDI) = val&0x000F;
    92             break;
    93     }
    94     MMIO_WRITE( INTC, reg, val );
    95 }
    97 int32_t mmio_region_INTC_read( uint32_t reg )
    98 {
    99     return MMIO_READ( INTC, reg );
   100 }
   102 /* We basically maintain a priority queue here, raise_interrupt adds an entry,
   103  * accept_interrupt takes it off. At the moment this is does as a simple
   104  * ordered array, on the basis that in practice there's unlikely to be more
   105  * than one at a time. There are lots of ways to optimize this if it turns out
   106  * to be necessary, but I'd doubt it will be...
   107  */
   109 void intc_raise_interrupt( int which )
   110 {
   111     int i, j, pri;
   113     pri = PRIORITY(which);
   114     if( pri == 0 ) return; /* masked off */
   116     for( i=0; i<intc_num_pending; i++ ) {
   117         if( intc_pending[i] == which ) return; /* Don't queue more than once */
   118         if( PRIORITY(intc_pending[i]) > pri ||
   119             (PRIORITY(intc_pending[i]) == pri &&
   120              intc_pending[i] < which))
   121             break;
   122     }
   123     /* i == insertion point */
   124     for( j=intc_num_pending; j > i; j-- )
   125         intc_pending[j] = intc_pending[j-1];
   126     intc_pending[i] = which;
   128     if( i == intc_num_pending && (sh4r.sr&SR_BL)==0 && SH4_INTMASK() < pri )
   129         sh4r.int_pending = 1;
   131     intc_num_pending++;
   132 }
   134 void intc_clear_interrupt( int which )
   135 {
   136     int i;
   137     for( i=intc_num_pending-1; i>=0; i-- ) {
   138 	if( intc_pending[i] == which ) {
   139 	    /* Shift array contents down */
   140 	    while( i < intc_num_pending-1 ) {
   141 		intc_pending[i] = intc_pending[++i];
   142 	    }
   143 	    intc_num_pending--;
   144 	    if( intc_num_pending == 0 )
   145 		sh4r.int_pending = 0;
   146 	    else
   147 		sh4r.int_pending = PRIORITY(intc_pending[intc_num_pending-1]);
   148 	    break;
   149 	}
   150     }
   152 }
   154 uint32_t intc_accept_interrupt( void )
   155 {
   156     assert(intc_num_pending > 0);
   157     return INTCODE(intc_pending[intc_num_pending-1]);
   158     /*
   159     intc_num_pending--;
   160     if( intc_num_pending > 0 )
   161         sh4r.int_pending = PRIORITY(intc_pending[intc_num_pending-1]);
   162     else
   163         sh4r.int_pending = 0;
   164     return INTCODE(intc_pending[intc_num_pending]);
   165     */
   166 }
   168 void intc_mask_changed( void )
   169 {   
   170     if( intc_num_pending > 0 && (sh4r.sr&SR_BL)==0 &&
   171         SH4_INTMASK() < PRIORITY(intc_pending[intc_num_pending-1]) )
   172         sh4r.int_pending = 1;
   173     else sh4r.int_pending = 0;
   174 }
   177 char *intc_get_interrupt_name( int code )
   178 {
   179     return intc_sources[code].name;
   180 }
   182 void intc_reset( void )
   183 {
   184     intc_num_pending = 0;
   185     sh4r.int_pending = 0;
   186 }
.