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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 369:4b4223e7d720
prev367:9c52dcbad3fb
next374:8f80a795513e
author nkeynes
date Sat Sep 08 03:12:21 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Move the store queue operation to a function in sh4mem.c
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     1 /**
     2  * $Id: sh4core.c,v 1.43 2007-09-08 03:11:53 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 #define EXV_EXCEPTION    0x100  /* General exception vector */
    38 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    39 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    41 /********************** SH4 Module Definition ****************************/
    43 void sh4_init( void );
    44 void sh4_reset( void );
    45 uint32_t sh4_run_slice( uint32_t );
    46 void sh4_start( void );
    47 void sh4_stop( void );
    48 void sh4_save_state( FILE *f );
    49 int sh4_load_state( FILE *f );
    50 void sh4_accept_interrupt( void );
    52 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    53 				       NULL, sh4_run_slice, sh4_stop,
    54 				       sh4_save_state, sh4_load_state };
    56 struct sh4_registers sh4r;
    58 void sh4_init(void)
    59 {
    60     register_io_regions( mmio_list_sh4mmio );
    61     MMU_init();
    62     sh4_reset();
    63 }
    65 void sh4_reset(void)
    66 {
    67     /* zero everything out, for the sake of having a consistent state. */
    68     memset( &sh4r, 0, sizeof(sh4r) );
    70     /* Resume running if we were halted */
    71     sh4r.sh4_state = SH4_STATE_RUNNING;
    73     sh4r.pc    = 0xA0000000;
    74     sh4r.new_pc= 0xA0000002;
    75     sh4r.vbr   = 0x00000000;
    76     sh4r.fpscr = 0x00040001;
    77     sh4r.sr    = 0x700000F0;
    79     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    80     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    82     /* Peripheral modules */
    83     CPG_reset();
    84     INTC_reset();
    85     MMU_reset();
    86     TMU_reset();
    87     SCIF_reset();
    88 }
    90 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    91 static int sh4_breakpoint_count = 0;
    92 static uint16_t *sh4_icache = NULL;
    93 static uint32_t sh4_icache_addr = 0;
    95 void sh4_set_breakpoint( uint32_t pc, int type )
    96 {
    97     sh4_breakpoints[sh4_breakpoint_count].address = pc;
    98     sh4_breakpoints[sh4_breakpoint_count].type = type;
    99     sh4_breakpoint_count++;
   100 }
   102 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   103 {
   104     int i;
   106     for( i=0; i<sh4_breakpoint_count; i++ ) {
   107 	if( sh4_breakpoints[i].address == pc && 
   108 	    sh4_breakpoints[i].type == type ) {
   109 	    while( ++i < sh4_breakpoint_count ) {
   110 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   111 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   112 	    }
   113 	    sh4_breakpoint_count--;
   114 	    return TRUE;
   115 	}
   116     }
   117     return FALSE;
   118 }
   120 int sh4_get_breakpoint( uint32_t pc )
   121 {
   122     int i;
   123     for( i=0; i<sh4_breakpoint_count; i++ ) {
   124 	if( sh4_breakpoints[i].address == pc )
   125 	    return sh4_breakpoints[i].type;
   126     }
   127     return 0;
   128 }
   130 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   131 {
   132     int i;
   133     sh4r.slice_cycle = 0;
   135     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   136 	if( sh4r.event_pending < nanosecs ) {
   137 	    sh4r.sh4_state = SH4_STATE_RUNNING;
   138 	    sh4r.slice_cycle = sh4r.event_pending;
   139 	}
   140     }
   142     if( sh4_breakpoint_count == 0 ) {
   143 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   144 	    if( SH4_EVENT_PENDING() ) {
   145 		if( sh4r.event_types & PENDING_EVENT ) {
   146 		    event_execute();
   147 		}
   148 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   149 		if( sh4r.event_types & PENDING_IRQ ) {
   150 		    sh4_accept_interrupt();
   151 		}
   152 	    }
   153 	    if( !sh4_execute_instruction() ) {
   154 		break;
   155 	    }
   156 	}
   157     } else {
   158 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
   159 	    if( SH4_EVENT_PENDING() ) {
   160 		if( sh4r.event_types & PENDING_EVENT ) {
   161 		    event_execute();
   162 		}
   163 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
   164 		if( sh4r.event_types & PENDING_IRQ ) {
   165 		    sh4_accept_interrupt();
   166 		}
   167 	    }
   169 	    if( !sh4_execute_instruction() )
   170 		break;
   171 #ifdef ENABLE_DEBUG_MODE
   172 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
   173 		if( sh4_breakpoints[i].address == sh4r.pc ) {
   174 		    break;
   175 		}
   176 	    }
   177 	    if( i != sh4_breakpoint_count ) {
   178 		dreamcast_stop();
   179 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
   180 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   181 		break;
   182 	    }
   183 #endif	
   184 	}
   185     }
   187     /* If we aborted early, but the cpu is still technically running,
   188      * we're doing a hard abort - cut the timeslice back to what we
   189      * actually executed
   190      */
   191     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   192 	nanosecs = sh4r.slice_cycle;
   193     }
   194     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   195 	TMU_run_slice( nanosecs );
   196 	SCIF_run_slice( nanosecs );
   197     }
   198     return nanosecs;
   199 }
   201 void sh4_stop(void)
   202 {
   204 }
   206 void sh4_save_state( FILE *f )
   207 {
   208     fwrite( &sh4r, sizeof(sh4r), 1, f );
   209     MMU_save_state( f );
   210     INTC_save_state( f );
   211     TMU_save_state( f );
   212     SCIF_save_state( f );
   213 }
   215 int sh4_load_state( FILE * f )
   216 {
   217     fread( &sh4r, sizeof(sh4r), 1, f );
   218     MMU_load_state( f );
   219     INTC_load_state( f );
   220     TMU_load_state( f );
   221     return SCIF_load_state( f );
   222 }
   224 /********************** SH4 emulation core  ****************************/
   226 void sh4_set_pc( int pc )
   227 {
   228     sh4r.pc = pc;
   229     sh4r.new_pc = pc+2;
   230 }
   232 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   233 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   235 #if(SH4_CALLTRACE == 1)
   236 #define MAX_CALLSTACK 32
   237 static struct call_stack {
   238     sh4addr_t call_addr;
   239     sh4addr_t target_addr;
   240     sh4addr_t stack_pointer;
   241 } call_stack[MAX_CALLSTACK];
   243 static int call_stack_depth = 0;
   244 int sh4_call_trace_on = 0;
   246 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   247 {
   248     if( call_stack_depth < MAX_CALLSTACK ) {
   249 	call_stack[call_stack_depth].call_addr = source;
   250 	call_stack[call_stack_depth].target_addr = dest;
   251 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   252     }
   253     call_stack_depth++;
   254 }
   256 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   257 {
   258     if( call_stack_depth > 0 ) {
   259 	call_stack_depth--;
   260     }
   261 }
   263 void fprint_stack_trace( FILE *f )
   264 {
   265     int i = call_stack_depth -1;
   266     if( i >= MAX_CALLSTACK )
   267 	i = MAX_CALLSTACK - 1;
   268     for( ; i >= 0; i-- ) {
   269 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   270 		 (call_stack_depth - i), call_stack[i].call_addr,
   271 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   272     }
   273 }
   275 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   276 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   277 #else
   278 #define TRACE_CALL( dest, rts ) 
   279 #define TRACE_RETURN( source, dest )
   280 #endif
   282 #define RAISE( x, v ) do{			\
   283     if( sh4r.vbr == 0 ) { \
   284         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   285         dreamcast_stop(); return FALSE;	\
   286     } else { \
   287         sh4r.spc = sh4r.pc;	\
   288         sh4r.ssr = sh4_read_sr(); \
   289         sh4r.sgr = sh4r.r[15]; \
   290         MMIO_WRITE(MMU,EXPEVT,x); \
   291         sh4r.pc = sh4r.vbr + v; \
   292         sh4r.new_pc = sh4r.pc + 2; \
   293         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   294 	if( sh4r.in_delay_slot ) { \
   295 	    sh4r.in_delay_slot = 0; \
   296 	    sh4r.spc -= 2; \
   297 	} \
   298     } \
   299     return TRUE; } while(0)
   301 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   302 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   303 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   304 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   305 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   306 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   308 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   310 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   311 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   313 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   314 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   315 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   316 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   317 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   319 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   320 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   321 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   323 static void sh4_switch_banks( )
   324 {
   325     uint32_t tmp[8];
   327     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   328     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   329     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   330 }
   332 static void sh4_load_sr( uint32_t newval )
   333 {
   334     if( (newval ^ sh4r.sr) & SR_RB )
   335         sh4_switch_banks();
   336     sh4r.sr = newval;
   337     sh4r.t = (newval&SR_T) ? 1 : 0;
   338     sh4r.s = (newval&SR_S) ? 1 : 0;
   339     sh4r.m = (newval&SR_M) ? 1 : 0;
   340     sh4r.q = (newval&SR_Q) ? 1 : 0;
   341     intc_mask_changed();
   342 }
   344 static void sh4_write_float( uint32_t addr, int reg )
   345 {
   346     if( IS_FPU_DOUBLESIZE() ) {
   347 	if( reg & 1 ) {
   348 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   349 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   350 	} else {
   351 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   352 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   353 	}
   354     } else {
   355 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   356     }
   357 }
   359 static void sh4_read_float( uint32_t addr, int reg )
   360 {
   361     if( IS_FPU_DOUBLESIZE() ) {
   362 	if( reg & 1 ) {
   363 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   364 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   365 	} else {
   366 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   367 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   368 	}
   369     } else {
   370 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   371     }
   372 }
   374 static uint32_t sh4_read_sr( void )
   375 {
   376     /* synchronize sh4r.sr with the various bitflags */
   377     sh4r.sr &= SR_MQSTMASK;
   378     if( sh4r.t ) sh4r.sr |= SR_T;
   379     if( sh4r.s ) sh4r.sr |= SR_S;
   380     if( sh4r.m ) sh4r.sr |= SR_M;
   381     if( sh4r.q ) sh4r.sr |= SR_Q;
   382     return sh4r.sr;
   383 }
   385 /**
   386  * Raise a general CPU exception for the specified exception code.
   387  * (NOT for TRAPA or TLB exceptions)
   388  */
   389 gboolean sh4_raise_exception( int code )
   390 {
   391     RAISE( code, EXV_EXCEPTION );
   392 }
   394 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   395     if( sh4r.in_delay_slot ) {
   396 	return sh4_raise_exception(slot_code);
   397     } else {
   398 	return sh4_raise_exception(normal_code);
   399     }
   400 }
   402 gboolean sh4_raise_tlb_exception( int code )
   403 {
   404     RAISE( code, EXV_TLBMISS );
   405 }
   407 void sh4_accept_interrupt( void )
   408 {
   409     uint32_t code = intc_accept_interrupt();
   410     sh4r.ssr = sh4_read_sr();
   411     sh4r.spc = sh4r.pc;
   412     sh4r.sgr = sh4r.r[15];
   413     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   414     MMIO_WRITE( MMU, INTEVT, code );
   415     sh4r.pc = sh4r.vbr + 0x600;
   416     sh4r.new_pc = sh4r.pc + 2;
   417     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   418 }
   420 gboolean sh4_execute_instruction( void )
   421 {
   422     uint32_t pc;
   423     unsigned short ir;
   424     uint32_t tmp;
   425     float ftmp;
   426     double dtmp;
   428 #define R0 sh4r.r[0]
   429     pc = sh4r.pc;
   430     if( pc > 0xFFFFFF00 ) {
   431 	/* SYSCALL Magic */
   432 	syscall_invoke( pc );
   433 	sh4r.in_delay_slot = 0;
   434 	pc = sh4r.pc = sh4r.pr;
   435 	sh4r.new_pc = sh4r.pc + 2;
   436     }
   437     CHECKRALIGN16(pc);
   439     /* Read instruction */
   440     uint32_t pageaddr = pc >> 12;
   441     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   442 	ir = sh4_icache[(pc&0xFFF)>>1];
   443     } else {
   444 	sh4_icache = (uint16_t *)mem_get_page(pc);
   445 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   446 	    /* If someone's actually been so daft as to try to execute out of an IO
   447 	     * region, fallback on the full-blown memory read
   448 	     */
   449 	    sh4_icache = NULL;
   450 	    ir = MEM_READ_WORD(pc);
   451 	} else {
   452 	    sh4_icache_addr = pageaddr;
   453 	    ir = sh4_icache[(pc&0xFFF)>>1];
   454 	}
   455     }
   456         switch( (ir&0xF000) >> 12 ) {
   457             case 0x0:
   458                 switch( ir&0xF ) {
   459                     case 0x2:
   460                         switch( (ir&0x80) >> 7 ) {
   461                             case 0x0:
   462                                 switch( (ir&0x70) >> 4 ) {
   463                                     case 0x0:
   464                                         { /* STC SR, Rn */
   465                                         uint32_t Rn = ((ir>>8)&0xF); 
   466                                         CHECKPRIV();
   467                                         sh4r.r[Rn] = sh4_read_sr();
   468                                         }
   469                                         break;
   470                                     case 0x1:
   471                                         { /* STC GBR, Rn */
   472                                         uint32_t Rn = ((ir>>8)&0xF); 
   473                                         CHECKPRIV();
   474                                         sh4r.r[Rn] = sh4r.gbr;
   475                                         }
   476                                         break;
   477                                     case 0x2:
   478                                         { /* STC VBR, Rn */
   479                                         uint32_t Rn = ((ir>>8)&0xF); 
   480                                         CHECKPRIV();
   481                                         sh4r.r[Rn] = sh4r.vbr;
   482                                         }
   483                                         break;
   484                                     case 0x3:
   485                                         { /* STC SSR, Rn */
   486                                         uint32_t Rn = ((ir>>8)&0xF); 
   487                                         CHECKPRIV();
   488                                         sh4r.r[Rn] = sh4r.ssr;
   489                                         }
   490                                         break;
   491                                     case 0x4:
   492                                         { /* STC SPC, Rn */
   493                                         uint32_t Rn = ((ir>>8)&0xF); 
   494                                         CHECKPRIV();
   495                                         sh4r.r[Rn] = sh4r.spc;
   496                                         }
   497                                         break;
   498                                     default:
   499                                         UNDEF();
   500                                         break;
   501                                 }
   502                                 break;
   503                             case 0x1:
   504                                 { /* STC Rm_BANK, Rn */
   505                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   506                                 CHECKPRIV();
   507                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   508                                 }
   509                                 break;
   510                         }
   511                         break;
   512                     case 0x3:
   513                         switch( (ir&0xF0) >> 4 ) {
   514                             case 0x0:
   515                                 { /* BSRF Rn */
   516                                 uint32_t Rn = ((ir>>8)&0xF); 
   517                                 CHECKSLOTILLEGAL();
   518                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   519                                 sh4r.in_delay_slot = 1;
   520                                 sh4r.pr = sh4r.pc + 4;
   521                                 sh4r.pc = sh4r.new_pc;
   522                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   523                                 TRACE_CALL( pc, sh4r.new_pc );
   524                                 return TRUE;
   525                                 }
   526                                 break;
   527                             case 0x2:
   528                                 { /* BRAF Rn */
   529                                 uint32_t Rn = ((ir>>8)&0xF); 
   530                                 CHECKSLOTILLEGAL();
   531                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   532                                 sh4r.in_delay_slot = 1;
   533                                 sh4r.pc = sh4r.new_pc;
   534                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   535                                 return TRUE;
   536                                 }
   537                                 break;
   538                             case 0x8:
   539                                 { /* PREF @Rn */
   540                                 uint32_t Rn = ((ir>>8)&0xF); 
   541                                 tmp = sh4r.r[Rn];
   542                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {
   543                            	 sh4_flush_store_queue(tmp);
   544                                 }
   545                                 }
   546                                 break;
   547                             case 0x9:
   548                                 { /* OCBI @Rn */
   549                                 uint32_t Rn = ((ir>>8)&0xF); 
   550                                 }
   551                                 break;
   552                             case 0xA:
   553                                 { /* OCBP @Rn */
   554                                 uint32_t Rn = ((ir>>8)&0xF); 
   555                                 }
   556                                 break;
   557                             case 0xB:
   558                                 { /* OCBWB @Rn */
   559                                 uint32_t Rn = ((ir>>8)&0xF); 
   560                                 }
   561                                 break;
   562                             case 0xC:
   563                                 { /* MOVCA.L R0, @Rn */
   564                                 uint32_t Rn = ((ir>>8)&0xF); 
   565                                 tmp = sh4r.r[Rn];
   566                                 CHECKWALIGN32(tmp);
   567                                 MEM_WRITE_LONG( tmp, R0 );
   568                                 }
   569                                 break;
   570                             default:
   571                                 UNDEF();
   572                                 break;
   573                         }
   574                         break;
   575                     case 0x4:
   576                         { /* MOV.B Rm, @(R0, Rn) */
   577                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   578                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   579                         }
   580                         break;
   581                     case 0x5:
   582                         { /* MOV.W Rm, @(R0, Rn) */
   583                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   584                         CHECKWALIGN16( R0 + sh4r.r[Rn] );
   585                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   586                         }
   587                         break;
   588                     case 0x6:
   589                         { /* MOV.L Rm, @(R0, Rn) */
   590                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   591                         CHECKWALIGN32( R0 + sh4r.r[Rn] );
   592                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   593                         }
   594                         break;
   595                     case 0x7:
   596                         { /* MUL.L Rm, Rn */
   597                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   598                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   599                                                (sh4r.r[Rm] * sh4r.r[Rn]);
   600                         }
   601                         break;
   602                     case 0x8:
   603                         switch( (ir&0xFF0) >> 4 ) {
   604                             case 0x0:
   605                                 { /* CLRT */
   606                                 sh4r.t = 0;
   607                                 }
   608                                 break;
   609                             case 0x1:
   610                                 { /* SETT */
   611                                 sh4r.t = 1;
   612                                 }
   613                                 break;
   614                             case 0x2:
   615                                 { /* CLRMAC */
   616                                 sh4r.mac = 0;
   617                                 }
   618                                 break;
   619                             case 0x3:
   620                                 { /* LDTLB */
   621                                 /* TODO */
   622                                 }
   623                                 break;
   624                             case 0x4:
   625                                 { /* CLRS */
   626                                 sh4r.s = 0;
   627                                 }
   628                                 break;
   629                             case 0x5:
   630                                 { /* SETS */
   631                                 sh4r.s = 1;
   632                                 }
   633                                 break;
   634                             default:
   635                                 UNDEF();
   636                                 break;
   637                         }
   638                         break;
   639                     case 0x9:
   640                         switch( (ir&0xF0) >> 4 ) {
   641                             case 0x0:
   642                                 { /* NOP */
   643                                 /* NOP */
   644                                 }
   645                                 break;
   646                             case 0x1:
   647                                 { /* DIV0U */
   648                                 sh4r.m = sh4r.q = sh4r.t = 0;
   649                                 }
   650                                 break;
   651                             case 0x2:
   652                                 { /* MOVT Rn */
   653                                 uint32_t Rn = ((ir>>8)&0xF); 
   654                                 sh4r.r[Rn] = sh4r.t;
   655                                 }
   656                                 break;
   657                             default:
   658                                 UNDEF();
   659                                 break;
   660                         }
   661                         break;
   662                     case 0xA:
   663                         switch( (ir&0xF0) >> 4 ) {
   664                             case 0x0:
   665                                 { /* STS MACH, Rn */
   666                                 uint32_t Rn = ((ir>>8)&0xF); 
   667                                 sh4r.r[Rn] = (sh4r.mac>>32);
   668                                 }
   669                                 break;
   670                             case 0x1:
   671                                 { /* STS MACL, Rn */
   672                                 uint32_t Rn = ((ir>>8)&0xF); 
   673                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;
   674                                 }
   675                                 break;
   676                             case 0x2:
   677                                 { /* STS PR, Rn */
   678                                 uint32_t Rn = ((ir>>8)&0xF); 
   679                                 sh4r.r[Rn] = sh4r.pr;
   680                                 }
   681                                 break;
   682                             case 0x3:
   683                                 { /* STC SGR, Rn */
   684                                 uint32_t Rn = ((ir>>8)&0xF); 
   685                                 CHECKPRIV();
   686                                 sh4r.r[Rn] = sh4r.sgr;
   687                                 }
   688                                 break;
   689                             case 0x5:
   690                                 { /* STS FPUL, Rn */
   691                                 uint32_t Rn = ((ir>>8)&0xF); 
   692                                 sh4r.r[Rn] = sh4r.fpul;
   693                                 }
   694                                 break;
   695                             case 0x6:
   696                                 { /* STS FPSCR, Rn */
   697                                 uint32_t Rn = ((ir>>8)&0xF); 
   698                                 sh4r.r[Rn] = sh4r.fpscr;
   699                                 }
   700                                 break;
   701                             case 0xF:
   702                                 { /* STC DBR, Rn */
   703                                 uint32_t Rn = ((ir>>8)&0xF); 
   704                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
   705                                 }
   706                                 break;
   707                             default:
   708                                 UNDEF();
   709                                 break;
   710                         }
   711                         break;
   712                     case 0xB:
   713                         switch( (ir&0xFF0) >> 4 ) {
   714                             case 0x0:
   715                                 { /* RTS */
   716                                 CHECKSLOTILLEGAL();
   717                                 CHECKDEST( sh4r.pr );
   718                                 sh4r.in_delay_slot = 1;
   719                                 sh4r.pc = sh4r.new_pc;
   720                                 sh4r.new_pc = sh4r.pr;
   721                                 TRACE_RETURN( pc, sh4r.new_pc );
   722                                 return TRUE;
   723                                 }
   724                                 break;
   725                             case 0x1:
   726                                 { /* SLEEP */
   727                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   728                             	sh4r.sh4_state = SH4_STATE_STANDBY;
   729                                 } else {
   730                             	sh4r.sh4_state = SH4_STATE_SLEEP;
   731                                 }
   732                                 return FALSE; /* Halt CPU */
   733                                 }
   734                                 break;
   735                             case 0x2:
   736                                 { /* RTE */
   737                                 CHECKPRIV();
   738                                 CHECKDEST( sh4r.spc );
   739                                 CHECKSLOTILLEGAL();
   740                                 sh4r.in_delay_slot = 1;
   741                                 sh4r.pc = sh4r.new_pc;
   742                                 sh4r.new_pc = sh4r.spc;
   743                                 sh4_load_sr( sh4r.ssr );
   744                                 return TRUE;
   745                                 }
   746                                 break;
   747                             default:
   748                                 UNDEF();
   749                                 break;
   750                         }
   751                         break;
   752                     case 0xC:
   753                         { /* MOV.B @(R0, Rm), Rn */
   754                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   755                         sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );
   756                         }
   757                         break;
   758                     case 0xD:
   759                         { /* MOV.W @(R0, Rm), Rn */
   760                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   761                         CHECKRALIGN16( R0 + sh4r.r[Rm] );
   762                                            sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
   763                         }
   764                         break;
   765                     case 0xE:
   766                         { /* MOV.L @(R0, Rm), Rn */
   767                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   768                         CHECKRALIGN32( R0 + sh4r.r[Rm] );
   769                                            sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
   770                         }
   771                         break;
   772                     case 0xF:
   773                         { /* MAC.L @Rm+, @Rn+ */
   774                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   775                         CHECKRALIGN32( sh4r.r[Rm] );
   776                         CHECKRALIGN32( sh4r.r[Rn] );
   777                         int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
   778                         sh4r.r[Rn] += 4;
   779                         tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
   780                         sh4r.r[Rm] += 4;
   781                         if( sh4r.s ) {
   782                             /* 48-bit Saturation. Yuch */
   783                             if( tmpl < (int64_t)0xFFFF800000000000LL )
   784                                 tmpl = 0xFFFF800000000000LL;
   785                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   786                                 tmpl = 0x00007FFFFFFFFFFFLL;
   787                         }
   788                         sh4r.mac = tmpl;
   789                         }
   790                         break;
   791                     default:
   792                         UNDEF();
   793                         break;
   794                 }
   795                 break;
   796             case 0x1:
   797                 { /* MOV.L Rm, @(disp, Rn) */
   798                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   799                 tmp = sh4r.r[Rn] + disp;
   800                 CHECKWALIGN32( tmp );
   801                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   802                 }
   803                 break;
   804             case 0x2:
   805                 switch( ir&0xF ) {
   806                     case 0x0:
   807                         { /* MOV.B Rm, @Rn */
   808                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   809                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   810                         }
   811                         break;
   812                     case 0x1:
   813                         { /* MOV.W Rm, @Rn */
   814                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   815                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   816                         }
   817                         break;
   818                     case 0x2:
   819                         { /* MOV.L Rm, @Rn */
   820                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   821                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   822                         }
   823                         break;
   824                     case 0x4:
   825                         { /* MOV.B Rm, @-Rn */
   826                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   827                         sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   828                         }
   829                         break;
   830                     case 0x5:
   831                         { /* MOV.W Rm, @-Rn */
   832                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   833                         sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   834                         }
   835                         break;
   836                     case 0x6:
   837                         { /* MOV.L Rm, @-Rn */
   838                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   839                         sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   840                         }
   841                         break;
   842                     case 0x7:
   843                         { /* DIV0S Rm, Rn */
   844                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   845                         sh4r.q = sh4r.r[Rn]>>31;
   846                         sh4r.m = sh4r.r[Rm]>>31;
   847                         sh4r.t = sh4r.q ^ sh4r.m;
   848                         }
   849                         break;
   850                     case 0x8:
   851                         { /* TST Rm, Rn */
   852                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   853                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
   854                         }
   855                         break;
   856                     case 0x9:
   857                         { /* AND Rm, Rn */
   858                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   859                         sh4r.r[Rn] &= sh4r.r[Rm];
   860                         }
   861                         break;
   862                     case 0xA:
   863                         { /* XOR Rm, Rn */
   864                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   865                         sh4r.r[Rn] ^= sh4r.r[Rm];
   866                         }
   867                         break;
   868                     case 0xB:
   869                         { /* OR Rm, Rn */
   870                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   871                         sh4r.r[Rn] |= sh4r.r[Rm];
   872                         }
   873                         break;
   874                     case 0xC:
   875                         { /* CMP/STR Rm, Rn */
   876                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   877                         /* set T = 1 if any byte in RM & RN is the same */
   878                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   879                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   880                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   881                         }
   882                         break;
   883                     case 0xD:
   884                         { /* XTRCT Rm, Rn */
   885                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   886                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
   887                         }
   888                         break;
   889                     case 0xE:
   890                         { /* MULU.W Rm, Rn */
   891                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   892                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   893                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   894                         }
   895                         break;
   896                     case 0xF:
   897                         { /* MULS.W Rm, Rn */
   898                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   899                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   900                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   901                         }
   902                         break;
   903                     default:
   904                         UNDEF();
   905                         break;
   906                 }
   907                 break;
   908             case 0x3:
   909                 switch( ir&0xF ) {
   910                     case 0x0:
   911                         { /* CMP/EQ Rm, Rn */
   912                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   913                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
   914                         }
   915                         break;
   916                     case 0x2:
   917                         { /* CMP/HS Rm, Rn */
   918                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   919                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
   920                         }
   921                         break;
   922                     case 0x3:
   923                         { /* CMP/GE Rm, Rn */
   924                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   925                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   926                         }
   927                         break;
   928                     case 0x4:
   929                         { /* DIV1 Rm, Rn */
   930                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   931                         /* This is just from the sh4p manual with some
   932                          * simplifications (someone want to check it's correct? :)
   933                          * Why they couldn't just provide a real DIV instruction...
   934                          */
   935                         uint32_t tmp0, tmp1, tmp2, dir;
   937                         dir = sh4r.q ^ sh4r.m;
   938                         sh4r.q = (sh4r.r[Rn] >> 31);
   939                         tmp2 = sh4r.r[Rm];
   940                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   941                         tmp0 = sh4r.r[Rn];
   942                         if( dir ) {
   943                              sh4r.r[Rn] += tmp2;
   944                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   945                         } else {
   946                              sh4r.r[Rn] -= tmp2;
   947                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   948                         }
   949                         sh4r.q ^= sh4r.m ^ tmp1;
   950                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   951                         }
   952                         break;
   953                     case 0x5:
   954                         { /* DMULU.L Rm, Rn */
   955                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   956                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
   957                         }
   958                         break;
   959                     case 0x6:
   960                         { /* CMP/HI Rm, Rn */
   961                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   962                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
   963                         }
   964                         break;
   965                     case 0x7:
   966                         { /* CMP/GT Rm, Rn */
   967                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   968                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   969                         }
   970                         break;
   971                     case 0x8:
   972                         { /* SUB Rm, Rn */
   973                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   974                         sh4r.r[Rn] -= sh4r.r[Rm];
   975                         }
   976                         break;
   977                     case 0xA:
   978                         { /* SUBC Rm, Rn */
   979                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   980                         tmp = sh4r.r[Rn];
   981                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   982                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   983                         }
   984                         break;
   985                     case 0xB:
   986                         UNIMP(ir); /* SUBV Rm, Rn */
   987                         break;
   988                     case 0xC:
   989                         { /* ADD Rm, Rn */
   990                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   991                         sh4r.r[Rn] += sh4r.r[Rm];
   992                         }
   993                         break;
   994                     case 0xD:
   995                         { /* DMULS.L Rm, Rn */
   996                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   997                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
   998                         }
   999                         break;
  1000                     case 0xE:
  1001                         { /* ADDC Rm, Rn */
  1002                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1003                         tmp = sh4r.r[Rn];
  1004                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
  1005                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
  1007                         break;
  1008                     case 0xF:
  1009                         { /* ADDV Rm, Rn */
  1010                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1011                         tmp = sh4r.r[Rn] + sh4r.r[Rm];
  1012                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
  1013                         sh4r.r[Rn] = tmp;
  1015                         break;
  1016                     default:
  1017                         UNDEF();
  1018                         break;
  1020                 break;
  1021             case 0x4:
  1022                 switch( ir&0xF ) {
  1023                     case 0x0:
  1024                         switch( (ir&0xF0) >> 4 ) {
  1025                             case 0x0:
  1026                                 { /* SHLL Rn */
  1027                                 uint32_t Rn = ((ir>>8)&0xF); 
  1028                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
  1030                                 break;
  1031                             case 0x1:
  1032                                 { /* DT Rn */
  1033                                 uint32_t Rn = ((ir>>8)&0xF); 
  1034                                 sh4r.r[Rn] --;
  1035                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
  1037                                 break;
  1038                             case 0x2:
  1039                                 { /* SHAL Rn */
  1040                                 uint32_t Rn = ((ir>>8)&0xF); 
  1041                                 sh4r.t = sh4r.r[Rn] >> 31;
  1042                                 sh4r.r[Rn] <<= 1;
  1044                                 break;
  1045                             default:
  1046                                 UNDEF();
  1047                                 break;
  1049                         break;
  1050                     case 0x1:
  1051                         switch( (ir&0xF0) >> 4 ) {
  1052                             case 0x0:
  1053                                 { /* SHLR Rn */
  1054                                 uint32_t Rn = ((ir>>8)&0xF); 
  1055                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
  1057                                 break;
  1058                             case 0x1:
  1059                                 { /* CMP/PZ Rn */
  1060                                 uint32_t Rn = ((ir>>8)&0xF); 
  1061                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
  1063                                 break;
  1064                             case 0x2:
  1065                                 { /* SHAR Rn */
  1066                                 uint32_t Rn = ((ir>>8)&0xF); 
  1067                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1068                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
  1070                                 break;
  1071                             default:
  1072                                 UNDEF();
  1073                                 break;
  1075                         break;
  1076                     case 0x2:
  1077                         switch( (ir&0xF0) >> 4 ) {
  1078                             case 0x0:
  1079                                 { /* STS.L MACH, @-Rn */
  1080                                 uint32_t Rn = ((ir>>8)&0xF); 
  1081                                 sh4r.r[Rn] -= 4;
  1082                                 CHECKWALIGN32( sh4r.r[Rn] );
  1083                                 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
  1085                                 break;
  1086                             case 0x1:
  1087                                 { /* STS.L MACL, @-Rn */
  1088                                 uint32_t Rn = ((ir>>8)&0xF); 
  1089                                 sh4r.r[Rn] -= 4;
  1090                                 CHECKWALIGN32( sh4r.r[Rn] );
  1091                                 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
  1093                                 break;
  1094                             case 0x2:
  1095                                 { /* STS.L PR, @-Rn */
  1096                                 uint32_t Rn = ((ir>>8)&0xF); 
  1097                                 sh4r.r[Rn] -= 4;
  1098                                 CHECKWALIGN32( sh4r.r[Rn] );
  1099                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
  1101                                 break;
  1102                             case 0x3:
  1103                                 { /* STC.L SGR, @-Rn */
  1104                                 uint32_t Rn = ((ir>>8)&0xF); 
  1105                                 CHECKPRIV();
  1106                                 sh4r.r[Rn] -= 4;
  1107                                 CHECKWALIGN32( sh4r.r[Rn] );
  1108                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
  1110                                 break;
  1111                             case 0x5:
  1112                                 { /* STS.L FPUL, @-Rn */
  1113                                 uint32_t Rn = ((ir>>8)&0xF); 
  1114                                 sh4r.r[Rn] -= 4;
  1115                                 CHECKWALIGN32( sh4r.r[Rn] );
  1116                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
  1118                                 break;
  1119                             case 0x6:
  1120                                 { /* STS.L FPSCR, @-Rn */
  1121                                 uint32_t Rn = ((ir>>8)&0xF); 
  1122                                 sh4r.r[Rn] -= 4;
  1123                                 CHECKWALIGN32( sh4r.r[Rn] );
  1124                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
  1126                                 break;
  1127                             case 0xF:
  1128                                 { /* STC.L DBR, @-Rn */
  1129                                 uint32_t Rn = ((ir>>8)&0xF); 
  1130                                 CHECKPRIV();
  1131                                 sh4r.r[Rn] -= 4;
  1132                                 CHECKWALIGN32( sh4r.r[Rn] );
  1133                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
  1135                                 break;
  1136                             default:
  1137                                 UNDEF();
  1138                                 break;
  1140                         break;
  1141                     case 0x3:
  1142                         switch( (ir&0x80) >> 7 ) {
  1143                             case 0x0:
  1144                                 switch( (ir&0x70) >> 4 ) {
  1145                                     case 0x0:
  1146                                         { /* STC.L SR, @-Rn */
  1147                                         uint32_t Rn = ((ir>>8)&0xF); 
  1148                                         CHECKPRIV();
  1149                                         sh4r.r[Rn] -= 4;
  1150                                         CHECKWALIGN32( sh4r.r[Rn] );
  1151                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
  1153                                         break;
  1154                                     case 0x1:
  1155                                         { /* STC.L GBR, @-Rn */
  1156                                         uint32_t Rn = ((ir>>8)&0xF); 
  1157                                         sh4r.r[Rn] -= 4;
  1158                                         CHECKWALIGN32( sh4r.r[Rn] );
  1159                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
  1161                                         break;
  1162                                     case 0x2:
  1163                                         { /* STC.L VBR, @-Rn */
  1164                                         uint32_t Rn = ((ir>>8)&0xF); 
  1165                                         CHECKPRIV();
  1166                                         sh4r.r[Rn] -= 4;
  1167                                         CHECKWALIGN32( sh4r.r[Rn] );
  1168                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
  1170                                         break;
  1171                                     case 0x3:
  1172                                         { /* STC.L SSR, @-Rn */
  1173                                         uint32_t Rn = ((ir>>8)&0xF); 
  1174                                         CHECKPRIV();
  1175                                         sh4r.r[Rn] -= 4;
  1176                                         CHECKWALIGN32( sh4r.r[Rn] );
  1177                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
  1179                                         break;
  1180                                     case 0x4:
  1181                                         { /* STC.L SPC, @-Rn */
  1182                                         uint32_t Rn = ((ir>>8)&0xF); 
  1183                                         CHECKPRIV();
  1184                                         sh4r.r[Rn] -= 4;
  1185                                         CHECKWALIGN32( sh4r.r[Rn] );
  1186                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
  1188                                         break;
  1189                                     default:
  1190                                         UNDEF();
  1191                                         break;
  1193                                 break;
  1194                             case 0x1:
  1195                                 { /* STC.L Rm_BANK, @-Rn */
  1196                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1197                                 CHECKPRIV();
  1198                                 sh4r.r[Rn] -= 4;
  1199                                 CHECKWALIGN32( sh4r.r[Rn] );
  1200                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
  1202                                 break;
  1204                         break;
  1205                     case 0x4:
  1206                         switch( (ir&0xF0) >> 4 ) {
  1207                             case 0x0:
  1208                                 { /* ROTL Rn */
  1209                                 uint32_t Rn = ((ir>>8)&0xF); 
  1210                                 sh4r.t = sh4r.r[Rn] >> 31;
  1211                                 sh4r.r[Rn] <<= 1;
  1212                                 sh4r.r[Rn] |= sh4r.t;
  1214                                 break;
  1215                             case 0x2:
  1216                                 { /* ROTCL Rn */
  1217                                 uint32_t Rn = ((ir>>8)&0xF); 
  1218                                 tmp = sh4r.r[Rn] >> 31;
  1219                                 sh4r.r[Rn] <<= 1;
  1220                                 sh4r.r[Rn] |= sh4r.t;
  1221                                 sh4r.t = tmp;
  1223                                 break;
  1224                             default:
  1225                                 UNDEF();
  1226                                 break;
  1228                         break;
  1229                     case 0x5:
  1230                         switch( (ir&0xF0) >> 4 ) {
  1231                             case 0x0:
  1232                                 { /* ROTR Rn */
  1233                                 uint32_t Rn = ((ir>>8)&0xF); 
  1234                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1235                                 sh4r.r[Rn] >>= 1;
  1236                                 sh4r.r[Rn] |= (sh4r.t << 31);
  1238                                 break;
  1239                             case 0x1:
  1240                                 { /* CMP/PL Rn */
  1241                                 uint32_t Rn = ((ir>>8)&0xF); 
  1242                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
  1244                                 break;
  1245                             case 0x2:
  1246                                 { /* ROTCR Rn */
  1247                                 uint32_t Rn = ((ir>>8)&0xF); 
  1248                                 tmp = sh4r.r[Rn] & 0x00000001;
  1249                                 sh4r.r[Rn] >>= 1;
  1250                                 sh4r.r[Rn] |= (sh4r.t << 31 );
  1251                                 sh4r.t = tmp;
  1253                                 break;
  1254                             default:
  1255                                 UNDEF();
  1256                                 break;
  1258                         break;
  1259                     case 0x6:
  1260                         switch( (ir&0xF0) >> 4 ) {
  1261                             case 0x0:
  1262                                 { /* LDS.L @Rm+, MACH */
  1263                                 uint32_t Rm = ((ir>>8)&0xF); 
  1264                                 CHECKRALIGN32( sh4r.r[Rm] );
  1265                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1266                                            (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
  1267                                 sh4r.r[Rm] += 4;
  1269                                 break;
  1270                             case 0x1:
  1271                                 { /* LDS.L @Rm+, MACL */
  1272                                 uint32_t Rm = ((ir>>8)&0xF); 
  1273                                 CHECKRALIGN32( sh4r.r[Rm] );
  1274                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1275                                            (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
  1276                                 sh4r.r[Rm] += 4;
  1278                                 break;
  1279                             case 0x2:
  1280                                 { /* LDS.L @Rm+, PR */
  1281                                 uint32_t Rm = ((ir>>8)&0xF); 
  1282                                 CHECKRALIGN32( sh4r.r[Rm] );
  1283                                 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
  1284                                 sh4r.r[Rm] += 4;
  1286                                 break;
  1287                             case 0x3:
  1288                                 { /* LDC.L @Rm+, SGR */
  1289                                 uint32_t Rm = ((ir>>8)&0xF); 
  1290                                 CHECKPRIV();
  1291                                 CHECKRALIGN32( sh4r.r[Rm] );
  1292                                 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
  1293                                 sh4r.r[Rm] +=4;
  1295                                 break;
  1296                             case 0x5:
  1297                                 { /* LDS.L @Rm+, FPUL */
  1298                                 uint32_t Rm = ((ir>>8)&0xF); 
  1299                                 CHECKRALIGN32( sh4r.r[Rm] );
  1300                                 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
  1301                                 sh4r.r[Rm] +=4;
  1303                                 break;
  1304                             case 0x6:
  1305                                 { /* LDS.L @Rm+, FPSCR */
  1306                                 uint32_t Rm = ((ir>>8)&0xF); 
  1307                                 CHECKRALIGN32( sh4r.r[Rm] );
  1308                                 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
  1309                                 sh4r.r[Rm] +=4;
  1311                                 break;
  1312                             case 0xF:
  1313                                 { /* LDC.L @Rm+, DBR */
  1314                                 uint32_t Rm = ((ir>>8)&0xF); 
  1315                                 CHECKPRIV();
  1316                                 CHECKRALIGN32( sh4r.r[Rm] );
  1317                                 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
  1318                                 sh4r.r[Rm] +=4;
  1320                                 break;
  1321                             default:
  1322                                 UNDEF();
  1323                                 break;
  1325                         break;
  1326                     case 0x7:
  1327                         switch( (ir&0x80) >> 7 ) {
  1328                             case 0x0:
  1329                                 switch( (ir&0x70) >> 4 ) {
  1330                                     case 0x0:
  1331                                         { /* LDC.L @Rm+, SR */
  1332                                         uint32_t Rm = ((ir>>8)&0xF); 
  1333                                         CHECKSLOTILLEGAL();
  1334                                         CHECKPRIV();
  1335                                         CHECKWALIGN32( sh4r.r[Rm] );
  1336                                         sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) );
  1337                                         sh4r.r[Rm] +=4;
  1339                                         break;
  1340                                     case 0x1:
  1341                                         { /* LDC.L @Rm+, GBR */
  1342                                         uint32_t Rm = ((ir>>8)&0xF); 
  1343                                         CHECKRALIGN32( sh4r.r[Rm] );
  1344                                         sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
  1345                                         sh4r.r[Rm] +=4;
  1347                                         break;
  1348                                     case 0x2:
  1349                                         { /* LDC.L @Rm+, VBR */
  1350                                         uint32_t Rm = ((ir>>8)&0xF); 
  1351                                         CHECKPRIV();
  1352                                         CHECKRALIGN32( sh4r.r[Rm] );
  1353                                         sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
  1354                                         sh4r.r[Rm] +=4;
  1356                                         break;
  1357                                     case 0x3:
  1358                                         { /* LDC.L @Rm+, SSR */
  1359                                         uint32_t Rm = ((ir>>8)&0xF); 
  1360                                         CHECKPRIV();
  1361                                         CHECKRALIGN32( sh4r.r[Rm] );
  1362                                         sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
  1363                                         sh4r.r[Rm] +=4;
  1365                                         break;
  1366                                     case 0x4:
  1367                                         { /* LDC.L @Rm+, SPC */
  1368                                         uint32_t Rm = ((ir>>8)&0xF); 
  1369                                         CHECKPRIV();
  1370                                         CHECKRALIGN32( sh4r.r[Rm] );
  1371                                         sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
  1372                                         sh4r.r[Rm] +=4;
  1374                                         break;
  1375                                     default:
  1376                                         UNDEF();
  1377                                         break;
  1379                                 break;
  1380                             case 0x1:
  1381                                 { /* LDC.L @Rm+, Rn_BANK */
  1382                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1383                                 CHECKPRIV();
  1384                                 CHECKRALIGN32( sh4r.r[Rm] );
  1385                                 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
  1386                                 sh4r.r[Rm] += 4;
  1388                                 break;
  1390                         break;
  1391                     case 0x8:
  1392                         switch( (ir&0xF0) >> 4 ) {
  1393                             case 0x0:
  1394                                 { /* SHLL2 Rn */
  1395                                 uint32_t Rn = ((ir>>8)&0xF); 
  1396                                 sh4r.r[Rn] <<= 2;
  1398                                 break;
  1399                             case 0x1:
  1400                                 { /* SHLL8 Rn */
  1401                                 uint32_t Rn = ((ir>>8)&0xF); 
  1402                                 sh4r.r[Rn] <<= 8;
  1404                                 break;
  1405                             case 0x2:
  1406                                 { /* SHLL16 Rn */
  1407                                 uint32_t Rn = ((ir>>8)&0xF); 
  1408                                 sh4r.r[Rn] <<= 16;
  1410                                 break;
  1411                             default:
  1412                                 UNDEF();
  1413                                 break;
  1415                         break;
  1416                     case 0x9:
  1417                         switch( (ir&0xF0) >> 4 ) {
  1418                             case 0x0:
  1419                                 { /* SHLR2 Rn */
  1420                                 uint32_t Rn = ((ir>>8)&0xF); 
  1421                                 sh4r.r[Rn] >>= 2;
  1423                                 break;
  1424                             case 0x1:
  1425                                 { /* SHLR8 Rn */
  1426                                 uint32_t Rn = ((ir>>8)&0xF); 
  1427                                 sh4r.r[Rn] >>= 8;
  1429                                 break;
  1430                             case 0x2:
  1431                                 { /* SHLR16 Rn */
  1432                                 uint32_t Rn = ((ir>>8)&0xF); 
  1433                                 sh4r.r[Rn] >>= 16;
  1435                                 break;
  1436                             default:
  1437                                 UNDEF();
  1438                                 break;
  1440                         break;
  1441                     case 0xA:
  1442                         switch( (ir&0xF0) >> 4 ) {
  1443                             case 0x0:
  1444                                 { /* LDS Rm, MACH */
  1445                                 uint32_t Rm = ((ir>>8)&0xF); 
  1446                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1447                                            (((uint64_t)sh4r.r[Rm])<<32);
  1449                                 break;
  1450                             case 0x1:
  1451                                 { /* LDS Rm, MACL */
  1452                                 uint32_t Rm = ((ir>>8)&0xF); 
  1453                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1454                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));
  1456                                 break;
  1457                             case 0x2:
  1458                                 { /* LDS Rm, PR */
  1459                                 uint32_t Rm = ((ir>>8)&0xF); 
  1460                                 sh4r.pr = sh4r.r[Rm];
  1462                                 break;
  1463                             case 0x3:
  1464                                 { /* LDC Rm, SGR */
  1465                                 uint32_t Rm = ((ir>>8)&0xF); 
  1466                                 CHECKPRIV();
  1467                                 sh4r.sgr = sh4r.r[Rm];
  1469                                 break;
  1470                             case 0x5:
  1471                                 { /* LDS Rm, FPUL */
  1472                                 uint32_t Rm = ((ir>>8)&0xF); 
  1473                                 sh4r.fpul = sh4r.r[Rm];
  1475                                 break;
  1476                             case 0x6:
  1477                                 { /* LDS Rm, FPSCR */
  1478                                 uint32_t Rm = ((ir>>8)&0xF); 
  1479                                 sh4r.fpscr = sh4r.r[Rm];
  1481                                 break;
  1482                             case 0xF:
  1483                                 { /* LDC Rm, DBR */
  1484                                 uint32_t Rm = ((ir>>8)&0xF); 
  1485                                 CHECKPRIV();
  1486                                 sh4r.dbr = sh4r.r[Rm];
  1488                                 break;
  1489                             default:
  1490                                 UNDEF();
  1491                                 break;
  1493                         break;
  1494                     case 0xB:
  1495                         switch( (ir&0xF0) >> 4 ) {
  1496                             case 0x0:
  1497                                 { /* JSR @Rn */
  1498                                 uint32_t Rn = ((ir>>8)&0xF); 
  1499                                 CHECKDEST( sh4r.r[Rn] );
  1500                                 CHECKSLOTILLEGAL();
  1501                                 sh4r.in_delay_slot = 1;
  1502                                 sh4r.pc = sh4r.new_pc;
  1503                                 sh4r.new_pc = sh4r.r[Rn];
  1504                                 sh4r.pr = pc + 4;
  1505                                 TRACE_CALL( pc, sh4r.new_pc );
  1506                                 return TRUE;
  1508                                 break;
  1509                             case 0x1:
  1510                                 { /* TAS.B @Rn */
  1511                                 uint32_t Rn = ((ir>>8)&0xF); 
  1512                                 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
  1513                                 sh4r.t = ( tmp == 0 ? 1 : 0 );
  1514                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
  1516                                 break;
  1517                             case 0x2:
  1518                                 { /* JMP @Rn */
  1519                                 uint32_t Rn = ((ir>>8)&0xF); 
  1520                                 CHECKDEST( sh4r.r[Rn] );
  1521                                 CHECKSLOTILLEGAL();
  1522                                 sh4r.in_delay_slot = 1;
  1523                                 sh4r.pc = sh4r.new_pc;
  1524                                 sh4r.new_pc = sh4r.r[Rn];
  1525                                 return TRUE;
  1527                                 break;
  1528                             default:
  1529                                 UNDEF();
  1530                                 break;
  1532                         break;
  1533                     case 0xC:
  1534                         { /* SHAD Rm, Rn */
  1535                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1536                         tmp = sh4r.r[Rm];
  1537                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1538                         else if( (tmp & 0x1F) == 0 )  
  1539                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
  1540                         else 
  1541                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
  1543                         break;
  1544                     case 0xD:
  1545                         { /* SHLD Rm, Rn */
  1546                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1547                         tmp = sh4r.r[Rm];
  1548                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1549                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
  1550                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
  1552                         break;
  1553                     case 0xE:
  1554                         switch( (ir&0x80) >> 7 ) {
  1555                             case 0x0:
  1556                                 switch( (ir&0x70) >> 4 ) {
  1557                                     case 0x0:
  1558                                         { /* LDC Rm, SR */
  1559                                         uint32_t Rm = ((ir>>8)&0xF); 
  1560                                         CHECKSLOTILLEGAL();
  1561                                         CHECKPRIV();
  1562                                         sh4_load_sr( sh4r.r[Rm] );
  1564                                         break;
  1565                                     case 0x1:
  1566                                         { /* LDC Rm, GBR */
  1567                                         uint32_t Rm = ((ir>>8)&0xF); 
  1568                                         sh4r.gbr = sh4r.r[Rm];
  1570                                         break;
  1571                                     case 0x2:
  1572                                         { /* LDC Rm, VBR */
  1573                                         uint32_t Rm = ((ir>>8)&0xF); 
  1574                                         CHECKPRIV();
  1575                                         sh4r.vbr = sh4r.r[Rm];
  1577                                         break;
  1578                                     case 0x3:
  1579                                         { /* LDC Rm, SSR */
  1580                                         uint32_t Rm = ((ir>>8)&0xF); 
  1581                                         CHECKPRIV();
  1582                                         sh4r.ssr = sh4r.r[Rm];
  1584                                         break;
  1585                                     case 0x4:
  1586                                         { /* LDC Rm, SPC */
  1587                                         uint32_t Rm = ((ir>>8)&0xF); 
  1588                                         CHECKPRIV();
  1589                                         sh4r.spc = sh4r.r[Rm];
  1591                                         break;
  1592                                     default:
  1593                                         UNDEF();
  1594                                         break;
  1596                                 break;
  1597                             case 0x1:
  1598                                 { /* LDC Rm, Rn_BANK */
  1599                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1600                                 CHECKPRIV();
  1601                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1603                                 break;
  1605                         break;
  1606                     case 0xF:
  1607                         { /* MAC.W @Rm+, @Rn+ */
  1608                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1609                         CHECKRALIGN16( sh4r.r[Rn] );
  1610                         CHECKRALIGN16( sh4r.r[Rm] );
  1611                         int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
  1612                         sh4r.r[Rn] += 2;
  1613                         stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
  1614                         sh4r.r[Rm] += 2;
  1615                         if( sh4r.s ) {
  1616                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
  1617                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
  1618                     	    sh4r.mac = 0x000000017FFFFFFFLL;
  1619                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
  1620                     	    sh4r.mac = 0x0000000180000000LL;
  1621                     	} else {
  1622                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1623                     		((uint32_t)(sh4r.mac + stmp));
  1625                         } else {
  1626                     	sh4r.mac += SIGNEXT32(stmp);
  1629                         break;
  1631                 break;
  1632             case 0x5:
  1633                 { /* MOV.L @(disp, Rm), Rn */
  1634                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  1635                 tmp = sh4r.r[Rm] + disp;
  1636                 CHECKRALIGN32( tmp );
  1637                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1639                 break;
  1640             case 0x6:
  1641                 switch( ir&0xF ) {
  1642                     case 0x0:
  1643                         { /* MOV.B @Rm, Rn */
  1644                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1645                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );
  1647                         break;
  1648                     case 0x1:
  1649                         { /* MOV.W @Rm, Rn */
  1650                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1651                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );
  1653                         break;
  1654                     case 0x2:
  1655                         { /* MOV.L @Rm, Rn */
  1656                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1657                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );
  1659                         break;
  1660                     case 0x3:
  1661                         { /* MOV Rm, Rn */
  1662                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1663                         sh4r.r[Rn] = sh4r.r[Rm];
  1665                         break;
  1666                     case 0x4:
  1667                         { /* MOV.B @Rm+, Rn */
  1668                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1669                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;
  1671                         break;
  1672                     case 0x5:
  1673                         { /* MOV.W @Rm+, Rn */
  1674                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1675                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;
  1677                         break;
  1678                     case 0x6:
  1679                         { /* MOV.L @Rm+, Rn */
  1680                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1681                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;
  1683                         break;
  1684                     case 0x7:
  1685                         { /* NOT Rm, Rn */
  1686                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1687                         sh4r.r[Rn] = ~sh4r.r[Rm];
  1689                         break;
  1690                     case 0x8:
  1691                         { /* SWAP.B Rm, Rn */
  1692                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1693                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
  1695                         break;
  1696                     case 0x9:
  1697                         { /* SWAP.W Rm, Rn */
  1698                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1699                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
  1701                         break;
  1702                     case 0xA:
  1703                         { /* NEGC Rm, Rn */
  1704                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1705                         tmp = 0 - sh4r.r[Rm];
  1706                         sh4r.r[Rn] = tmp - sh4r.t;
  1707                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
  1709                         break;
  1710                     case 0xB:
  1711                         { /* NEG Rm, Rn */
  1712                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1713                         sh4r.r[Rn] = 0 - sh4r.r[Rm];
  1715                         break;
  1716                     case 0xC:
  1717                         { /* EXTU.B Rm, Rn */
  1718                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1719                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
  1721                         break;
  1722                     case 0xD:
  1723                         { /* EXTU.W Rm, Rn */
  1724                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1725                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
  1727                         break;
  1728                     case 0xE:
  1729                         { /* EXTS.B Rm, Rn */
  1730                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1731                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
  1733                         break;
  1734                     case 0xF:
  1735                         { /* EXTS.W Rm, Rn */
  1736                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1737                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
  1739                         break;
  1741                 break;
  1742             case 0x7:
  1743                 { /* ADD #imm, Rn */
  1744                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1745                 sh4r.r[Rn] += imm;
  1747                 break;
  1748             case 0x8:
  1749                 switch( (ir&0xF00) >> 8 ) {
  1750                     case 0x0:
  1751                         { /* MOV.B R0, @(disp, Rn) */
  1752                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1753                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
  1755                         break;
  1756                     case 0x1:
  1757                         { /* MOV.W R0, @(disp, Rn) */
  1758                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1759                         tmp = sh4r.r[Rn] + disp;
  1760                         CHECKWALIGN16( tmp );
  1761                         MEM_WRITE_WORD( tmp, R0 );
  1763                         break;
  1764                     case 0x4:
  1765                         { /* MOV.B @(disp, Rm), R0 */
  1766                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1767                         R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );
  1769                         break;
  1770                     case 0x5:
  1771                         { /* MOV.W @(disp, Rm), R0 */
  1772                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1773                         tmp = sh4r.r[Rm] + disp;
  1774                         CHECKRALIGN16( tmp );
  1775                         R0 = MEM_READ_WORD( tmp );
  1777                         break;
  1778                     case 0x8:
  1779                         { /* CMP/EQ #imm, R0 */
  1780                         int32_t imm = SIGNEXT8(ir&0xFF); 
  1781                         sh4r.t = ( R0 == imm ? 1 : 0 );
  1783                         break;
  1784                     case 0x9:
  1785                         { /* BT disp */
  1786                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1787                         CHECKSLOTILLEGAL();
  1788                         if( sh4r.t ) {
  1789                             CHECKDEST( sh4r.pc + disp + 4 )
  1790                             sh4r.pc += disp + 4;
  1791                             sh4r.new_pc = sh4r.pc + 2;
  1792                             return TRUE;
  1795                         break;
  1796                     case 0xB:
  1797                         { /* BF disp */
  1798                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1799                         CHECKSLOTILLEGAL();
  1800                         if( !sh4r.t ) {
  1801                             CHECKDEST( sh4r.pc + disp + 4 )
  1802                             sh4r.pc += disp + 4;
  1803                             sh4r.new_pc = sh4r.pc + 2;
  1804                             return TRUE;
  1807                         break;
  1808                     case 0xD:
  1809                         { /* BT/S disp */
  1810                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1811                         CHECKSLOTILLEGAL();
  1812                         if( sh4r.t ) {
  1813                             CHECKDEST( sh4r.pc + disp + 4 )
  1814                             sh4r.in_delay_slot = 1;
  1815                             sh4r.pc = sh4r.new_pc;
  1816                             sh4r.new_pc = pc + disp + 4;
  1817                             sh4r.in_delay_slot = 1;
  1818                             return TRUE;
  1821                         break;
  1822                     case 0xF:
  1823                         { /* BF/S disp */
  1824                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1825                         CHECKSLOTILLEGAL();
  1826                         if( !sh4r.t ) {
  1827                             CHECKDEST( sh4r.pc + disp + 4 )
  1828                             sh4r.in_delay_slot = 1;
  1829                             sh4r.pc = sh4r.new_pc;
  1830                             sh4r.new_pc = pc + disp + 4;
  1831                             return TRUE;
  1834                         break;
  1835                     default:
  1836                         UNDEF();
  1837                         break;
  1839                 break;
  1840             case 0x9:
  1841                 { /* MOV.W @(disp, PC), Rn */
  1842                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  1843                 CHECKSLOTILLEGAL();
  1844                 tmp = pc + 4 + disp;
  1845                 sh4r.r[Rn] = MEM_READ_WORD( tmp );
  1847                 break;
  1848             case 0xA:
  1849                 { /* BRA disp */
  1850                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1851                 CHECKSLOTILLEGAL();
  1852                 CHECKDEST( sh4r.pc + disp + 4 );
  1853                 sh4r.in_delay_slot = 1;
  1854                 sh4r.pc = sh4r.new_pc;
  1855                 sh4r.new_pc = pc + 4 + disp;
  1856                 return TRUE;
  1858                 break;
  1859             case 0xB:
  1860                 { /* BSR disp */
  1861                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1862                 CHECKDEST( sh4r.pc + disp + 4 );
  1863                 CHECKSLOTILLEGAL();
  1864                 sh4r.in_delay_slot = 1;
  1865                 sh4r.pr = pc + 4;
  1866                 sh4r.pc = sh4r.new_pc;
  1867                 sh4r.new_pc = pc + 4 + disp;
  1868                 TRACE_CALL( pc, sh4r.new_pc );
  1869                 return TRUE;
  1871                 break;
  1872             case 0xC:
  1873                 switch( (ir&0xF00) >> 8 ) {
  1874                     case 0x0:
  1875                         { /* MOV.B R0, @(disp, GBR) */
  1876                         uint32_t disp = (ir&0xFF); 
  1877                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
  1879                         break;
  1880                     case 0x1:
  1881                         { /* MOV.W R0, @(disp, GBR) */
  1882                         uint32_t disp = (ir&0xFF)<<1; 
  1883                         tmp = sh4r.gbr + disp;
  1884                         CHECKWALIGN16( tmp );
  1885                         MEM_WRITE_WORD( tmp, R0 );
  1887                         break;
  1888                     case 0x2:
  1889                         { /* MOV.L R0, @(disp, GBR) */
  1890                         uint32_t disp = (ir&0xFF)<<2; 
  1891                         tmp = sh4r.gbr + disp;
  1892                         CHECKWALIGN32( tmp );
  1893                         MEM_WRITE_LONG( tmp, R0 );
  1895                         break;
  1896                     case 0x3:
  1897                         { /* TRAPA #imm */
  1898                         uint32_t imm = (ir&0xFF); 
  1899                         CHECKSLOTILLEGAL();
  1900                         MMIO_WRITE( MMU, TRA, imm<<2 );
  1901                         sh4r.pc += 2;
  1902                         sh4_raise_exception( EXC_TRAP );
  1904                         break;
  1905                     case 0x4:
  1906                         { /* MOV.B @(disp, GBR), R0 */
  1907                         uint32_t disp = (ir&0xFF); 
  1908                         R0 = MEM_READ_BYTE( sh4r.gbr + disp );
  1910                         break;
  1911                     case 0x5:
  1912                         { /* MOV.W @(disp, GBR), R0 */
  1913                         uint32_t disp = (ir&0xFF)<<1; 
  1914                         tmp = sh4r.gbr + disp;
  1915                         CHECKRALIGN16( tmp );
  1916                         R0 = MEM_READ_WORD( tmp );
  1918                         break;
  1919                     case 0x6:
  1920                         { /* MOV.L @(disp, GBR), R0 */
  1921                         uint32_t disp = (ir&0xFF)<<2; 
  1922                         tmp = sh4r.gbr + disp;
  1923                         CHECKRALIGN32( tmp );
  1924                         R0 = MEM_READ_LONG( tmp );
  1926                         break;
  1927                     case 0x7:
  1928                         { /* MOVA @(disp, PC), R0 */
  1929                         uint32_t disp = (ir&0xFF)<<2; 
  1930                         CHECKSLOTILLEGAL();
  1931                         R0 = (pc&0xFFFFFFFC) + disp + 4;
  1933                         break;
  1934                     case 0x8:
  1935                         { /* TST #imm, R0 */
  1936                         uint32_t imm = (ir&0xFF); 
  1937                         sh4r.t = (R0 & imm ? 0 : 1);
  1939                         break;
  1940                     case 0x9:
  1941                         { /* AND #imm, R0 */
  1942                         uint32_t imm = (ir&0xFF); 
  1943                         R0 &= imm;
  1945                         break;
  1946                     case 0xA:
  1947                         { /* XOR #imm, R0 */
  1948                         uint32_t imm = (ir&0xFF); 
  1949                         R0 ^= imm;
  1951                         break;
  1952                     case 0xB:
  1953                         { /* OR #imm, R0 */
  1954                         uint32_t imm = (ir&0xFF); 
  1955                         R0 |= imm;
  1957                         break;
  1958                     case 0xC:
  1959                         { /* TST.B #imm, @(R0, GBR) */
  1960                         uint32_t imm = (ir&0xFF); 
  1961                         sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );
  1963                         break;
  1964                     case 0xD:
  1965                         { /* AND.B #imm, @(R0, GBR) */
  1966                         uint32_t imm = (ir&0xFF); 
  1967                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1969                         break;
  1970                     case 0xE:
  1971                         { /* XOR.B #imm, @(R0, GBR) */
  1972                         uint32_t imm = (ir&0xFF); 
  1973                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1975                         break;
  1976                     case 0xF:
  1977                         { /* OR.B #imm, @(R0, GBR) */
  1978                         uint32_t imm = (ir&0xFF); 
  1979                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1981                         break;
  1983                 break;
  1984             case 0xD:
  1985                 { /* MOV.L @(disp, PC), Rn */
  1986                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  1987                 CHECKSLOTILLEGAL();
  1988                 tmp = (pc&0xFFFFFFFC) + disp + 4;
  1989                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1991                 break;
  1992             case 0xE:
  1993                 { /* MOV #imm, Rn */
  1994                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1995                 sh4r.r[Rn] = imm;
  1997                 break;
  1998             case 0xF:
  1999                 switch( ir&0xF ) {
  2000                     case 0x0:
  2001                         { /* FADD FRm, FRn */
  2002                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2003                         CHECKFPUEN();
  2004                         if( IS_FPU_DOUBLEPREC() ) {
  2005                     	DR(FRn) += DR(FRm);
  2006                         } else {
  2007                     	FR(FRn) += FR(FRm);
  2010                         break;
  2011                     case 0x1:
  2012                         { /* FSUB FRm, FRn */
  2013                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2014                         CHECKFPUEN();
  2015                         if( IS_FPU_DOUBLEPREC() ) {
  2016                     	DR(FRn) -= DR(FRm);
  2017                         } else {
  2018                     	FR(FRn) -= FR(FRm);
  2021                         break;
  2022                     case 0x2:
  2023                         { /* FMUL FRm, FRn */
  2024                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2025                         CHECKFPUEN();
  2026                         if( IS_FPU_DOUBLEPREC() ) {
  2027                     	DR(FRn) *= DR(FRm);
  2028                         } else {
  2029                     	FR(FRn) *= FR(FRm);
  2032                         break;
  2033                     case 0x3:
  2034                         { /* FDIV FRm, FRn */
  2035                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2036                         CHECKFPUEN();
  2037                         if( IS_FPU_DOUBLEPREC() ) {
  2038                     	DR(FRn) /= DR(FRm);
  2039                         } else {
  2040                     	FR(FRn) /= FR(FRm);
  2043                         break;
  2044                     case 0x4:
  2045                         { /* FCMP/EQ FRm, FRn */
  2046                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2047                         CHECKFPUEN();
  2048                         if( IS_FPU_DOUBLEPREC() ) {
  2049                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  2050                         } else {
  2051                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  2054                         break;
  2055                     case 0x5:
  2056                         { /* FCMP/GT FRm, FRn */
  2057                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2058                         CHECKFPUEN();
  2059                         if( IS_FPU_DOUBLEPREC() ) {
  2060                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  2061                         } else {
  2062                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  2065                         break;
  2066                     case 0x6:
  2067                         { /* FMOV @(R0, Rm), FRn */
  2068                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2069                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
  2071                         break;
  2072                     case 0x7:
  2073                         { /* FMOV FRm, @(R0, Rn) */
  2074                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2075                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
  2077                         break;
  2078                     case 0x8:
  2079                         { /* FMOV @Rm, FRn */
  2080                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2081                         MEM_FP_READ( sh4r.r[Rm], FRn );
  2083                         break;
  2084                     case 0x9:
  2085                         { /* FMOV @Rm+, FRn */
  2086                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2087                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
  2089                         break;
  2090                     case 0xA:
  2091                         { /* FMOV FRm, @Rn */
  2092                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2093                         MEM_FP_WRITE( sh4r.r[Rn], FRm );
  2095                         break;
  2096                     case 0xB:
  2097                         { /* FMOV FRm, @-Rn */
  2098                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2099                         sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
  2101                         break;
  2102                     case 0xC:
  2103                         { /* FMOV FRm, FRn */
  2104                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2105                         if( IS_FPU_DOUBLESIZE() )
  2106                     	DR(FRn) = DR(FRm);
  2107                         else
  2108                     	FR(FRn) = FR(FRm);
  2110                         break;
  2111                     case 0xD:
  2112                         switch( (ir&0xF0) >> 4 ) {
  2113                             case 0x0:
  2114                                 { /* FSTS FPUL, FRn */
  2115                                 uint32_t FRn = ((ir>>8)&0xF); 
  2116                                 CHECKFPUEN(); FR(FRn) = FPULf;
  2118                                 break;
  2119                             case 0x1:
  2120                                 { /* FLDS FRm, FPUL */
  2121                                 uint32_t FRm = ((ir>>8)&0xF); 
  2122                                 CHECKFPUEN(); FPULf = FR(FRm);
  2124                                 break;
  2125                             case 0x2:
  2126                                 { /* FLOAT FPUL, FRn */
  2127                                 uint32_t FRn = ((ir>>8)&0xF); 
  2128                                 CHECKFPUEN();
  2129                                 if( IS_FPU_DOUBLEPREC() )
  2130                             	DR(FRn) = (float)FPULi;
  2131                                 else
  2132                             	FR(FRn) = (float)FPULi;
  2134                                 break;
  2135                             case 0x3:
  2136                                 { /* FTRC FRm, FPUL */
  2137                                 uint32_t FRm = ((ir>>8)&0xF); 
  2138                                 CHECKFPUEN();
  2139                                 if( IS_FPU_DOUBLEPREC() ) {
  2140                                     dtmp = DR(FRm);
  2141                                     if( dtmp >= MAX_INTF )
  2142                                         FPULi = MAX_INT;
  2143                                     else if( dtmp <= MIN_INTF )
  2144                                         FPULi = MIN_INT;
  2145                                     else 
  2146                                         FPULi = (int32_t)dtmp;
  2147                                 } else {
  2148                             	ftmp = FR(FRm);
  2149                             	if( ftmp >= MAX_INTF )
  2150                             	    FPULi = MAX_INT;
  2151                             	else if( ftmp <= MIN_INTF )
  2152                             	    FPULi = MIN_INT;
  2153                             	else
  2154                             	    FPULi = (int32_t)ftmp;
  2157                                 break;
  2158                             case 0x4:
  2159                                 { /* FNEG FRn */
  2160                                 uint32_t FRn = ((ir>>8)&0xF); 
  2161                                 CHECKFPUEN();
  2162                                 if( IS_FPU_DOUBLEPREC() ) {
  2163                             	DR(FRn) = -DR(FRn);
  2164                                 } else {
  2165                                     FR(FRn) = -FR(FRn);
  2168                                 break;
  2169                             case 0x5:
  2170                                 { /* FABS FRn */
  2171                                 uint32_t FRn = ((ir>>8)&0xF); 
  2172                                 CHECKFPUEN();
  2173                                 if( IS_FPU_DOUBLEPREC() ) {
  2174                             	DR(FRn) = fabs(DR(FRn));
  2175                                 } else {
  2176                                     FR(FRn) = fabsf(FR(FRn));
  2179                                 break;
  2180                             case 0x6:
  2181                                 { /* FSQRT FRn */
  2182                                 uint32_t FRn = ((ir>>8)&0xF); 
  2183                                 CHECKFPUEN();
  2184                                 if( IS_FPU_DOUBLEPREC() ) {
  2185                             	DR(FRn) = sqrt(DR(FRn));
  2186                                 } else {
  2187                                     FR(FRn) = sqrtf(FR(FRn));
  2190                                 break;
  2191                             case 0x7:
  2192                                 { /* FSRRA FRn */
  2193                                 uint32_t FRn = ((ir>>8)&0xF); 
  2194                                 CHECKFPUEN();
  2195                                 if( !IS_FPU_DOUBLEPREC() ) {
  2196                             	FR(FRn) = 1.0/sqrtf(FR(FRn));
  2199                                 break;
  2200                             case 0x8:
  2201                                 { /* FLDI0 FRn */
  2202                                 uint32_t FRn = ((ir>>8)&0xF); 
  2203                                 CHECKFPUEN();
  2204                                 if( IS_FPU_DOUBLEPREC() ) {
  2205                             	DR(FRn) = 0.0;
  2206                                 } else {
  2207                                     FR(FRn) = 0.0;
  2210                                 break;
  2211                             case 0x9:
  2212                                 { /* FLDI1 FRn */
  2213                                 uint32_t FRn = ((ir>>8)&0xF); 
  2214                                 CHECKFPUEN();
  2215                                 if( IS_FPU_DOUBLEPREC() ) {
  2216                             	DR(FRn) = 1.0;
  2217                                 } else {
  2218                                     FR(FRn) = 1.0;
  2221                                 break;
  2222                             case 0xA:
  2223                                 { /* FCNVSD FPUL, FRn */
  2224                                 uint32_t FRn = ((ir>>8)&0xF); 
  2225                                 CHECKFPUEN();
  2226                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2227                             	DR(FRn) = (double)FPULf;
  2230                                 break;
  2231                             case 0xB:
  2232                                 { /* FCNVDS FRm, FPUL */
  2233                                 uint32_t FRm = ((ir>>8)&0xF); 
  2234                                 CHECKFPUEN();
  2235                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2236                             	FPULf = (float)DR(FRm);
  2239                                 break;
  2240                             case 0xE:
  2241                                 { /* FIPR FVm, FVn */
  2242                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  2243                                 CHECKFPUEN();
  2244                                 if( !IS_FPU_DOUBLEPREC() ) {
  2245                                     int tmp2 = FVn<<2;
  2246                                     tmp = FVm<<2;
  2247                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  2248                                         FR(tmp+1)*FR(tmp2+1) +
  2249                                         FR(tmp+2)*FR(tmp2+2) +
  2250                                         FR(tmp+3)*FR(tmp2+3);
  2253                                 break;
  2254                             case 0xF:
  2255                                 switch( (ir&0x100) >> 8 ) {
  2256                                     case 0x0:
  2257                                         { /* FSCA FPUL, FRn */
  2258                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  2259                                         CHECKFPUEN();
  2260                                         if( !IS_FPU_DOUBLEPREC() ) {
  2261                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  2262                                             FR(FRn) = sinf(angle);
  2263                                             FR((FRn)+1) = cosf(angle);
  2266                                         break;
  2267                                     case 0x1:
  2268                                         switch( (ir&0x200) >> 9 ) {
  2269                                             case 0x0:
  2270                                                 { /* FTRV XMTRX, FVn */
  2271                                                 uint32_t FVn = ((ir>>10)&0x3); 
  2272                                                 CHECKFPUEN();
  2273                                                 if( !IS_FPU_DOUBLEPREC() ) {
  2274                                                     tmp = FVn<<2;
  2275                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  2276                                                     FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
  2277                                             	    XF(8)*fv[2] + XF(12)*fv[3];
  2278                                                     FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
  2279                                             	    XF(9)*fv[2] + XF(13)*fv[3];
  2280                                                     FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
  2281                                             	    XF(10)*fv[2] + XF(14)*fv[3];
  2282                                                     FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
  2283                                             	    XF(11)*fv[2] + XF(15)*fv[3];
  2286                                                 break;
  2287                                             case 0x1:
  2288                                                 switch( (ir&0xC00) >> 10 ) {
  2289                                                     case 0x0:
  2290                                                         { /* FSCHG */
  2291                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
  2293                                                         break;
  2294                                                     case 0x2:
  2295                                                         { /* FRCHG */
  2296                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR;
  2298                                                         break;
  2299                                                     case 0x3:
  2300                                                         { /* UNDEF */
  2301                                                         UNDEF(ir);
  2303                                                         break;
  2304                                                     default:
  2305                                                         UNDEF();
  2306                                                         break;
  2308                                                 break;
  2310                                         break;
  2312                                 break;
  2313                             default:
  2314                                 UNDEF();
  2315                                 break;
  2317                         break;
  2318                     case 0xE:
  2319                         { /* FMAC FR0, FRm, FRn */
  2320                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2321                         CHECKFPUEN();
  2322                         if( IS_FPU_DOUBLEPREC() ) {
  2323                             DR(FRn) += DR(FRm)*DR(0);
  2324                         } else {
  2325                     	FR(FRn) += FR(FRm)*FR(0);
  2328                         break;
  2329                     default:
  2330                         UNDEF();
  2331                         break;
  2333                 break;
  2336     sh4r.pc = sh4r.new_pc;
  2337     sh4r.new_pc += 2;
  2338     sh4r.in_delay_slot = 0;
  2339     return TRUE;
.