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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 127:4ba79389bb6d
prev108:565de331ccec
next133:249aeda31f02
author nkeynes
date Thu Mar 23 13:19:15 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add a vram dump function for debugging purposes
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     1 /**
     2  * $Id: pvr2.c,v 1.21 2006-03-23 13:19:15 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "video.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2/pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2/pvr2mmio.h"
    29 char *video_base;
    31 void pvr2_init( void );
    32 uint32_t pvr2_run_slice( uint32_t );
    33 void pvr2_display_frame( void );
    35 /**
    36  * Current PVR2 ram address of the data (if any) currently held in the 
    37  * OpenGL buffers.
    38  */
    40 video_driver_t video_driver = NULL;
    41 struct video_buffer video_buffer[2];
    42 int video_buffer_idx = 0;
    44 struct video_timing {
    45     int fields_per_second;
    46     int total_lines;
    47     int retrace_lines;
    48     int line_time_ns;
    49 };
    51 struct video_timing pal_timing = { 50, 625, 50, 32000 };
    52 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    54 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, 
    55 					pvr2_run_slice, NULL,
    56 					NULL, NULL };
    58 void pvr2_init( void )
    59 {
    60     register_io_region( &mmio_region_PVR2 );
    61     register_io_region( &mmio_region_PVR2PAL );
    62     register_io_region( &mmio_region_PVR2TA );
    63     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    64     pvr2_render_init();
    65     texcache_init();
    66 }
    68 void video_set_driver( video_driver_t driver )
    69 {
    70     if( video_driver != NULL && video_driver->shutdown_driver != NULL )
    71 	video_driver->shutdown_driver();
    73     video_driver = driver;
    74     if( driver->init_driver != NULL )
    75 	driver->init_driver();
    76     driver->set_display_format( 640, 480, COLFMT_RGB32 );
    77     driver->set_render_format( 640, 480, COLFMT_RGB32, FALSE );
    78     texcache_gl_init();
    79 }
    81 uint32_t pvr2_line_count = 0;
    82 uint32_t pvr2_line_remainder = 0;
    83 uint32_t pvr2_irq_vpos1 = 0;
    84 uint32_t pvr2_irq_vpos2 = 0;
    85 gboolean pvr2_retrace = FALSE;
    86 struct video_timing *pvr2_timing = &ntsc_timing;
    87 uint32_t pvr2_time_counter = 0;
    88 uint32_t pvr2_frame_counter = 0;
    89 uint32_t pvr2_time_per_frame = 20000000;
    91 uint32_t pvr2_run_slice( uint32_t nanosecs ) 
    92 {
    93     pvr2_line_remainder += nanosecs;
    94     while( pvr2_line_remainder >= pvr2_timing->line_time_ns ) {
    95 	pvr2_line_remainder -= pvr2_timing->line_time_ns;
    96 	pvr2_line_count++;
    97 	if( pvr2_line_count == pvr2_irq_vpos1 ) {
    98 	    asic_event( EVENT_SCANLINE1 );
    99 	} 
   100 	if( pvr2_line_count == pvr2_irq_vpos2 ) {
   101 	    asic_event( EVENT_SCANLINE2 );
   102 	}
   103 	if( pvr2_line_count == pvr2_timing->total_lines ) {
   104 	    asic_event( EVENT_RETRACE );
   105 	    pvr2_line_count = 0;
   106 	    pvr2_retrace = TRUE;
   107 	} else if( pvr2_line_count == pvr2_timing->retrace_lines ) {
   108 	    if( pvr2_retrace ) {
   109 		pvr2_display_frame();
   110 		pvr2_retrace = FALSE;
   111 	    }
   112 	}
   113     }
   114     return nanosecs;
   115 }
   117 uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
   118 int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
   119 char *frame_start; /* current video start address (in real memory) */
   121 /**
   122  * Display the next frame, copying the current contents of video ram to
   123  * the window. If the video configuration has changed, first recompute the
   124  * new frame size/depth.
   125  */
   126 void pvr2_display_frame( void )
   127 {
   128     uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
   130     int dispsize = MMIO_READ( PVR2, DISPSIZE );
   131     int dispmode = MMIO_READ( PVR2, DISPMODE );
   132     int vidcfg = MMIO_READ( PVR2, DISPCFG );
   133     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   134     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   135     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   136     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   137     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   138     if( bEnabled ) {
   139 	video_buffer_t buffer = &video_buffer[video_buffer_idx];
   140 	video_buffer_idx = !video_buffer_idx;
   141 	video_buffer_t last = &video_buffer[video_buffer_idx];
   142 	buffer->rowstride = (vid_ppl + vid_stride) << 2;
   143 	buffer->data = frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
   144 	buffer->vres = vid_lpf;
   145 	if( interlaced ) buffer->vres <<= 1;
   146 	switch( (dispmode & DISPMODE_COL) >> 2 ) {
   147 	case 0: 
   148 	    buffer->colour_format = COLFMT_ARGB1555;
   149 	    buffer->hres = vid_ppl << 1; 
   150 	    break;
   151 	case 1: 
   152 	    buffer->colour_format = COLFMT_RGB565;
   153 	    buffer->hres = vid_ppl << 1; 
   154 	    break;
   155 	case 2:
   156 	    buffer->colour_format = COLFMT_RGB888;
   157 	    buffer->hres = (vid_ppl << 2) / 3; 
   158 	    break;
   159 	case 3: 
   160 	    buffer->colour_format = COLFMT_ARGB8888;
   161 	    buffer->hres = vid_ppl; 
   162 	    break;
   163 	}
   165 	if( video_driver != NULL ) {
   166 	    if( buffer->hres != last->hres ||
   167 		buffer->vres != last->vres ||
   168 		buffer->colour_format != last->colour_format) {
   169 		video_driver->set_display_format( buffer->hres, buffer->vres,
   170 						  buffer->colour_format );
   171 	    }
   172 	    if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
   173 		uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
   174 		video_driver->display_blank_frame( colour );
   175 	    } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   176 		video_driver->display_frame( buffer );
   177 	    }
   178 	}
   179     } else {
   180 	video_buffer_idx = 0;
   181 	video_buffer[0].hres = video_buffer[0].vres = 0;
   182     }
   183     pvr2_frame_counter++;
   184     asic_event( EVENT_SCANLINE1 );
   185     asic_event( EVENT_SCANLINE2 );
   186     asic_event( EVENT_RETRACE );
   187 }
   189 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   190 {
   191     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   192         MMIO_WRITE( PVR2, reg, val );
   193         /* I don't want to hear about these */
   194         return;
   195     }
   197     INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
   198           MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
   200     MMIO_WRITE( PVR2, reg, val );
   202     switch(reg) {
   203     case DISPADDR1:
   204 	if( pvr2_retrace ) {
   205 	    pvr2_display_frame();
   206 	    pvr2_retrace = FALSE;
   207 	}
   208 	break;
   209     case VPOS_IRQ:
   210 	pvr2_irq_vpos1 = (val >> 16) & 0x03FF;
   211 	pvr2_irq_vpos2 = val & 0x03FF;
   212 	break;
   213     case TAINIT:
   214 	if( val & 0x80000000 )
   215 	    pvr2_ta_init();
   216 	break;
   217     case RENDSTART:
   218 	if( val == 0xFFFFFFFF )
   219 	    pvr2_render_scene();
   220 	break;
   221     }
   222 }
   224 MMIO_REGION_READ_FN( PVR2, reg )
   225 {
   226     switch( reg ) {
   227         case BEAMPOS:
   228             return sh4r.icount&0x20 ? 0x2000 : 1;
   229         default:
   230             return MMIO_READ( PVR2, reg );
   231     }
   232 }
   234 MMIO_REGION_DEFFNS( PVR2PAL )
   236 void pvr2_set_base_address( uint32_t base ) 
   237 {
   238     mmio_region_PVR2_write( DISPADDR1, base );
   239 }
   244 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   245 {
   246     return 0xFFFFFFFF;
   247 }
   249 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   250 {
   251     pvr2_ta_write( &val, sizeof(uint32_t) );
   252 }
   255 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
   256 {
   257     int bank_flag = (destaddr & 0x04) >> 2;
   258     uint32_t *banks[2];
   259     uint32_t *dwsrc;
   260     int i;
   262     destaddr = destaddr & 0x7FFFFF;
   263     if( destaddr + length > 0x800000 ) {
   264 	length = 0x800000 - destaddr;
   265     }
   267     for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
   268 	texcache_invalidate_page( i );
   269     }
   271     banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
   272     banks[1] = banks[0] + 0x100000;
   273     if( bank_flag ) 
   274 	banks[0]++;
   276     /* Handle non-aligned start of source */
   277     if( destaddr & 0x03 ) {
   278 	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
   279 	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   280 	    *dest++ = *src++;
   281 	}
   282 	bank_flag = !bank_flag;
   283     }
   285     dwsrc = (uint32_t *)src;
   286     while( length >= 4 ) {
   287 	*banks[bank_flag]++ = *dwsrc++;
   288 	bank_flag = !bank_flag;
   289 	length -= 4;
   290     }
   292     /* Handle non-aligned end of source */
   293     if( length ) {
   294 	src = (char *)dwsrc;
   295 	char *dest = (char *)banks[bank_flag];
   296 	while( length-- > 0 ) {
   297 	    *dest++ = *src++;
   298 	}
   299     }  
   301 }
   303 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
   304 {
   305     int bank_flag = (srcaddr & 0x04) >> 2;
   306     uint32_t *banks[2];
   307     uint32_t *dwdest;
   308     int i;
   310     srcaddr = srcaddr & 0x7FFFFF;
   311     if( srcaddr + length > 0x800000 )
   312 	length = 0x800000 - srcaddr;
   314     banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
   315     banks[1] = banks[0] + 0x100000;
   316     if( bank_flag )
   317 	banks[0]++;
   319     /* Handle non-aligned start of source */
   320     if( srcaddr & 0x03 ) {
   321 	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
   322 	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   323 	    *dest++ = *src++;
   324 	}
   325 	bank_flag = !bank_flag;
   326     }
   328     dwdest = (uint32_t *)dest;
   329     while( length >= 4 ) {
   330 	*dwdest++ = *banks[bank_flag]++;
   331 	bank_flag = !bank_flag;
   332 	length -= 4;
   333     }
   335     /* Handle non-aligned end of source */
   336     if( length ) {
   337 	dest = (char *)dwdest;
   338 	char *src = (char *)banks[bank_flag];
   339 	while( length-- > 0 ) {
   340 	    *dest++ = *src++;
   341 	}
   342     }
   343 }
   345 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
   346 {
   347     char tmp[length];
   348     pvr2_vram64_read( tmp, addr, length );
   349     fwrite_dump( tmp, length, f );
   350 }
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