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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 855:b937948d79d9
prev833:1ea87e0221f8
next929:fd8cb0c82f5f
author nkeynes
date Wed Oct 29 23:51:58 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Use regparam calling conventions for all functions called from translated code,
along with a few other high-use functions. Can probably extend this to all functions,
but as it is this is a nice performance boost
view annotate diff log raw
     1 /**
     2  * $Id$
     3  *
     4  * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
     5  * and DMA). 
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE asic_module
    22 #include <assert.h>
    23 #include <stdlib.h>
    24 #include "dream.h"
    25 #include "mem.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/dmac.h"
    28 #include "sh4/sh4.h"
    29 #include "dreamcast.h"
    30 #include "maple/maple.h"
    31 #include "gdrom/ide.h"
    32 #include "pvr2/pvr2.h"
    33 #include "asic.h"
    34 #define MMIO_IMPL
    35 #include "asic.h"
    36 /*
    37  * Open questions:
    38  *   1) Does changing the mask after event occurance result in the
    39  *      interrupt being delivered immediately?
    40  * TODO: Logic diagram of ASIC event/interrupt logic.
    41  *
    42  * ... don't even get me started on the "EXTDMA" page, about which, apparently,
    43  * practically nothing is publicly known...
    44  */
    46 static void asic_check_cleared_events( void );
    47 static void asic_init( void );
    48 static void asic_reset( void );
    49 static uint32_t asic_run_slice( uint32_t nanosecs );
    50 static void asic_save_state( FILE *f );
    51 static int asic_load_state( FILE *f );
    52 static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
    54 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
    55         NULL, asic_save_state, asic_load_state };
    57 #define G2_BIT5_TICKS 60
    58 #define G2_BIT4_TICKS 160
    59 #define G2_BIT0_ON_TICKS 120
    60 #define G2_BIT0_OFF_TICKS 420
    62 struct asic_g2_state {
    63     int bit5_off_timer;
    64     int bit4_on_timer;
    65     int bit4_off_timer;
    66     int bit0_on_timer;
    67     int bit0_off_timer;
    68 };
    70 static struct asic_g2_state g2_state;
    72 static uint32_t asic_run_slice( uint32_t nanosecs )
    73 {
    74     g2_update_fifo_status(nanosecs);
    75     if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
    76         g2_state.bit5_off_timer = -1;
    77     } else {
    78         g2_state.bit5_off_timer -= nanosecs;
    79     }
    81     if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
    82         g2_state.bit4_off_timer = -1;
    83     } else {
    84         g2_state.bit4_off_timer -= nanosecs;
    85     }
    86     if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
    87         g2_state.bit4_on_timer = -1;
    88     } else {
    89         g2_state.bit4_on_timer -= nanosecs;
    90     }
    92     if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
    93         g2_state.bit0_off_timer = -1;
    94     } else {
    95         g2_state.bit0_off_timer -= nanosecs;
    96     }
    97     if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
    98         g2_state.bit0_on_timer = -1;
    99     } else {
   100         g2_state.bit0_on_timer -= nanosecs;
   101     }
   103     return nanosecs;
   104 }
   106 static void asic_init( void )
   107 {
   108     register_io_region( &mmio_region_ASIC );
   109     register_io_region( &mmio_region_EXTDMA );
   110     asic_reset();
   111 }
   113 static void asic_reset( void )
   114 {
   115     memset( &g2_state, 0xFF, sizeof(g2_state) );
   116 }    
   118 static void asic_save_state( FILE *f )
   119 {
   120     fwrite( &g2_state, sizeof(g2_state), 1, f );
   121 }
   123 static int asic_load_state( FILE *f )
   124 {
   125     if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
   126         return 1;
   127     else
   128         return 0;
   129 }
   132 /**
   133  * Setup the timers for the 3 FIFO status bits following a write through the G2
   134  * bus from the SH4 side. The timing is roughly as follows: (times are
   135  * approximate based on software readings - I wouldn't take this as gospel but
   136  * it seems to be enough to fool most programs). 
   137  *    0ns: Bit 5 (Input fifo?) goes high immediately on the write
   138  *   40ns: Bit 5 goes low and bit 4 goes high
   139  *  120ns: Bit 4 goes low, bit 0 goes high
   140  *  240ns: Bit 0 goes low.
   141  *
   142  * Additional writes while the FIFO is in operation extend the time that the
   143  * bits remain high as one might expect, without altering the time at which
   144  * they initially go high.
   145  */
   146 void asic_g2_write_word()
   147 {
   148     if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
   149         g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
   150     } else {
   151         g2_state.bit5_off_timer += G2_BIT5_TICKS;
   152     }
   154     if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
   155         g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
   156     }
   158     if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
   159         g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
   160     } else {
   161         g2_state.bit4_off_timer += G2_BIT4_TICKS;
   162     }
   164     if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
   165         g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
   166     }
   168     if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
   169         g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
   170     } else {
   171         g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
   172     }
   174     MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
   175 }
   177 static uint32_t g2_update_fifo_status( uint32_t nanos )
   178 {
   179     uint32_t val = MMIO_READ( ASIC, G2STATUS );
   180     if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
   181         val = val & (~0x20);
   182         g2_state.bit5_off_timer = -1;
   183     }
   184     if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
   185         val = val | 0x10;
   186         g2_state.bit4_on_timer = -1;
   187     }
   188     if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
   189         val = val & (~0x10);
   190         g2_state.bit4_off_timer = -1;
   191     } 
   193     if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
   194         val = val | 0x01;
   195         g2_state.bit0_on_timer = -1;
   196     }
   197     if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
   198         val = val & (~0x01);
   199         g2_state.bit0_off_timer = -1;
   200     } 
   202     MMIO_WRITE( ASIC, G2STATUS, val );
   203     return val;
   204 }   
   206 static int g2_read_status() {
   207     return g2_update_fifo_status( sh4r.slice_cycle );
   208 }
   211 void asic_event( int event )
   212 {
   213     int offset = ((event&0x60)>>3);
   214     int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
   216     if( result & MMIO_READ(ASIC, IRQA0 + offset) )
   217         intc_raise_interrupt( INT_IRQ13 );
   218     if( result & MMIO_READ(ASIC, IRQB0 + offset) )
   219         intc_raise_interrupt( INT_IRQ11 );
   220     if( result & MMIO_READ(ASIC, IRQC0 + offset) )
   221         intc_raise_interrupt( INT_IRQ9 );
   223     if( event >= 64 ) { /* Third word */
   224         asic_event( EVENT_CASCADE2 );
   225     } else if( event >= 32 ) { /* Second word */
   226         asic_event( EVENT_CASCADE1 );
   227     }
   228 }
   230 void asic_clear_event( int event ) {
   231     int offset = ((event&0x60)>>3);
   232     uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
   233     MMIO_WRITE( ASIC, PIRQ0 + offset, result );
   234     if( result == 0 ) {
   235         /* clear cascades if necessary */
   236         if( event >= 64 ) {
   237             MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
   238         } else if( event >= 32 ) {
   239             MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
   240         }
   241     }
   243     asic_check_cleared_events();
   244 }
   246 void asic_check_cleared_events( )
   247 {
   248     int i, setA = 0, setB = 0, setC = 0;
   249     uint32_t bits;
   250     for( i=0; i<12; i+=4 ) {
   251         bits = MMIO_READ( ASIC, PIRQ0 + i );
   252         setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
   253         setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
   254         setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
   255     }
   256     if( setA == 0 )
   257         intc_clear_interrupt( INT_IRQ13 );
   258     if( setB == 0 )
   259         intc_clear_interrupt( INT_IRQ11 );
   260     if( setC == 0 )
   261         intc_clear_interrupt( INT_IRQ9 );
   262 }
   264 void asic_event_mask_changed( )
   265 {
   266     int i, setA = 0, setB = 0, setC = 0;
   267     uint32_t bits;
   268     for( i=0; i<12; i+=4 ) {
   269         bits = MMIO_READ( ASIC, PIRQ0 + i );
   270         setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
   271         setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
   272         setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
   273     }
   274     if( setA == 0 ) 
   275         intc_clear_interrupt( INT_IRQ13 );
   276     else
   277         intc_raise_interrupt( INT_IRQ13 );
   278     if( setB == 0 )
   279         intc_clear_interrupt( INT_IRQ11 );
   280     else
   281         intc_raise_interrupt( INT_IRQ11 );
   282     if( setC == 0 )
   283         intc_clear_interrupt( INT_IRQ9 );
   284     else
   285         intc_raise_interrupt( INT_IRQ9 );
   286 }
   288 void g2_dma_transfer( int channel )
   289 {
   290     uint32_t offset = channel << 5;
   292     if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
   293         if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
   294             uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
   295             uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
   296             uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
   297             uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
   298             // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
   299             unsigned char buf[length];
   300             if( dir == 0 ) { /* SH4 to device */
   301                 mem_copy_from_sh4( buf, sh4addr, length );
   302                 mem_copy_to_sh4( extaddr, buf, length );
   303             } else { /* Device to SH4 */
   304                 mem_copy_from_sh4( buf, extaddr, length );
   305                 mem_copy_to_sh4( sh4addr, buf, length );
   306             }
   307             MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
   308             asic_event( EVENT_G2_DMA0 + channel );
   309         } else {
   310             MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
   311         }
   312     }
   313 }
   315 void asic_ide_dma_transfer( )
   316 {	
   317     if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
   318         if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
   319             MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
   321             uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
   322             uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
   323             // int dir = MMIO_READ( EXTDMA, IDEDMADIR );
   325             uint32_t xfer = ide_read_data_dma( addr, length );
   326             MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
   327             MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
   328             asic_event( EVENT_IDE_DMA );            
   329         } else { /* 0 */
   330             MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
   331         }
   332     }
   333 }
   335 void pvr_dma_transfer( )
   336 {
   337     sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
   338     uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
   339     unsigned char *data = alloca( count );
   340     uint32_t rcount = DMAC_get_buffer( 2, data, count );
   341     if( rcount != count )
   342         WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
   344     pvr2_dma_write( destaddr, data, rcount );
   346     MMIO_WRITE( ASIC, PVRDMACTL, 0 );
   347     MMIO_WRITE( ASIC, PVRDMACNT, 0 );
   348     if( destaddr & 0x01000000 ) { /* Write to texture RAM */
   349         MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );
   350     }
   351     asic_event( EVENT_PVR_DMA );
   352 }
   354 void pvr_dma2_transfer()
   355 {
   356     if( MMIO_READ( EXTDMA, PVRDMA2CTL2 ) == 1 ) {
   357         if( MMIO_READ( EXTDMA, PVRDMA2CTL1 ) == 1 ) {
   358             sh4addr_t extaddr = MMIO_READ( EXTDMA, PVRDMA2EXT );
   359             sh4addr_t sh4addr = MMIO_READ( EXTDMA, PVRDMA2SH4 );
   360             int dir = MMIO_READ( EXTDMA, PVRDMA2DIR );
   361             uint32_t length = MMIO_READ( EXTDMA, PVRDMA2SIZ );
   362             unsigned char buf[length];
   363             if( dir == 0 ) { /* SH4 to PVR */
   364                 mem_copy_from_sh4( buf, sh4addr, length );
   365                 mem_copy_to_sh4( extaddr, buf, length );
   366             } else { /* PVR to SH4 */
   367                 mem_copy_from_sh4( buf, extaddr, length );
   368                 mem_copy_to_sh4( sh4addr, buf, length );
   369             }
   370             MMIO_WRITE( EXTDMA, PVRDMA2CTL2, 0 );
   371             asic_event( EVENT_PVR_DMA2 );
   372         }
   373     }
   374 }
   376 void sort_dma_transfer( )
   377 {
   378     sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
   379     sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );
   380     int table_size = MMIO_READ( ASIC, SORTDMATSIZ );
   381     int addr_shift = MMIO_READ( ASIC, SORTDMAASIZ ) ? 5 : 0;
   382     int count = 1;
   384     uint32_t *table32 = (uint32_t *)mem_get_region( table_addr );
   385     uint16_t *table16 = (uint16_t *)table32;
   386     uint32_t next = table_size ? (*table32++) : (uint32_t)(*table16++);
   387     while(1) {
   388         next &= 0x07FFFFFF;
   389         if( next == 1 ) {
   390             next = table_size ? (*table32++) : (uint32_t)(*table16++);
   391             count++;
   392             continue;
   393         } else if( next == 2 ) {
   394             asic_event( EVENT_SORT_DMA );
   395             break;
   396         } 
   397         uint32_t *data = (uint32_t *)mem_get_region(data_addr + (next<<addr_shift));
   398         if( data == NULL ) {
   399             break;
   400         }
   402         uint32_t *poly = pvr2_ta_find_polygon_context(data, 128);
   403         if( poly == NULL ) {
   404             asic_event( EVENT_SORT_DMA_ERR );
   405             break;
   406         }
   407         uint32_t size = poly[6] & 0xFF;
   408         if( size == 0 ) {
   409             size = 0x100;
   410         }
   411         next = poly[7];
   412         pvr2_ta_write( (unsigned char *)data, size<<5 );
   413     }
   415     MMIO_WRITE( ASIC, SORTDMACNT, count );
   416     MMIO_WRITE( ASIC, SORTDMACTL, 0 );
   417 }
   419 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
   420 {
   421     switch( reg ) {
   422     case PIRQ1:
   423         break; /* Treat this as read-only for the moment */
   424     case PIRQ0:
   425         val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
   426         MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
   427         asic_check_cleared_events();
   428         break;
   429     case PIRQ2:
   430         /* Clear any events */
   431         val = MMIO_READ(ASIC, reg)&(~val);
   432         MMIO_WRITE( ASIC, reg, val );
   433         if( val == 0 ) { /* all clear - clear the cascade bit */
   434             MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
   435         }
   436         asic_check_cleared_events();
   437         break;
   438     case IRQA0:
   439     case IRQA1:
   440     case IRQA2:
   441     case IRQB0:
   442     case IRQB1:
   443     case IRQB2:
   444     case IRQC0:
   445     case IRQC1:
   446     case IRQC2:
   447         MMIO_WRITE( ASIC, reg, val );
   448         asic_event_mask_changed();
   449         break;
   450     case SYSRESET:
   451         if( val == 0x7611 ) {
   452             dreamcast_reset();
   453         } else {
   454             WARN( "Unknown value %08X written to SYSRESET port", val );
   455         }
   456         break;
   457     case MAPLE_STATE:
   458         MMIO_WRITE( ASIC, reg, val );
   459         if( val & 1 ) {
   460             uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
   461             maple_handle_buffer( maple_addr );
   462             MMIO_WRITE( ASIC, reg, 0 );
   463         }
   464         break;
   465     case PVRDMADEST:
   466         MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
   467         break;
   468     case PVRDMACNT: 
   469         MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
   470         break;
   471     case PVRDMACTL: /* Initiate PVR DMA transfer */
   472         val = val & 0x01;
   473         MMIO_WRITE( ASIC, reg, val );
   474         if( val == 1 ) {
   475             pvr_dma_transfer();
   476         }
   477         break;
   478     case SORTDMATBL: case SORTDMADATA:
   479         MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );
   480         break;
   481     case SORTDMATSIZ: case SORTDMAASIZ:
   482         MMIO_WRITE( ASIC, reg, (val & 1) );
   483         break;
   484     case SORTDMACTL:
   485         val = val & 1;
   486         MMIO_WRITE( ASIC, reg, val );
   487         if( val == 1 ) {
   488             sort_dma_transfer();
   489         }
   490         break;
   491     case MAPLE_DMA:
   492         MMIO_WRITE( ASIC, reg, val );
   493         break;
   494     default:
   495         MMIO_WRITE( ASIC, reg, val );
   496     }
   497 }
   499 int32_t mmio_region_ASIC_read( uint32_t reg )
   500 {
   501     int32_t val;
   502     switch( reg ) {
   503     case PIRQ0:
   504     case PIRQ1:
   505     case PIRQ2:
   506     case IRQA0:
   507     case IRQA1:
   508     case IRQA2:
   509     case IRQB0:
   510     case IRQB1:
   511     case IRQB2:
   512     case IRQC0:
   513     case IRQC1:
   514     case IRQC2:
   515     case MAPLE_STATE:
   516         val = MMIO_READ(ASIC, reg);
   517         return val;            
   518     case G2STATUS:
   519         return g2_read_status();
   520     default:
   521         val = MMIO_READ(ASIC, reg);
   522         return val;
   523     }
   525 }
   527 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
   528 {
   529     if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
   530         return; /* disabled */
   531     }
   533     switch( reg ) {
   534     case IDEALTSTATUS: /* Device control */
   535         ide_write_control( val );
   536         break;
   537     case IDEDATA:
   538         ide_write_data_pio( val );
   539         break;
   540     case IDEFEAT:
   541         if( ide_can_write_regs() )
   542             idereg.feature = (uint8_t)val;
   543         break;
   544     case IDECOUNT:
   545         if( ide_can_write_regs() )
   546             idereg.count = (uint8_t)val;
   547         break;
   548     case IDELBA0:
   549         if( ide_can_write_regs() )
   550             idereg.lba0 = (uint8_t)val;
   551         break;
   552     case IDELBA1:
   553         if( ide_can_write_regs() )
   554             idereg.lba1 = (uint8_t)val;
   555         break;
   556     case IDELBA2:
   557         if( ide_can_write_regs() )
   558             idereg.lba2 = (uint8_t)val;
   559         break;
   560     case IDEDEV:
   561         if( ide_can_write_regs() )
   562             idereg.device = (uint8_t)val;
   563         break;
   564     case IDECMD:
   565         if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
   566             ide_write_command( (uint8_t)val );
   567         }
   568         break;
   569     case IDEDMASH4:
   570         MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
   571         break;
   572     case IDEDMASIZ:
   573         MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
   574         break;
   575     case IDEDMADIR:
   576         MMIO_WRITE( EXTDMA, reg, val & 1 );
   577         break;
   578     case IDEDMACTL1:
   579     case IDEDMACTL2:
   580         MMIO_WRITE( EXTDMA, reg, val & 0x01 );
   581         asic_ide_dma_transfer( );
   582         break;
   583     case IDEACTIVATE:
   584         if( val == 0x001FFFFF ) {
   585             idereg.interface_enabled = TRUE;
   586             /* Conventional wisdom says that this is necessary but not
   587              * sufficient to enable the IDE interface.
   588              */
   589         } else if( val == 0x000042FE ) {
   590             idereg.interface_enabled = FALSE;
   591         }
   592         break;
   593     case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
   594     case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
   595     case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
   596     case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
   597         MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
   598         break;
   599     case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
   600         MMIO_WRITE( EXTDMA, reg, val & 0x07 );
   601         break;
   602     case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
   603         MMIO_WRITE( EXTDMA, reg, val & 0x01 );
   604         break;
   605     case G2DMA0CTL1:
   606     case G2DMA0CTL2:
   607         MMIO_WRITE( EXTDMA, reg, val & 1);
   608         g2_dma_transfer( 0 );
   609         break;
   610     case G2DMA0STOP:
   611         MMIO_WRITE( EXTDMA, reg, val & 0x37 );
   612         break;
   613     case G2DMA1CTL1:
   614     case G2DMA1CTL2:
   615         MMIO_WRITE( EXTDMA, reg, val & 1);
   616         g2_dma_transfer( 1 );
   617         break;
   619     case G2DMA1STOP:
   620         MMIO_WRITE( EXTDMA, reg, val & 0x37 );
   621         break;
   622     case G2DMA2CTL1:
   623     case G2DMA2CTL2:
   624         MMIO_WRITE( EXTDMA, reg, val &1 );
   625         g2_dma_transfer( 2 );
   626         break;
   627     case G2DMA2STOP:
   628         MMIO_WRITE( EXTDMA, reg, val & 0x37 );
   629         break;
   630     case G2DMA3CTL1:
   631     case G2DMA3CTL2:
   632         MMIO_WRITE( EXTDMA, reg, val &1 );
   633         g2_dma_transfer( 3 );
   634         break;
   635     case G2DMA3STOP:
   636         MMIO_WRITE( EXTDMA, reg, val & 0x37 );
   637         break;
   638     case PVRDMA2CTL1:
   639     case PVRDMA2CTL2:
   640         MMIO_WRITE( EXTDMA, reg, val & 1 );
   641         pvr_dma2_transfer();
   642         break;
   643     default:
   644         MMIO_WRITE( EXTDMA, reg, val );
   645     }
   646 }
   648 MMIO_REGION_READ_FN( EXTDMA, reg )
   649 {
   650     uint32_t val;
   651     if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
   652         return 0xFFFFFFFF; /* disabled */
   653     }
   655     switch( reg ) {
   656     case IDEALTSTATUS: 
   657         val = idereg.status;
   658         return val;
   659     case IDEDATA: return ide_read_data_pio( );
   660     case IDEFEAT: return idereg.error;
   661     case IDECOUNT:return idereg.count;
   662     case IDELBA0: return ide_get_drive_status();
   663     case IDELBA1: return idereg.lba1;
   664     case IDELBA2: return idereg.lba2;
   665     case IDEDEV: return idereg.device;
   666     case IDECMD:
   667         val = ide_read_status();
   668         return val;
   669     default:
   670         val = MMIO_READ( EXTDMA, reg );
   671         return val;
   672     }
   673 }
.