2 * $Id: pvr2.c,v 1.48 2007-10-31 09:10:23 nkeynes Exp $
4 * PVR2 (Video) Core module implementation and MMIO registers.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #define MODULE pvr2_module
27 #include "pvr2/pvr2.h"
28 #include "sh4/sh4core.h"
30 #include "pvr2/pvr2mmio.h"
34 #define MAX_RENDER_BUFFERS 4
36 #define HPOS_PER_FRAME 0
37 #define HPOS_PER_LINECOUNT 1
39 static void pvr2_init( void );
40 static void pvr2_reset( void );
41 static uint32_t pvr2_run_slice( uint32_t );
42 static void pvr2_save_state( FILE *f );
43 static int pvr2_load_state( FILE *f );
44 static void pvr2_update_raster_posn( uint32_t nanosecs );
45 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
46 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
47 static render_buffer_t pvr2_next_render_buffer( );
48 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
49 uint32_t pvr2_get_sync_status();
51 void pvr2_display_frame( void );
53 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
55 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
57 pvr2_save_state, pvr2_load_state };
60 display_driver_t display_driver = NULL;
65 uint32_t line_remainder;
66 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
67 uint32_t irq_hpos_line;
68 uint32_t irq_hpos_line_count;
69 uint32_t irq_hpos_mode;
70 uint32_t irq_hpos_time_ns; /* Time within the line */
73 uint32_t odd_even_field; /* 1 = odd, 0 = even */
74 gboolean palette_changed; /* TRUE if palette has changed since last render */
75 gchar *save_next_render_filename;
80 uint32_t line_time_ns;
82 uint32_t hsync_width_ns;
83 uint32_t front_porch_ns;
84 uint32_t back_porch_ns;
85 uint32_t retrace_start_line;
86 uint32_t retrace_end_line;
90 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
91 static int render_buffer_count = 0;
92 static render_buffer_t displayed_render_buffer = NULL;
95 * Event handler for the hpos callback
97 static void pvr2_hpos_callback( int eventid ) {
98 asic_event( eventid );
99 pvr2_update_raster_posn(sh4r.slice_cycle);
100 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
101 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
102 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
103 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
106 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
107 pvr2_state.irq_hpos_time_ns );
111 * Event handler for the scanline callbacks. Fires the corresponding
112 * ASIC event, and resets the timer for the next field.
114 static void pvr2_scanline_callback( int eventid ) {
115 asic_event( eventid );
116 pvr2_update_raster_posn(sh4r.slice_cycle);
117 if( eventid == EVENT_SCANLINE1 ) {
118 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
120 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
124 static void pvr2_init( void )
127 register_io_region( &mmio_region_PVR2 );
128 register_io_region( &mmio_region_PVR2PAL );
129 register_io_region( &mmio_region_PVR2TA );
130 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
131 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
132 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
133 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
137 pvr2_state.save_next_render_filename = NULL;
138 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
139 render_buffers[i] = NULL;
141 render_buffer_count = 0;
142 displayed_render_buffer = NULL;
145 static void pvr2_reset( void )
148 pvr2_state.line_count = 0;
149 pvr2_state.line_remainder = 0;
150 pvr2_state.cycles_run = 0;
151 pvr2_state.irq_vpos1 = 0;
152 pvr2_state.irq_vpos2 = 0;
153 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
154 pvr2_state.back_porch_ns = 4000;
155 pvr2_state.palette_changed = FALSE;
156 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
157 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
158 mmio_region_PVR2_write( YUV_ADDR, 0 );
159 mmio_region_PVR2_write( YUV_CFG, 0 );
163 if( display_driver ) {
164 display_driver->display_blank(0);
165 for( i=0; i<render_buffer_count; i++ ) {
166 display_driver->destroy_render_buffer(render_buffers[i]);
167 render_buffers[i] = NULL;
169 render_buffer_count = 0;
173 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
175 struct frame_buffer fbuf;
177 fbuf.width = buffer->width;
178 fbuf.height = buffer->height;
179 fbuf.rowstride = fbuf.width*3;
180 fbuf.colour_format = COLFMT_BGR888;
181 fbuf.inverted = buffer->inverted;
182 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
184 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
185 write_png_to_stream( f, &fbuf );
188 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
189 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
190 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
191 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
192 fwrite( &buffer->flushed, sizeof(buffer->flushed), 1, f );
196 render_buffer_t pvr2_load_render_buffer( FILE *f )
198 frame_buffer_t frame = read_png_from_stream( f );
199 if( frame == NULL ) {
203 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
204 assert( buffer != NULL );
205 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
206 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
207 fread( &buffer->address, sizeof(buffer->address), 1, f );
208 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
209 fread( &buffer->flushed, sizeof(buffer->flushed), 1, f );
216 void pvr2_save_render_buffers( FILE *f )
219 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
220 if( displayed_render_buffer != NULL ) {
222 fwrite( &i, sizeof(i), 1, f );
223 pvr2_save_render_buffer( f, displayed_render_buffer );
226 fwrite( &i, sizeof(i), 1, f );
229 for( i=0; i<render_buffer_count; i++ ) {
230 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
231 pvr2_save_render_buffer( f, render_buffers[i] );
236 gboolean pvr2_load_render_buffers( FILE *f )
239 int i, has_frontbuffer;
241 fread( &count, sizeof(count), 1, f );
242 if( count >= MAX_RENDER_BUFFERS ) {
245 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
246 for( i=0; i<render_buffer_count; i++ ) {
247 display_driver->destroy_render_buffer(render_buffers[i]);
248 render_buffers[i] = NULL;
250 render_buffer_count = 0;
252 if( has_frontbuffer ) {
253 displayed_render_buffer = pvr2_load_render_buffer(f);
254 display_driver->display_render_buffer( displayed_render_buffer );
258 for( i=0; i<count; i++ ) {
259 if( pvr2_load_render_buffer( f ) == NULL ) {
267 static void pvr2_save_state( FILE *f )
269 pvr2_save_render_buffers( f );
270 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
271 pvr2_ta_save_state( f );
272 pvr2_yuv_save_state( f );
275 static int pvr2_load_state( FILE *f )
277 if( !pvr2_load_render_buffers(f) )
279 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
281 if( pvr2_ta_load_state(f) ) {
284 return pvr2_yuv_load_state(f);
288 * Update the current raster position to the given number of nanoseconds,
289 * relative to the last time slice. (ie the raster will be adjusted forward
290 * by nanosecs - nanosecs_already_run_this_timeslice)
292 static void pvr2_update_raster_posn( uint32_t nanosecs )
294 uint32_t old_line_count = pvr2_state.line_count;
295 if( pvr2_state.line_time_ns == 0 ) {
296 return; /* do nothing */
298 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
299 pvr2_state.cycles_run = nanosecs;
300 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
301 pvr2_state.line_count ++;
302 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
305 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
306 pvr2_state.line_count -= pvr2_state.total_lines;
307 if( pvr2_state.interlaced ) {
308 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
311 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
312 (old_line_count < pvr2_state.retrace_end_line ||
313 old_line_count > pvr2_state.line_count) ) {
314 pvr2_state.frame_count++;
315 pvr2_display_frame();
319 static uint32_t pvr2_run_slice( uint32_t nanosecs )
321 pvr2_update_raster_posn( nanosecs );
322 pvr2_state.cycles_run = 0;
326 int pvr2_get_frame_count()
328 return pvr2_state.frame_count;
331 render_buffer_t pvr2_get_front_buffer()
333 return displayed_render_buffer;
336 gboolean pvr2_save_next_scene( const gchar *filename )
338 if( pvr2_state.save_next_render_filename != NULL ) {
339 g_free( pvr2_state.save_next_render_filename );
341 pvr2_state.save_next_render_filename = g_strdup(filename);
348 * Display the next frame, copying the current contents of video ram to
349 * the window. If the video configuration has changed, first recompute the
350 * new frame size/depth.
352 void pvr2_display_frame( void )
354 int dispmode = MMIO_READ( PVR2, DISP_MODE );
355 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
356 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
358 if( display_driver == NULL ) {
359 return; /* can't really do anything much */
360 } else if( !bEnabled ) {
361 /* Output disabled == black */
362 display_driver->display_blank( 0 );
363 displayed_render_buffer = NULL;
364 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
365 /* Enabled but blanked - border colour */
366 uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
367 display_driver->display_blank( colour );
368 displayed_render_buffer = NULL;
370 /* Real output - determine dimensions etc */
371 struct frame_buffer fbuf;
372 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
373 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
374 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
376 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
377 fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
378 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
379 fbuf.size = vid_ppl << 2 * fbuf.height;
380 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
382 /* Determine the field to display, and deinterlace if possible */
383 if( pvr2_state.interlaced ) {
384 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
385 fbuf.height = fbuf.height << 1;
386 fbuf.rowstride = vid_ppl << 2;
387 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
389 /* Just display the field as is, folks. This is slightly tricky -
390 * we pick the field based on which frame is about to come through,
391 * which may not be the same as the odd_even_field.
393 gboolean oddfield = pvr2_state.odd_even_field;
394 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
395 oddfield = !oddfield;
398 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
400 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
404 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
406 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
407 fbuf.inverted = FALSE;
408 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
410 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
412 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
414 displayed_render_buffer = rbuf;
416 display_driver->display_render_buffer( rbuf );
422 * This has to handle every single register individually as they all get masked
423 * off differently (and its easier to do it at write time)
425 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
427 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
428 MMIO_WRITE( PVR2, reg, val );
435 case GUNPOS: /* Read only registers */
438 val &= 0x00000007; /* Do stuff? */
439 MMIO_WRITE( PVR2, reg, val );
441 case RENDER_START: /* Don't really care what value */
442 if( pvr2_state.save_next_render_filename != NULL ) {
443 if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
444 INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
446 g_free( pvr2_state.save_next_render_filename );
447 pvr2_state.save_next_render_filename = NULL;
449 render_buffer_t buffer = pvr2_next_render_buffer();
450 if( buffer != NULL ) {
451 pvr2_render_scene( buffer );
453 asic_event( EVENT_PVR_RENDER_DONE );
455 case RENDER_POLYBASE:
456 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
459 MMIO_WRITE( PVR2, reg, val&0x00010101 );
462 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
465 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
468 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
471 MMIO_WRITE( PVR2, reg, val&0x000001FF );
475 MMIO_WRITE( PVR2, reg, val );
476 pvr2_update_raster_posn(sh4r.slice_cycle);
479 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
480 pvr2_update_raster_posn(sh4r.slice_cycle);
483 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
487 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
490 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
493 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
496 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
497 pvr2_state.irq_hpos_line = val & 0x03FF;
498 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
499 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
500 switch( pvr2_state.irq_hpos_mode ) {
501 case 3: /* Reserved - treat as 0 */
502 case 0: /* Once per frame at specified line */
503 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
505 case 2: /* Once per line - as per-line-count */
506 pvr2_state.irq_hpos_line = 1;
507 pvr2_state.irq_hpos_mode = 1;
508 case 1: /* Once per N lines */
509 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
510 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
511 pvr2_state.irq_hpos_line_count;
512 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
513 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
515 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
517 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
518 pvr2_state.irq_hpos_time_ns );
521 val = val & 0x03FF03FF;
522 pvr2_state.irq_vpos1 = (val >> 16);
523 pvr2_state.irq_vpos2 = val & 0x03FF;
524 pvr2_update_raster_posn(sh4r.slice_cycle);
525 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
526 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
527 MMIO_WRITE( PVR2, reg, val );
529 case RENDER_NEARCLIP:
530 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
533 MMIO_WRITE( PVR2, reg, val&0x000001FF );
536 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
539 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
542 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
545 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
548 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
551 MMIO_WRITE( PVR2, reg, val&0x000000FF );
554 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
557 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
559 case RENDER_FOGTBLCOL:
560 case RENDER_FOGVRTCOL:
561 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
563 case RENDER_FOGCOEFF:
564 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
568 MMIO_WRITE( PVR2, reg, val );
571 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
574 MMIO_WRITE( PVR2, reg, val&0x00000003 );
577 /********** CRTC registers *************/
580 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
583 val = val & 0x03FF03FF;
584 MMIO_WRITE( PVR2, reg, val );
585 pvr2_update_raster_posn(sh4r.slice_cycle);
586 pvr2_state.total_lines = (val >> 16) + 1;
587 pvr2_state.line_size = (val & 0x03FF) + 1;
588 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
589 pvr2_state.retrace_end_line = 0x2A;
590 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
591 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
592 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
593 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
594 pvr2_state.irq_hpos_time_ns );
597 MMIO_WRITE( PVR2, reg, val&0x000003FF );
598 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
601 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
602 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
603 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
606 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
610 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
611 MMIO_WRITE( PVR2, reg, val );
614 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
617 /*********** Tile accelerator registers ***********/
620 /* Readonly registers */
625 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
627 case RENDER_TILEBASE:
630 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
633 MMIO_WRITE( PVR2, reg, val&0x000F003F );
636 MMIO_WRITE( PVR2, reg, val&0x00133333 );
639 if( val & 0x80000000 )
644 /**************** Scaler registers? ****************/
646 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
650 val = val & 0x00FFFFF8;
651 MMIO_WRITE( PVR2, reg, val );
652 pvr2_yuv_init( val );
655 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
656 pvr2_yuv_set_config(val);
659 /**************** Unknowns ***************/
661 MMIO_WRITE( PVR2, reg, val&0x000007FF );
664 MMIO_WRITE( PVR2, reg, val&0x00000007 );
667 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
670 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
673 MMIO_WRITE( PVR2, reg, val&0x000000FF );
676 MMIO_WRITE( PVR2, reg, val&0x00000001 );
682 * Calculate the current read value of the syncstat register, using
683 * the current SH4 clock time as an offset from the last timeslice.
684 * The register reads (LSB to MSB) as:
685 * 0..9 Current scan line
686 * 10 Odd/even field (1 = odd, 0 = even)
687 * 11 Display active (including border and overscan)
688 * 12 Horizontal sync off
689 * 13 Vertical sync off
690 * Note this method is probably incorrect for anything other than straight
691 * interlaced PAL/NTSC, and needs further testing.
693 uint32_t pvr2_get_sync_status()
695 pvr2_update_raster_posn(sh4r.slice_cycle);
696 uint32_t result = pvr2_state.line_count;
698 if( pvr2_state.odd_even_field ) {
701 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
702 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
703 result |= 0x1000; /* !HSYNC */
705 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
706 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
707 result |= 0x2800; /* Display active */
709 result |= 0x2000; /* Front porch */
713 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
714 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
715 result |= 0x3800; /* Display active */
720 result |= 0x1000; /* Back porch */
727 * Schedule a "scanline" event. This actually goes off at
728 * 2 * line in even fields and 2 * line + 1 in odd fields.
729 * Otherwise this behaves as per pvr2_schedule_line_event().
730 * The raster position should be updated before calling this
732 * @param eventid Event to fire at the specified time
733 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
735 * @param hpos_ns Nanoseconds into the line at which to fire.
737 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
739 uint32_t field = pvr2_state.odd_even_field;
740 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
743 if( hpos_ns > pvr2_state.line_time_ns ) {
744 hpos_ns = pvr2_state.line_time_ns;
752 if( line < pvr2_state.total_lines ) {
755 if( line <= pvr2_state.line_count ) {
756 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
758 lines = (line - pvr2_state.line_count);
760 if( lines <= minimum_lines ) {
761 lines += pvr2_state.total_lines;
763 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
764 event_schedule( eventid, time );
766 event_cancel( eventid );
770 MMIO_REGION_READ_FN( PVR2, reg )
774 return pvr2_get_sync_status();
776 return MMIO_READ( PVR2, reg );
780 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
782 MMIO_WRITE( PVR2PAL, reg, val );
783 pvr2_state.palette_changed = TRUE;
786 void pvr2_check_palette_changed()
788 if( pvr2_state.palette_changed ) {
789 texcache_invalidate_palette();
790 pvr2_state.palette_changed = FALSE;
794 MMIO_REGION_READ_DEFFN( PVR2PAL );
796 void pvr2_set_base_address( uint32_t base )
798 mmio_region_PVR2_write( DISP_ADDR1, base );
804 int32_t mmio_region_PVR2TA_read( uint32_t reg )
809 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
811 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
815 * Find the render buffer corresponding to the requested output frame
816 * (does not consider texture renders).
817 * @return the render_buffer if found, or null if no such buffer.
819 * Note: Currently does not consider "partial matches", ie partial
820 * frame overlap - it probably needs to do this.
822 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
825 for( i=0; i<render_buffer_count; i++ ) {
826 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
827 return render_buffers[i];
834 * Allocate a render buffer with the requested parameters.
835 * The order of preference is:
836 * 1. An existing buffer with the same address. (not flushed unless the new
837 * size is smaller than the old one).
838 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
839 * is flushed to vram.
840 * 3. A new buffer if one can be created.
841 * 4. The current display buff
842 * Note: The current display field(s) will never be overwritten except as a last
845 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
848 render_buffer_t result = NULL;
850 /* Check existing buffers for an available buffer */
851 for( i=0; i<render_buffer_count; i++ ) {
852 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
853 /* needs to be the right dimensions */
854 if( render_buffers[i]->address == render_addr ) {
855 if( displayed_render_buffer == render_buffers[i] ) {
856 /* Same address, but we can't use it because the
857 * display has it. Mark it as unaddressed for later.
859 render_buffers[i]->address = -1;
862 result = render_buffers[i];
865 } else if( render_buffers[i]->address == -1 && result == NULL &&
866 displayed_render_buffer != render_buffers[i] ) {
867 result = render_buffers[i];
870 } else if( render_buffers[i]->address == render_addr ) {
871 /* right address, wrong size - if it's larger, flush it, otherwise
873 if( render_buffers[i]->width * render_buffers[i]->height >
875 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
877 render_buffers[i]->address = -1;
881 /* Nothing available - make one */
882 if( result == NULL ) {
883 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
884 /* maximum buffers reached - need to throw one away */
885 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
886 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
887 for( i=0; i<render_buffer_count; i++ ) {
888 if( render_buffers[i]->address != field1_addr &&
889 render_buffers[i]->address != field2_addr &&
890 render_buffers[i] != displayed_render_buffer ) {
891 /* Never throw away the current "front buffer(s)" */
892 result = render_buffers[i];
893 if( !result->flushed ) {
894 pvr2_render_buffer_copy_to_sh4( result );
896 if( result->width != width || result->height != height ) {
897 display_driver->destroy_render_buffer(render_buffers[i]);
898 result = display_driver->create_render_buffer(width,height);
899 render_buffers[i] = result;
905 result = display_driver->create_render_buffer(width,height);
906 if( result != NULL ) {
907 render_buffers[render_buffer_count++] = result;
912 if( result != NULL ) {
913 result->address = render_addr;
919 * Allocate a render buffer based on the current rendering settings
921 render_buffer_t pvr2_next_render_buffer()
923 render_buffer_t result = NULL;
924 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
925 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
926 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
927 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
929 if( render_addr & 0x01000000 ) { /* vram64 */
930 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
931 } else { /* vram32 */
932 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
936 int colour_format = pvr2_render_colour_format[render_mode&0x07];
937 pvr2_render_getsize( &width, &height );
939 result = pvr2_alloc_render_buffer( render_addr, width, height );
940 /* Setup the buffer */
941 if( result != NULL ) {
942 result->rowstride = render_stride;
943 result->colour_format = colour_format;
944 result->scale = render_scale;
945 result->size = width * height * colour_formats[colour_format].bpp;
946 result->flushed = FALSE;
947 result->inverted = TRUE; // render buffers are inverted normally
952 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
954 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
955 if( result != NULL ) {
956 int bpp = colour_formats[frame->colour_format].bpp;
957 result->rowstride = frame->rowstride;
958 result->colour_format = frame->colour_format;
959 result->scale = 0x400;
960 result->size = frame->width * frame->height * bpp;
961 result->flushed = TRUE;
962 result->inverted = frame->inverted;
963 display_driver->load_frame_buffer( frame, result );
970 * Invalidate any caching on the supplied address. Specifically, if it falls
971 * within any of the render buffers, flush the buffer back to PVR2 ram.
973 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
976 address = address & 0x1FFFFFFF;
977 for( i=0; i<render_buffer_count; i++ ) {
978 uint32_t bufaddr = render_buffers[i]->address;
979 if( bufaddr != -1 && bufaddr <= address &&
980 (bufaddr + render_buffers[i]->size) > address ) {
981 if( !render_buffers[i]->flushed ) {
982 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
983 render_buffers[i]->flushed = TRUE;
986 render_buffers[i]->address = -1; /* Invalid */
988 return TRUE; /* should never have overlapping buffers */
.