2 * $Id: sh4.c,v 1.7 2007-11-08 11:54:16 nkeynes Exp $
4 * SH4 parent module for all CPU modes and SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "dreamcast.h"
24 #include "sh4/sh4core.h"
25 #include "sh4/sh4mmio.h"
27 #include "sh4/xltcache.h"
28 #include "sh4/sh4stat.h"
33 #define EXV_EXCEPTION 0x100 /* General exception vector */
34 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
35 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
37 void sh4_init( void );
38 void sh4_xlat_init( void );
39 void sh4_reset( void );
40 void sh4_start( void );
41 void sh4_stop( void );
42 void sh4_save_state( FILE *f );
43 int sh4_load_state( FILE *f );
45 uint32_t sh4_run_slice( uint32_t );
46 uint32_t sh4_xlat_run_slice( uint32_t );
48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
49 NULL, sh4_run_slice, sh4_stop,
50 sh4_save_state, sh4_load_state };
52 struct sh4_registers sh4r;
53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
54 int sh4_breakpoint_count = 0;
55 extern sh4ptr_t sh4_main_ram;
56 static gboolean sh4_use_translator = FALSE;
58 void sh4_set_use_xlat( gboolean use )
60 // No-op if the translator was not built
65 sh4_module.run_time_slice = sh4_xlat_run_slice;
67 sh4_module.run_time_slice = sh4_run_slice;
69 sh4_use_translator = use;
75 register_io_regions( mmio_list_sh4mmio );
76 sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
83 if( sh4_use_translator ) {
87 /* zero everything out, for the sake of having a consistent state. */
88 memset( &sh4r, 0, sizeof(sh4r) );
90 /* Resume running if we were halted */
91 sh4r.sh4_state = SH4_STATE_RUNNING;
94 sh4r.new_pc= 0xA0000002;
95 sh4r.vbr = 0x00000000;
96 sh4r.fpscr = 0x00040001;
98 sh4r.fr_bank = &sh4r.fr[0][0];
100 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
101 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
103 /* Peripheral modules */
114 if( sh4_use_translator ) {
115 /* If we were running with the translator, update new_pc and in_delay_slot */
116 sh4r.new_pc = sh4r.pc+2;
117 sh4r.in_delay_slot = FALSE;
122 void sh4_save_state( FILE *f )
124 if( sh4_use_translator ) {
125 /* If we were running with the translator, update new_pc and in_delay_slot */
126 sh4r.new_pc = sh4r.pc+2;
127 sh4r.in_delay_slot = FALSE;
130 fwrite( &sh4r, sizeof(sh4r), 1, f );
132 INTC_save_state( f );
134 SCIF_save_state( f );
137 int sh4_load_state( FILE * f )
139 if( sh4_use_translator ) {
142 fread( &sh4r, sizeof(sh4r), 1, f );
143 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
145 INTC_load_state( f );
147 return SCIF_load_state( f );
151 void sh4_set_breakpoint( uint32_t pc, int type )
153 sh4_breakpoints[sh4_breakpoint_count].address = pc;
154 sh4_breakpoints[sh4_breakpoint_count].type = type;
155 sh4_breakpoint_count++;
158 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
162 for( i=0; i<sh4_breakpoint_count; i++ ) {
163 if( sh4_breakpoints[i].address == pc &&
164 sh4_breakpoints[i].type == type ) {
165 while( ++i < sh4_breakpoint_count ) {
166 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
167 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
169 sh4_breakpoint_count--;
176 int sh4_get_breakpoint( uint32_t pc )
179 for( i=0; i<sh4_breakpoint_count; i++ ) {
180 if( sh4_breakpoints[i].address == pc )
181 return sh4_breakpoints[i].type;
186 void sh4_set_pc( int pc )
193 /******************************* Support methods ***************************/
195 static void sh4_switch_banks( )
199 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
200 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
201 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
204 void sh4_write_sr( uint32_t newval )
206 if( (newval ^ sh4r.sr) & SR_RB )
209 sh4r.t = (newval&SR_T) ? 1 : 0;
210 sh4r.s = (newval&SR_S) ? 1 : 0;
211 sh4r.m = (newval&SR_M) ? 1 : 0;
212 sh4r.q = (newval&SR_Q) ? 1 : 0;
216 uint32_t sh4_read_sr( void )
218 /* synchronize sh4r.sr with the various bitflags */
219 sh4r.sr &= SR_MQSTMASK;
220 if( sh4r.t ) sh4r.sr |= SR_T;
221 if( sh4r.s ) sh4r.sr |= SR_S;
222 if( sh4r.m ) sh4r.sr |= SR_M;
223 if( sh4r.q ) sh4r.sr |= SR_Q;
229 #define RAISE( x, v ) do{ \
230 if( sh4r.vbr == 0 ) { \
231 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
232 dreamcast_stop(); return FALSE; \
234 sh4r.spc = sh4r.pc; \
235 sh4r.ssr = sh4_read_sr(); \
236 sh4r.sgr = sh4r.r[15]; \
237 MMIO_WRITE(MMU,EXPEVT,x); \
238 sh4r.pc = sh4r.vbr + v; \
239 sh4r.new_pc = sh4r.pc + 2; \
240 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
241 if( sh4r.in_delay_slot ) { \
242 sh4r.in_delay_slot = 0; \
246 return TRUE; } while(0)
249 * Raise a general CPU exception for the specified exception code.
250 * (NOT for TRAPA or TLB exceptions)
252 gboolean sh4_raise_exception( int code )
254 RAISE( code, EXV_EXCEPTION );
257 gboolean sh4_raise_trap( int trap )
259 MMIO_WRITE( MMU, TRA, trap<<2 );
260 return sh4_raise_exception( EXC_TRAP );
263 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
264 if( sh4r.in_delay_slot ) {
265 return sh4_raise_exception(slot_code);
267 return sh4_raise_exception(normal_code);
271 gboolean sh4_raise_tlb_exception( int code )
273 RAISE( code, EXV_TLBMISS );
276 void sh4_accept_interrupt( void )
278 uint32_t code = intc_accept_interrupt();
279 sh4r.ssr = sh4_read_sr();
281 sh4r.sgr = sh4r.r[15];
282 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
283 MMIO_WRITE( MMU, INTEVT, code );
284 sh4r.pc = sh4r.vbr + 0x600;
285 sh4r.new_pc = sh4r.pc + 2;
286 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
289 void signsat48( void )
291 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
292 sh4r.mac = 0xFFFF800000000000LL;
293 else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
294 sh4r.mac = 0x00007FFFFFFFFFFFLL;
297 void sh4_fsca( uint32_t anglei, float *fr )
299 float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
306 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
307 sh4r.sh4_state = SH4_STATE_STANDBY;
309 sh4r.sh4_state = SH4_STATE_SLEEP;
314 * Compute the matrix tranform of fv given the matrix xf.
315 * Both fv and xf are word-swapped as per the sh4r.fr banks
317 void sh4_ftrv( float *target, float *xf )
319 float fv[4] = { target[1], target[0], target[3], target[2] };
320 target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
321 xf[9]*fv[2] + xf[13]*fv[3];
322 target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
323 xf[8]*fv[2] + xf[12]*fv[3];
324 target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
325 xf[11]*fv[2] + xf[15]*fv[3];
326 target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
327 xf[10]*fv[2] + xf[14]*fv[3];
.