2 * $Id: pvr2.c,v 1.37 2007-01-11 12:14:57 nkeynes Exp $
4 * PVR2 (Video) Core module implementation and MMIO registers.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #define MODULE pvr2_module
26 #include "pvr2/pvr2.h"
27 #include "sh4/sh4core.h"
29 #include "pvr2/pvr2mmio.h"
33 static void pvr2_init( void );
34 static void pvr2_reset( void );
35 static uint32_t pvr2_run_slice( uint32_t );
36 static void pvr2_save_state( FILE *f );
37 static int pvr2_load_state( FILE *f );
38 static void pvr2_update_raster_posn( uint32_t nanosecs );
39 static void pvr2_schedule_line_event( int eventid, int line );
40 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines );
41 uint32_t pvr2_get_sync_status();
43 void pvr2_display_frame( void );
45 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
47 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
49 pvr2_save_state, pvr2_load_state };
52 display_driver_t display_driver = NULL;
55 int fields_per_second;
61 struct video_timing pal_timing = { 50, 625, 65, 31945 };
62 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
67 uint32_t line_remainder;
68 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
71 uint32_t odd_even_field; /* 1 = odd, 0 = even */
77 uint32_t line_time_ns;
79 uint32_t hsync_width_ns;
80 uint32_t front_porch_ns;
81 uint32_t back_porch_ns;
82 uint32_t retrace_start_line;
83 uint32_t retrace_end_line;
85 struct video_timing timing;
88 struct video_buffer video_buffer[2];
89 int video_buffer_idx = 0;
92 * Event handler for the retrace callback (fires on line 0 normally)
94 static void pvr2_retrace_callback( int eventid ) {
95 asic_event( eventid );
96 pvr2_update_raster_posn(sh4r.slice_cycle);
97 pvr2_schedule_line_event( EVENT_RETRACE, 0 );
101 * Event handler for the scanline callbacks. Fires the corresponding
102 * ASIC event, and resets the timer for the next field.
104 static void pvr2_scanline_callback( int eventid ) {
105 asic_event( eventid );
106 pvr2_update_raster_posn(sh4r.slice_cycle);
107 if( eventid == EVENT_SCANLINE1 ) {
108 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1 );
110 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1 );
114 static void pvr2_init( void )
116 register_io_region( &mmio_region_PVR2 );
117 register_io_region( &mmio_region_PVR2PAL );
118 register_io_region( &mmio_region_PVR2TA );
119 register_event_callback( EVENT_RETRACE, pvr2_retrace_callback );
120 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
121 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
122 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
128 static void pvr2_reset( void )
130 pvr2_state.line_count = 0;
131 pvr2_state.line_remainder = 0;
132 pvr2_state.cycles_run = 0;
133 pvr2_state.irq_vpos1 = 0;
134 pvr2_state.irq_vpos2 = 0;
135 pvr2_state.timing = ntsc_timing;
136 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
137 pvr2_state.back_porch_ns = 4000;
138 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
139 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
140 video_buffer_idx = 0;
147 static void pvr2_save_state( FILE *f )
149 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
150 pvr2_ta_save_state( f );
153 static int pvr2_load_state( FILE *f )
155 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
157 return pvr2_ta_load_state(f);
161 * Update the current raster position to the given number of nanoseconds,
162 * relative to the last time slice. (ie the raster will be adjusted forward
163 * by nanosecs - nanosecs_already_run_this_timeslice)
165 static void pvr2_update_raster_posn( uint32_t nanosecs )
167 uint32_t old_line_count = pvr2_state.line_count;
168 if( pvr2_state.line_time_ns == 0 ) {
169 return; /* do nothing */
171 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
172 pvr2_state.cycles_run = nanosecs;
173 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
174 pvr2_state.line_count ++;
175 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
178 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
179 pvr2_state.line_count -= pvr2_state.total_lines;
180 if( pvr2_state.interlaced ) {
181 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
184 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
185 (old_line_count < pvr2_state.retrace_end_line ||
186 old_line_count > pvr2_state.line_count) ) {
187 pvr2_display_frame();
191 static uint32_t pvr2_run_slice( uint32_t nanosecs )
193 pvr2_update_raster_posn( nanosecs );
194 pvr2_state.cycles_run = 0;
198 int pvr2_get_frame_count()
200 return pvr2_state.frame_count;
204 * Display the next frame, copying the current contents of video ram to
205 * the window. If the video configuration has changed, first recompute the
206 * new frame size/depth.
208 void pvr2_display_frame( void )
210 uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
212 int dispsize = MMIO_READ( PVR2, DISP_SIZE );
213 int dispmode = MMIO_READ( PVR2, DISP_MODE );
214 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
215 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
216 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
217 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
218 gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
219 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
220 video_buffer_t buffer = &video_buffer[video_buffer_idx];
221 video_buffer_idx = !video_buffer_idx;
222 video_buffer_t last = &video_buffer[video_buffer_idx];
223 buffer->rowstride = (vid_ppl + vid_stride) << 2;
224 buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
225 buffer->vres = vid_lpf;
226 if( interlaced ) buffer->vres <<= 1;
227 switch( (dispmode & DISPMODE_COL) >> 2 ) {
229 buffer->colour_format = COLFMT_ARGB1555;
230 buffer->hres = vid_ppl << 1;
233 buffer->colour_format = COLFMT_RGB565;
234 buffer->hres = vid_ppl << 1;
237 buffer->colour_format = COLFMT_RGB888;
238 buffer->hres = (vid_ppl << 2) / 3;
241 buffer->colour_format = COLFMT_ARGB8888;
242 buffer->hres = vid_ppl;
246 if( buffer->hres <=8 )
248 if( buffer->vres <=8 )
250 if( display_driver != NULL ) {
251 if( buffer->hres != last->hres ||
252 buffer->vres != last->vres ||
253 buffer->colour_format != last->colour_format) {
254 display_driver->set_display_format( buffer->hres, buffer->vres,
255 buffer->colour_format );
258 display_driver->display_blank_frame( 0 );
259 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
260 uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
261 display_driver->display_blank_frame( colour );
262 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
263 display_driver->display_frame( buffer );
266 pvr2_state.frame_count++;
270 * This has to handle every single register individually as they all get masked
271 * off differently (and its easier to do it at write time)
273 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
275 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
276 MMIO_WRITE( PVR2, reg, val );
283 case GUNPOS: /* Read only registers */
286 val &= 0x00000007; /* Do stuff? */
287 MMIO_WRITE( PVR2, reg, val );
290 if( val == 0xFFFFFFFF || val == 0x00000001 )
293 case RENDER_POLYBASE:
294 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
297 MMIO_WRITE( PVR2, reg, val&0x00010101 );
300 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
303 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
306 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
309 MMIO_WRITE( PVR2, reg, val&0x000001FF );
313 MMIO_WRITE( PVR2, reg, val );
314 pvr2_update_raster_posn(sh4r.slice_cycle);
315 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||
316 pvr2_state.line_count < pvr2_state.retrace_end_line ) {
317 pvr2_display_frame();
321 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
324 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
328 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
331 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
334 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
337 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
340 val = val & 0x03FF03FF;
341 pvr2_state.irq_vpos1 = (val >> 16);
342 pvr2_state.irq_vpos2 = val & 0x03FF;
343 pvr2_update_raster_posn(sh4r.slice_cycle);
344 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
345 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
346 MMIO_WRITE( PVR2, reg, val );
348 case RENDER_NEARCLIP:
349 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
352 MMIO_WRITE( PVR2, reg, val&0x000001FF );
355 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
358 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
361 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
364 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
367 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
370 MMIO_WRITE( PVR2, reg, val&0x000000FF );
373 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
376 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
378 case RENDER_FOGTBLCOL:
379 case RENDER_FOGVRTCOL:
380 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
382 case RENDER_FOGCOEFF:
383 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
387 MMIO_WRITE( PVR2, reg, val );
390 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
393 MMIO_WRITE( PVR2, reg, val&0x00000003 );
396 /********** CRTC registers *************/
399 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
402 val = val & 0x03FF03FF;
403 MMIO_WRITE( PVR2, reg, val );
404 pvr2_update_raster_posn(sh4r.slice_cycle);
405 pvr2_state.total_lines = (val >> 16) + 1;
406 pvr2_state.line_size = (val & 0x03FF) + 1;
407 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
408 pvr2_state.retrace_end_line = 0x2A;
409 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
410 pvr2_schedule_line_event( EVENT_RETRACE, 0 );
411 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
412 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
415 MMIO_WRITE( PVR2, reg, val&0x000003FF );
416 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
419 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
420 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
421 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
424 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
428 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
429 MMIO_WRITE( PVR2, reg, val );
432 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
435 /*********** Tile accelerator registers ***********/
438 /* Readonly registers */
443 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
445 case RENDER_TILEBASE:
448 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
451 MMIO_WRITE( PVR2, reg, val&0x000F003F );
454 MMIO_WRITE( PVR2, reg, val&0x00133333 );
457 if( val & 0x80000000 )
462 /**************** Scaler registers? ****************/
464 /* KOS suggests bits as follows:
465 * 0: enable vertical scaling
469 DEBUG( "Scaler config set to %08X", val );
470 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
474 MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
477 DEBUG( "YUV config set to %08X", val );
478 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
482 /**************** Unknowns ***************/
484 MMIO_WRITE( PVR2, reg, val&0x000007FF );
487 MMIO_WRITE( PVR2, reg, val&0x00000007 );
490 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
493 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
496 MMIO_WRITE( PVR2, reg, val&0x000000FF );
499 MMIO_WRITE( PVR2, reg, val&0x00000001 );
505 * Calculate the current read value of the syncstat register, using
506 * the current SH4 clock time as an offset from the last timeslice.
507 * The register reads (LSB to MSB) as:
508 * 0..9 Current scan line
509 * 10 Odd/even field (1 = odd, 0 = even)
510 * 11 Display active (including border and overscan)
511 * 12 Horizontal sync off
512 * 13 Vertical sync off
513 * Note this method is probably incorrect for anything other than straight
514 * interlaced PAL/NTSC, and needs further testing.
516 uint32_t pvr2_get_sync_status()
518 pvr2_update_raster_posn(sh4r.slice_cycle);
519 uint32_t result = pvr2_state.line_count;
521 if( pvr2_state.odd_even_field ) {
524 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
525 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
526 result |= 0x1000; /* !HSYNC */
528 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
529 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
530 result |= 0x2800; /* Display active */
532 result |= 0x2000; /* Front porch */
536 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
537 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
538 result |= 0x3800; /* Display active */
543 result |= 0x1000; /* Back porch */
550 * Schedule an event for the start of the given line. If the line is actually
551 * the current line, schedules it for the next field.
552 * The raster position should be updated before calling this method.
554 static void pvr2_schedule_line_event( int eventid, int line )
557 if( line <= pvr2_state.line_count ) {
558 time = (pvr2_state.total_lines - pvr2_state.line_count + line) * pvr2_state.line_time_ns
559 - pvr2_state.line_remainder;
561 time = (line - pvr2_state.line_count) * pvr2_state.line_time_ns - pvr2_state.line_remainder;
564 if( line < pvr2_state.total_lines ) {
565 event_schedule( eventid, time );
567 event_cancel( eventid );
572 * Schedule a "scanline" event. This actually goes off at
573 * 2 * line in even fields and 2 * line + 1 in odd fields.
574 * Otherwise this behaves as per pvr2_schedule_line_event().
575 * The raster position should be updated before calling this
578 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines )
580 uint32_t field = pvr2_state.odd_even_field;
581 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
590 if( line < pvr2_state.total_lines ) {
593 if( line <= pvr2_state.line_count ) {
594 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
596 lines = (line - pvr2_state.line_count);
598 if( lines <= minimum_lines ) {
599 lines += pvr2_state.total_lines;
601 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder;
602 event_schedule( eventid, time );
604 event_cancel( eventid );
608 MMIO_REGION_READ_FN( PVR2, reg )
612 return pvr2_get_sync_status();
614 return MMIO_READ( PVR2, reg );
618 MMIO_REGION_DEFFNS( PVR2PAL )
620 void pvr2_set_base_address( uint32_t base )
622 mmio_region_PVR2_write( DISP_ADDR1, base );
628 int32_t mmio_region_PVR2TA_read( uint32_t reg )
633 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
635 pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
639 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
641 int bank_flag = (destaddr & 0x04) >> 2;
646 destaddr = destaddr & 0x7FFFFF;
647 if( destaddr + length > 0x800000 ) {
648 length = 0x800000 - destaddr;
651 for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
652 texcache_invalidate_page( i );
655 banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
656 banks[1] = banks[0] + 0x100000;
660 /* Handle non-aligned start of source */
661 if( destaddr & 0x03 ) {
662 char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
663 for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
666 bank_flag = !bank_flag;
669 dwsrc = (uint32_t *)src;
670 while( length >= 4 ) {
671 *banks[bank_flag]++ = *dwsrc++;
672 bank_flag = !bank_flag;
676 /* Handle non-aligned end of source */
679 char *dest = (char *)banks[bank_flag];
680 while( length-- > 0 ) {
686 void pvr2_vram_write_invert( sh4addr_t destaddr, char *src, uint32_t length, uint32_t line_length )
688 char *dest = video_base + (destaddr & 0x007FFFFF);
689 char *p = src + length - line_length;
691 memcpy( dest, p, line_length );
697 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
699 int bank_flag = (srcaddr & 0x04) >> 2;
704 srcaddr = srcaddr & 0x7FFFFF;
705 if( srcaddr + length > 0x800000 )
706 length = 0x800000 - srcaddr;
708 banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
709 banks[1] = banks[0] + 0x100000;
713 /* Handle non-aligned start of source */
714 if( srcaddr & 0x03 ) {
715 char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
716 for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
719 bank_flag = !bank_flag;
722 dwdest = (uint32_t *)dest;
723 while( length >= 4 ) {
724 *dwdest++ = *banks[bank_flag]++;
725 bank_flag = !bank_flag;
729 /* Handle non-aligned end of source */
731 dest = (char *)dwdest;
732 char *src = (char *)banks[bank_flag];
733 while( length-- > 0 ) {
739 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f )
742 pvr2_vram64_read( tmp, addr, length );
743 fwrite_dump( tmp, length, f );
.