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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 986:5090104b0963
prev984:a01567058a47
next1014:f5914b2fd0db
author nkeynes
date Tue Feb 24 11:50:17 2009 +0000 (11 years ago)
permissions -rw-r--r--
last change Fix minor warnings
Add explicit casts to mmap() result for platforms where it's not void *...
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/sh4stat.h"
    32 #include "sh4/mmu.h"
    34 #define SH4_CALLTRACE 1
    36 #define MAX_INT 0x7FFFFFFF
    37 #define MIN_INT 0x80000000
    38 #define MAX_INTF 2147483647.0
    39 #define MIN_INTF -2147483648.0
    41 /********************** SH4 Module Definition ****************************/
    43 uint32_t sh4_emulate_run_slice( uint32_t nanosecs ) 
    44 {
    45     int i;
    47     if( sh4_breakpoint_count == 0 ) {
    48 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    49 	    if( SH4_EVENT_PENDING() ) {
    50 		if( sh4r.event_types & PENDING_EVENT ) {
    51 		    event_execute();
    52 		}
    53 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    54 		if( sh4r.event_types & PENDING_IRQ ) {
    55 		    sh4_accept_interrupt();
    56 		}
    57 	    }
    58 	    if( !sh4_execute_instruction() ) {
    59 		break;
    60 	    }
    61 	}
    62     } else {
    63 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    64 	    if( SH4_EVENT_PENDING() ) {
    65 		if( sh4r.event_types & PENDING_EVENT ) {
    66 		    event_execute();
    67 		}
    68 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    69 		if( sh4r.event_types & PENDING_IRQ ) {
    70 		    sh4_accept_interrupt();
    71 		}
    72 	    }
    74 	    if( !sh4_execute_instruction() )
    75 		break;
    76 #ifdef ENABLE_DEBUG_MODE
    77 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    78 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    79 		    break;
    80 		}
    81 	    }
    82 	    if( i != sh4_breakpoint_count ) {
    83 	    	sh4_core_exit( CORE_EXIT_BREAKPOINT );
    84 	    }
    85 #endif	
    86 	}
    87     }
    89     /* If we aborted early, but the cpu is still technically running,
    90      * we're doing a hard abort - cut the timeslice back to what we
    91      * actually executed
    92      */
    93     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
    94 	nanosecs = sh4r.slice_cycle;
    95     }
    96     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
    97 	TMU_run_slice( nanosecs );
    98 	SCIF_run_slice( nanosecs );
    99     }
   100     return nanosecs;
   101 }
   103 /********************** SH4 emulation core  ****************************/
   105 #if(SH4_CALLTRACE == 1)
   106 #define MAX_CALLSTACK 32
   107 static struct call_stack {
   108     sh4addr_t call_addr;
   109     sh4addr_t target_addr;
   110     sh4addr_t stack_pointer;
   111 } call_stack[MAX_CALLSTACK];
   113 static int call_stack_depth = 0;
   114 int sh4_call_trace_on = 0;
   116 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   117 {
   118     if( call_stack_depth < MAX_CALLSTACK ) {
   119 	call_stack[call_stack_depth].call_addr = source;
   120 	call_stack[call_stack_depth].target_addr = dest;
   121 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   122     }
   123     call_stack_depth++;
   124 }
   126 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   127 {
   128     if( call_stack_depth > 0 ) {
   129 	call_stack_depth--;
   130     }
   131 }
   133 void fprint_stack_trace( FILE *f )
   134 {
   135     int i = call_stack_depth -1;
   136     if( i >= MAX_CALLSTACK )
   137 	i = MAX_CALLSTACK - 1;
   138     for( ; i >= 0; i-- ) {
   139 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   140 		 (call_stack_depth - i), call_stack[i].call_addr,
   141 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   142     }
   143 }
   145 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   146 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   147 #else
   148 #define TRACE_CALL( dest, rts ) 
   149 #define TRACE_RETURN( source, dest )
   150 #endif
   152 static gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
   153     if( sh4r.in_delay_slot ) {
   154         sh4_raise_exception(slot_code);
   155     } else {
   156         sh4_raise_exception(normal_code);
   157     }
   158     return TRUE;
   159 }
   162 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) { return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL ); }
   163 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   164 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   165 #define CHECKRALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   166 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   167 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   168 #define CHECKWALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   170 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   171 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }
   172 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { sh4_raise_exception(EXC_SLOT_ILLEGAL); return TRUE; }
   174 #define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)
   175 #define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)
   177 #ifdef HAVE_FRAME_ADDRESS
   178 static FASTCALL __attribute__((noinline)) void *__first_arg(void *a, void *b) { return a; }
   179 #define INIT_EXCEPTIONS(label) goto *__first_arg(&&fnstart,&&label); fnstart:
   180 #define MEM_READ_BYTE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte)((addr), &&except)
   181 #define MEM_READ_WORD( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_word)((addr), &&except)
   182 #define MEM_READ_LONG( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_long)((addr), &&except)
   183 #define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)
   184 #define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)
   185 #define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)
   186 #define MEM_PREFETCH( addr ) ((mem_prefetch_exc_fn_t)ADDRSPACE[(addr)>>12]->prefetch)((addr), &&except)
   187 #else
   188 #define INIT_EXCEPTIONS(label)
   189 #define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)
   190 #define MEM_READ_WORD( addr, val ) val = ADDRSPACE[(addr)>>12]->read_word(addr)
   191 #define MEM_READ_LONG( addr, val ) val = ADDRSPACE[(addr)>>12]->read_long(addr)
   192 #define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)
   193 #define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)
   194 #define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)
   195 #define MEM_PREFETCH( addr ) ADDRSPACE[(addr)>>12]->prefetch(addr)
   196 #endif
   198 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   200 #define MEM_FP_READ( addr, reg ) \
   201     if( IS_FPU_DOUBLESIZE() ) { \
   202 	CHECKRALIGN64(addr); \
   203         if( reg & 1 ) { \
   204             MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \
   205             MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
   206         } else { \
   207             MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   208             MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   209 	} \
   210     } else { \
   211         CHECKRALIGN32(addr); \
   212         MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   213     }
   214 #define MEM_FP_WRITE( addr, reg ) \
   215     if( IS_FPU_DOUBLESIZE() ) { \
   216         CHECKWALIGN64(addr); \
   217         if( reg & 1 ) { \
   218 	    MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \
   219 	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
   220         } else { \
   221 	    MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   222 	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   223 	} \
   224     } else { \
   225     	CHECKWALIGN32(addr); \
   226         MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \
   227     }
   229 #define UNDEF(ir)
   230 #define UNIMP(ir)
   232 /**
   233  * Perform instruction-completion following core exit of a partially completed
   234  * instruction. NOTE: This is only allowed on memory writes, operation is not
   235  * guaranteed in any other case.
   236  */
   237 void sh4_finalize_instruction( void )
   238 {
   239     unsigned short ir;
   240     uint32_t tmp;
   242     assert( IS_IN_ICACHE(sh4r.pc) );
   243     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   245     /**
   246      * Note - we can't take an exit on a control transfer instruction itself,
   247      * which means the exit must have happened in the delay slot. So for these
   248      * cases, finalize the delay slot instruction, and re-execute the control transfer.
   249      *
   250      * For delay slots which modify the argument used in the branch instruction,
   251      * we pretty much just assume that that can't have already happened in an exit case.
   252      */
   254 %%
   255 BRA disp {: 
   256     sh4r.pc += 2; 
   257     sh4_finalize_instruction(); 
   258     sh4r.pc += disp;
   259 :}
   260 BRAF Rn {: 
   261     sh4r.pc += 2; 
   262     tmp = sh4r.r[Rn];
   263     sh4_finalize_instruction(); 
   264     sh4r.pc += tmp;
   265 :}
   266 BSR disp {: 
   267     /* Note: PR is already set */ 
   268     sh4r.pc += 2;
   269     sh4_finalize_instruction();
   270     sh4r.pc += disp;
   271 :}
   272 BSRF Rn {:
   273     /* Note: PR is already set */ 
   274     sh4r.pc += 2;
   275     tmp = sh4r.r[Rn];
   276     sh4_finalize_instruction();
   277     sh4r.pc += tmp;
   278 :}
   279 BF/S disp {: 
   280     sh4r.pc += 2;
   281     sh4_finalize_instruction();
   282     if( !sh4r.t ) {
   283         sh4r.pc += disp;
   284     }
   285 :}
   286 BT/S disp {: 
   287     sh4r.pc += 2;
   288     sh4_finalize_instruction();
   289     if( sh4r.t ) {
   290         sh4r.pc += disp;
   291     }
   292 :}
   293 JMP @Rn {:
   294     sh4r.pc += 2;
   295     tmp = sh4r.r[Rn];
   296     sh4_finalize_instruction();
   297     sh4r.pc = tmp;
   298     sh4r.new_pc = tmp + 2;
   299     sh4r.slice_cycle += sh4_cpu_period;
   300     return;
   301 :}
   302 JSR @Rn {: 
   303     /* Note: PR is already set */ 
   304     sh4r.pc += 2;
   305     tmp = sh4r.r[Rn];
   306     sh4_finalize_instruction();
   307     sh4r.pc = tmp;
   308     sh4r.new_pc = tmp + 2;
   309     sh4r.slice_cycle += sh4_cpu_period;
   310     return;
   311 :}
   312 RTS {: 
   313     sh4r.pc += 2;
   314     sh4_finalize_instruction();
   315     sh4r.pc = sh4r.pr;
   316     sh4r.new_pc = sh4r.pr + 2;
   317     sh4r.slice_cycle += sh4_cpu_period;
   318     return;
   319 :}
   320 RTE {: 
   321     /* SR is already set */
   322     sh4r.pc += 2;
   323     sh4_finalize_instruction();
   324     sh4r.pc = sh4r.spc;
   325     sh4r.new_pc = sh4r.pr + 2;
   326     sh4r.slice_cycle += sh4_cpu_period;
   327     return;
   328 :}
   329 MOV.B Rm, @-Rn {: sh4r.r[Rn]--; :}
   330 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; :}
   331 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; :}
   332 MOV.B @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] ++;  } :}
   333 MOV.W @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
   334 MOV.L @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
   335 %%
   336     sh4r.in_delay_slot = 0;
   337     sh4r.pc += 2;
   338     sh4r.new_pc = sh4r.pc+2;
   339     sh4r.slice_cycle += sh4_cpu_period;
   340 }
   342 #undef UNDEF
   343 #undef UNIMP
   345 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   346 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)
   349 gboolean sh4_execute_instruction( void )
   350 {
   351     uint32_t pc;
   352     unsigned short ir;
   353     uint32_t tmp;
   354     float ftmp;
   355     double dtmp;
   356     int64_t memtmp; // temporary holder for memory reads
   358     INIT_EXCEPTIONS(except)
   360 #define R0 sh4r.r[0]
   361     pc = sh4r.pc;
   362     if( pc > 0xFFFFFF00 ) {
   363 	/* SYSCALL Magic */
   364 	syscall_invoke( pc );
   365 	sh4r.in_delay_slot = 0;
   366 	pc = sh4r.pc = sh4r.pr;
   367 	sh4r.new_pc = sh4r.pc + 2;
   368         return TRUE;
   369     }
   370     CHECKRALIGN16(pc);
   372 #ifdef ENABLE_SH4STATS
   373     sh4_stats_add_by_pc(sh4r.pc);
   374 #endif
   376     /* Read instruction */
   377     if( !IS_IN_ICACHE(pc) ) {
   378         gboolean delay_slot = sh4r.in_delay_slot;
   379 	if( !mmu_update_icache(pc) ) {
   380 	    if( delay_slot ) {
   381 	        sh4r.spc -= 2;
   382 	    }
   383 	    // Fault - look for the fault handler
   384 	    if( !mmu_update_icache(sh4r.pc) ) {
   385 		// double fault - halt
   386 		ERROR( "Double fault - halting" );
   387 		sh4_core_exit(CORE_EXIT_HALT);
   388 		return FALSE;
   389 	    }
   390 	}
   391 	pc = sh4r.pc;
   392     }
   393     assert( IS_IN_ICACHE(pc) );
   394     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   396     /* FIXME: This is a bit of a hack, but the PC of the delay slot should not
   397      * be visible until after the instruction has executed (for exception 
   398      * correctness)
   399      */
   400     if( sh4r.in_delay_slot ) {
   401     	sh4r.pc -= 2;
   402     }
   403 %%
   404 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   405 AND #imm, R0 {: R0 &= imm; :}
   406  AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
   407 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   408 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   409 OR #imm, R0  {: R0 |= imm; :}
   410  OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
   411 TAS.B @Rn {:
   412     MEM_READ_BYTE( sh4r.r[Rn], tmp );
   413     sh4r.t = ( tmp == 0 ? 1 : 0 );
   414     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   415 :}
   416 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   417 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   418  TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
   419 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   420 XOR #imm, R0 {: R0 ^= imm; :}
   421  XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
   422 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   424 ROTL Rn {:
   425     sh4r.t = sh4r.r[Rn] >> 31;
   426     sh4r.r[Rn] <<= 1;
   427     sh4r.r[Rn] |= sh4r.t;
   428 :}
   429 ROTR Rn {:
   430     sh4r.t = sh4r.r[Rn] & 0x00000001;
   431     sh4r.r[Rn] >>= 1;
   432     sh4r.r[Rn] |= (sh4r.t << 31);
   433 :}
   434 ROTCL Rn {:
   435     tmp = sh4r.r[Rn] >> 31;
   436     sh4r.r[Rn] <<= 1;
   437     sh4r.r[Rn] |= sh4r.t;
   438     sh4r.t = tmp;
   439 :}
   440 ROTCR Rn {:
   441     tmp = sh4r.r[Rn] & 0x00000001;
   442     sh4r.r[Rn] >>= 1;
   443     sh4r.r[Rn] |= (sh4r.t << 31 );
   444     sh4r.t = tmp;
   445 :}
   446 SHAD Rm, Rn {:
   447     tmp = sh4r.r[Rm];
   448     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   449     else if( (tmp & 0x1F) == 0 )  
   450         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   451     else 
   452 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   453 :}
   454 SHLD Rm, Rn {:
   455     tmp = sh4r.r[Rm];
   456     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   457     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   458     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   459 :}
   460 SHAL Rn {:
   461     sh4r.t = sh4r.r[Rn] >> 31;
   462     sh4r.r[Rn] <<= 1;
   463 :}
   464 SHAR Rn {:
   465     sh4r.t = sh4r.r[Rn] & 0x00000001;
   466     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   467 :}
   468 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   469 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   470 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   471 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   472 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   473 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   474 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   475 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   477 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   478 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   479 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   480 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   481 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   482 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   484 CLRT {: sh4r.t = 0; :}
   485 SETT {: sh4r.t = 1; :}
   486 CLRMAC {: sh4r.mac = 0; :}
   487 LDTLB {: MMU_ldtlb(); :}
   488 CLRS {: sh4r.s = 0; :}
   489 SETS {: sh4r.s = 1; :}
   490 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   491 NOP {: /* NOP */ :}
   493 PREF @Rn {:
   494     MEM_PREFETCH(sh4r.r[Rn]);
   495 :}
   496 OCBI @Rn {: :}
   497 OCBP @Rn {: :}
   498 OCBWB @Rn {: :}
   499 MOVCA.L R0, @Rn {:
   500     tmp = sh4r.r[Rn];
   501     CHECKWALIGN32(tmp);
   502     MEM_WRITE_LONG( tmp, R0 );
   503 :}
   504 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   505 MOV.W Rm, @(R0, Rn) {: 
   506     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   507     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   508 :}
   509 MOV.L Rm, @(R0, Rn) {:
   510     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   511     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   512 :}
   513 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
   514 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   515     MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   516 :}
   517 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   518     MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   519 :}
   520 MOV.L Rm, @(disp, Rn) {:
   521     tmp = sh4r.r[Rn] + disp;
   522     CHECKWALIGN32( tmp );
   523     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   524 :}
   525 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   526 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   527 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   528  MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
   529  MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
   530  MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
   531 MOV.L @(disp, Rm), Rn {:
   532     tmp = sh4r.r[Rm] + disp;
   533     CHECKRALIGN32( tmp );
   534     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   535 :}
   536 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
   537  MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
   538  MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
   539 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   540  MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] ++; } :}
   541  MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
   542  MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
   543 MOV.L @(disp, PC), Rn {:
   544     CHECKSLOTILLEGAL();
   545     tmp = (pc&0xFFFFFFFC) + disp + 4;
   546     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   547 :}
   548 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   549 MOV.W R0, @(disp, GBR) {:
   550     tmp = sh4r.gbr + disp;
   551     CHECKWALIGN16( tmp );
   552     MEM_WRITE_WORD( tmp, R0 );
   553 :}
   554 MOV.L R0, @(disp, GBR) {:
   555     tmp = sh4r.gbr + disp;
   556     CHECKWALIGN32( tmp );
   557     MEM_WRITE_LONG( tmp, R0 );
   558 :}
   559  MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
   560 MOV.W @(disp, GBR), R0 {: 
   561     tmp = sh4r.gbr + disp;
   562     CHECKRALIGN16( tmp );
   563     MEM_READ_WORD( tmp, R0 );
   564 :}
   565 MOV.L @(disp, GBR), R0 {:
   566     tmp = sh4r.gbr + disp;
   567     CHECKRALIGN32( tmp );
   568     MEM_READ_LONG( tmp, R0 );
   569 :}
   570 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   571 MOV.W R0, @(disp, Rn) {: 
   572     tmp = sh4r.r[Rn] + disp;
   573     CHECKWALIGN16( tmp );
   574     MEM_WRITE_WORD( tmp, R0 );
   575 :}
   576  MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
   577 MOV.W @(disp, Rm), R0 {: 
   578     tmp = sh4r.r[Rm] + disp;
   579     CHECKRALIGN16( tmp );
   580     MEM_READ_WORD( tmp, R0 );
   581 :}
   582 MOV.W @(disp, PC), Rn {:
   583     CHECKSLOTILLEGAL();
   584     tmp = pc + 4 + disp;
   585     MEM_READ_WORD( tmp, sh4r.r[Rn] );
   586 :}
   587 MOVA @(disp, PC), R0 {:
   588     CHECKSLOTILLEGAL();
   589     R0 = (pc&0xFFFFFFFC) + disp + 4;
   590 :}
   591 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   593 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
   594 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
   595 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
   596 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
   597 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   598  FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
   599 FMOV FRm, FRn {: 
   600     if( IS_FPU_DOUBLESIZE() )
   601 	DR(FRn) = DR(FRm);
   602     else
   603 	FR(FRn) = FR(FRm);
   604 :}
   606 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   607 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   608 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   609 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   610 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   611 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   612 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   613 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   614 CMP/STR Rm, Rn {: 
   615     /* set T = 1 if any byte in RM & RN is the same */
   616     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   617     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   618              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   619 :}
   621 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   622 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   623 ADDC Rm, Rn {:
   624     tmp = sh4r.r[Rn];
   625     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   626     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   627 :}
   628 ADDV Rm, Rn {:
   629     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   630     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   631     sh4r.r[Rn] = tmp;
   632 :}
   633 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   634 DIV0S Rm, Rn {: 
   635     sh4r.q = sh4r.r[Rn]>>31;
   636     sh4r.m = sh4r.r[Rm]>>31;
   637     sh4r.t = sh4r.q ^ sh4r.m;
   638 :}
   639 DIV1 Rm, Rn {:
   640     /* This is derived from the sh4 manual with some simplifications */
   641     uint32_t tmp0, tmp1, tmp2, dir;
   643     dir = sh4r.q ^ sh4r.m;
   644     sh4r.q = (sh4r.r[Rn] >> 31);
   645     tmp2 = sh4r.r[Rm];
   646     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   647     tmp0 = sh4r.r[Rn];
   648     if( dir ) {
   649          sh4r.r[Rn] += tmp2;
   650          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   651     } else {
   652          sh4r.r[Rn] -= tmp2;
   653          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   654     }
   655     sh4r.q ^= sh4r.m ^ tmp1;
   656     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   657 :}
   658 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   659 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   660 DT Rn {:
   661     sh4r.r[Rn] --;
   662     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   663 :}
   664 MAC.W @Rm+, @Rn+ {:
   665     int32_t stmp;
   666     if( Rm == Rn ) {
   667 	CHECKRALIGN16(sh4r.r[Rn]);
   668 	MEM_READ_WORD( sh4r.r[Rn], tmp );
   669 	stmp = SIGNEXT16(tmp);
   670 	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
   671 	stmp *= SIGNEXT16(tmp);
   672 	sh4r.r[Rn] += 4;
   673     } else {
   674 	CHECKRALIGN16( sh4r.r[Rn] );
   675 	CHECKRALIGN16( sh4r.r[Rm] );
   676 	MEM_READ_WORD(sh4r.r[Rn], tmp);
   677 	stmp = SIGNEXT16(tmp);
   678 	MEM_READ_WORD(sh4r.r[Rm], tmp);
   679 	stmp = stmp * SIGNEXT16(tmp);
   680 	sh4r.r[Rn] += 2;
   681 	sh4r.r[Rm] += 2;
   682     }
   683     if( sh4r.s ) {
   684 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   685 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   686 	    sh4r.mac = 0x000000017FFFFFFFLL;
   687 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   688 	    sh4r.mac = 0x0000000180000000LL;
   689 	} else {
   690 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   691 		((uint32_t)(sh4r.mac + stmp));
   692 	}
   693     } else {
   694 	sh4r.mac += SIGNEXT32(stmp);
   695     }
   696 :}
   697 MAC.L @Rm+, @Rn+ {:
   698     int64_t tmpl;
   699     if( Rm == Rn ) {
   700 	CHECKRALIGN32( sh4r.r[Rn] );
   701 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   702 	tmpl = SIGNEXT32(tmp);
   703 	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   704 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   705 	sh4r.r[Rn] += 8;
   706     } else {
   707 	CHECKRALIGN32( sh4r.r[Rm] );
   708 	CHECKRALIGN32( sh4r.r[Rn] );
   709 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   710 	tmpl = SIGNEXT32(tmp);
   711 	MEM_READ_LONG(sh4r.r[Rm], tmp);
   712 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   713 	sh4r.r[Rn] += 4;
   714 	sh4r.r[Rm] += 4;
   715     }
   716     if( sh4r.s ) {
   717         /* 48-bit Saturation. Yuch */
   718         if( tmpl < (int64_t)0xFFFF800000000000LL )
   719             tmpl = 0xFFFF800000000000LL;
   720         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   721             tmpl = 0x00007FFFFFFFFFFFLL;
   722     }
   723     sh4r.mac = tmpl;
   724 :}
   725 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   726                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   727 MULU.W Rm, Rn {:
   728     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   729                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   730 :}
   731 MULS.W Rm, Rn {:
   732     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   733                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   734 :}
   735 NEGC Rm, Rn {:
   736     tmp = 0 - sh4r.r[Rm];
   737     sh4r.r[Rn] = tmp - sh4r.t;
   738     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   739 :}
   740 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   741 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   742 SUBC Rm, Rn {: 
   743     tmp = sh4r.r[Rn];
   744     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   745     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   746 :}
   748 BRAF Rn {:
   749      CHECKSLOTILLEGAL();
   750      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   751      sh4r.in_delay_slot = 1;
   752      sh4r.pc = sh4r.new_pc;
   753      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   754      return TRUE;
   755 :}
   756 BSRF Rn {:
   757      CHECKSLOTILLEGAL();
   758      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   759      sh4r.in_delay_slot = 1;
   760      sh4r.pr = sh4r.pc + 4;
   761      sh4r.pc = sh4r.new_pc;
   762      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   763      TRACE_CALL( pc, sh4r.new_pc );
   764      return TRUE;
   765 :}
   766 BT disp {:
   767     CHECKSLOTILLEGAL();
   768     if( sh4r.t ) {
   769         CHECKDEST( sh4r.pc + disp + 4 )
   770         sh4r.pc += disp + 4;
   771         sh4r.new_pc = sh4r.pc + 2;
   772         return TRUE;
   773     }
   774 :}
   775 BF disp {:
   776     CHECKSLOTILLEGAL();
   777     if( !sh4r.t ) {
   778         CHECKDEST( sh4r.pc + disp + 4 )
   779         sh4r.pc += disp + 4;
   780         sh4r.new_pc = sh4r.pc + 2;
   781         return TRUE;
   782     }
   783 :}
   784 BT/S disp {:
   785     CHECKSLOTILLEGAL();
   786     if( sh4r.t ) {
   787         CHECKDEST( sh4r.pc + disp + 4 )
   788         sh4r.in_delay_slot = 1;
   789         sh4r.pc = sh4r.new_pc;
   790         sh4r.new_pc = pc + disp + 4;
   791         sh4r.in_delay_slot = 1;
   792         return TRUE;
   793     }
   794 :}
   795 BF/S disp {:
   796     CHECKSLOTILLEGAL();
   797     if( !sh4r.t ) {
   798         CHECKDEST( sh4r.pc + disp + 4 )
   799         sh4r.in_delay_slot = 1;
   800         sh4r.pc = sh4r.new_pc;
   801         sh4r.new_pc = pc + disp + 4;
   802         return TRUE;
   803     }
   804 :}
   805 BRA disp {:
   806     CHECKSLOTILLEGAL();
   807     CHECKDEST( sh4r.pc + disp + 4 );
   808     sh4r.in_delay_slot = 1;
   809     sh4r.pc = sh4r.new_pc;
   810     sh4r.new_pc = pc + 4 + disp;
   811     return TRUE;
   812 :}
   813 BSR disp {:
   814     CHECKDEST( sh4r.pc + disp + 4 );
   815     CHECKSLOTILLEGAL();
   816     sh4r.in_delay_slot = 1;
   817     sh4r.pr = pc + 4;
   818     sh4r.pc = sh4r.new_pc;
   819     sh4r.new_pc = pc + 4 + disp;
   820     TRACE_CALL( pc, sh4r.new_pc );
   821     return TRUE;
   822 :}
   823 TRAPA #imm {:
   824     CHECKSLOTILLEGAL();
   825     sh4r.pc += 2;
   826     sh4_raise_trap( imm );
   827     return TRUE;
   828 :}
   829 RTS {: 
   830     CHECKSLOTILLEGAL();
   831     CHECKDEST( sh4r.pr );
   832     sh4r.in_delay_slot = 1;
   833     sh4r.pc = sh4r.new_pc;
   834     sh4r.new_pc = sh4r.pr;
   835     TRACE_RETURN( pc, sh4r.new_pc );
   836     return TRUE;
   837 :}
   838 SLEEP {:
   839     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   840 	sh4r.sh4_state = SH4_STATE_STANDBY;
   841     } else {
   842 	sh4r.sh4_state = SH4_STATE_SLEEP;
   843     }
   844     return FALSE; /* Halt CPU */
   845 :}
   846 RTE {:
   847     CHECKPRIV();
   848     CHECKDEST( sh4r.spc );
   849     CHECKSLOTILLEGAL();
   850     sh4r.in_delay_slot = 1;
   851     sh4r.pc = sh4r.new_pc;
   852     sh4r.new_pc = sh4r.spc;
   853     sh4_write_sr( sh4r.ssr );
   854     return TRUE;
   855 :}
   856 JMP @Rn {:
   857     CHECKDEST( sh4r.r[Rn] );
   858     CHECKSLOTILLEGAL();
   859     sh4r.in_delay_slot = 1;
   860     sh4r.pc = sh4r.new_pc;
   861     sh4r.new_pc = sh4r.r[Rn];
   862     return TRUE;
   863 :}
   864 JSR @Rn {:
   865     CHECKDEST( sh4r.r[Rn] );
   866     CHECKSLOTILLEGAL();
   867     sh4r.in_delay_slot = 1;
   868     sh4r.pc = sh4r.new_pc;
   869     sh4r.new_pc = sh4r.r[Rn];
   870     sh4r.pr = pc + 4;
   871     TRACE_CALL( pc, sh4r.new_pc );
   872     return TRUE;
   873 :}
   874 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   875 STS.L MACH, @-Rn {:
   876     CHECKWALIGN32( sh4r.r[Rn] );
   877     MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   878     sh4r.r[Rn] -= 4;
   879 :}
   880 STC.L SR, @-Rn {:
   881     CHECKPRIV();
   882     CHECKWALIGN32( sh4r.r[Rn] );
   883     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   884     sh4r.r[Rn] -= 4;
   885 :}
   886 LDS.L @Rm+, MACH {:
   887     CHECKRALIGN32( sh4r.r[Rm] );
   888     MEM_READ_LONG(sh4r.r[Rm], tmp);
   889     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   890 	(((uint64_t)tmp)<<32);
   891     sh4r.r[Rm] += 4;
   892 :}
   893 LDC.L @Rm+, SR {:
   894     CHECKSLOTILLEGAL();
   895     CHECKPRIV();
   896     CHECKWALIGN32( sh4r.r[Rm] );
   897     MEM_READ_LONG(sh4r.r[Rm], tmp);
   898     sh4_write_sr( tmp );
   899     sh4r.r[Rm] +=4;
   900 :}
   901 LDS Rm, MACH {:
   902     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   903                (((uint64_t)sh4r.r[Rm])<<32);
   904 :}
   905 LDC Rm, SR {:
   906     CHECKSLOTILLEGAL();
   907     CHECKPRIV();
   908     sh4_write_sr( sh4r.r[Rm] );
   909 :}
   910 LDC Rm, SGR {:
   911     CHECKPRIV();
   912     sh4r.sgr = sh4r.r[Rm];
   913 :}
   914 LDC.L @Rm+, SGR {:
   915     CHECKPRIV();
   916     CHECKRALIGN32( sh4r.r[Rm] );
   917     MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
   918     sh4r.r[Rm] +=4;
   919 :}
   920 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   921 STS.L MACL, @-Rn {:
   922     CHECKWALIGN32( sh4r.r[Rn] );
   923     MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   924     sh4r.r[Rn] -= 4;
   925 :}
   926 STC.L GBR, @-Rn {:
   927     CHECKWALIGN32( sh4r.r[Rn] );
   928     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   929     sh4r.r[Rn] -= 4;
   930 :}
   931 LDS.L @Rm+, MACL {:
   932     CHECKRALIGN32( sh4r.r[Rm] );
   933     MEM_READ_LONG(sh4r.r[Rm], tmp);
   934     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   935                (uint64_t)((uint32_t)tmp);
   936     sh4r.r[Rm] += 4;
   937 :}
   938 LDC.L @Rm+, GBR {:
   939     CHECKRALIGN32( sh4r.r[Rm] );
   940     MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
   941     sh4r.r[Rm] +=4;
   942 :}
   943 LDS Rm, MACL {:
   944     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   945                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   946 :}
   947 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   948 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   949 STS.L PR, @-Rn {:
   950     CHECKWALIGN32( sh4r.r[Rn] );
   951     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   952     sh4r.r[Rn] -= 4;
   953 :}
   954 STC.L VBR, @-Rn {:
   955     CHECKPRIV();
   956     CHECKWALIGN32( sh4r.r[Rn] );
   957     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   958     sh4r.r[Rn] -= 4;
   959 :}
   960 LDS.L @Rm+, PR {:
   961     CHECKRALIGN32( sh4r.r[Rm] );
   962     MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
   963     sh4r.r[Rm] += 4;
   964 :}
   965 LDC.L @Rm+, VBR {:
   966     CHECKPRIV();
   967     CHECKRALIGN32( sh4r.r[Rm] );
   968     MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
   969     sh4r.r[Rm] +=4;
   970 :}
   971 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   972 LDC Rm, VBR {:
   973     CHECKPRIV();
   974     sh4r.vbr = sh4r.r[Rm];
   975 :}
   976 STC SGR, Rn {:
   977     CHECKPRIV();
   978     sh4r.r[Rn] = sh4r.sgr;
   979 :}
   980 STC.L SGR, @-Rn {:
   981     CHECKPRIV();
   982     CHECKWALIGN32( sh4r.r[Rn] );
   983     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   984     sh4r.r[Rn] -= 4;
   985 :}
   986 STC.L SSR, @-Rn {:
   987     CHECKPRIV();
   988     CHECKWALIGN32( sh4r.r[Rn] );
   989     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   990     sh4r.r[Rn] -= 4;
   991 :}
   992 LDC.L @Rm+, SSR {:
   993     CHECKPRIV();
   994     CHECKRALIGN32( sh4r.r[Rm] );
   995     MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
   996     sh4r.r[Rm] +=4;
   997 :}
   998 LDC Rm, SSR {:
   999     CHECKPRIV();
  1000     sh4r.ssr = sh4r.r[Rm];
  1001 :}
  1002 STC.L SPC, @-Rn {:
  1003     CHECKPRIV();
  1004     CHECKWALIGN32( sh4r.r[Rn] );
  1005     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
  1006     sh4r.r[Rn] -= 4;
  1007 :}
  1008 LDC.L @Rm+, SPC {:
  1009     CHECKPRIV();
  1010     CHECKRALIGN32( sh4r.r[Rm] );
  1011     MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
  1012     sh4r.r[Rm] +=4;
  1013 :}
  1014 LDC Rm, SPC {:
  1015     CHECKPRIV();
  1016     sh4r.spc = sh4r.r[Rm];
  1017 :}
  1018 STS FPUL, Rn {: 
  1019     CHECKFPUEN();
  1020     sh4r.r[Rn] = FPULi; 
  1021 :}
  1022 STS.L FPUL, @-Rn {:
  1023     CHECKFPUEN();
  1024     CHECKWALIGN32( sh4r.r[Rn] );
  1025     MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
  1026     sh4r.r[Rn] -= 4;
  1027 :}
  1028 LDS.L @Rm+, FPUL {:
  1029     CHECKFPUEN();
  1030     CHECKRALIGN32( sh4r.r[Rm] );
  1031     MEM_READ_LONG(sh4r.r[Rm], FPULi);
  1032     sh4r.r[Rm] +=4;
  1033 :}
  1034 LDS Rm, FPUL {:
  1035     CHECKFPUEN();
  1036     FPULi = sh4r.r[Rm]; 
  1037 :}
  1038 STS FPSCR, Rn {: 
  1039     CHECKFPUEN();
  1040     sh4r.r[Rn] = sh4r.fpscr; 
  1041 :}
  1042 STS.L FPSCR, @-Rn {:
  1043     CHECKFPUEN();
  1044     CHECKWALIGN32( sh4r.r[Rn] );
  1045     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
  1046     sh4r.r[Rn] -= 4;
  1047 :}
  1048 LDS.L @Rm+, FPSCR {:
  1049     CHECKFPUEN();
  1050     CHECKRALIGN32( sh4r.r[Rm] );
  1051     MEM_READ_LONG(sh4r.r[Rm], tmp);
  1052     sh4r.r[Rm] +=4;
  1053     sh4_write_fpscr( tmp );
  1054 :}
  1055 LDS Rm, FPSCR {: 
  1056     CHECKFPUEN();
  1057     sh4_write_fpscr( sh4r.r[Rm] );
  1058 :}
  1059 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
  1060 STC.L DBR, @-Rn {:
  1061     CHECKPRIV();
  1062     CHECKWALIGN32( sh4r.r[Rn] );
  1063     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
  1064     sh4r.r[Rn] -= 4;
  1065 :}
  1066 LDC.L @Rm+, DBR {:
  1067     CHECKPRIV();
  1068     CHECKRALIGN32( sh4r.r[Rm] );
  1069     MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
  1070     sh4r.r[Rm] +=4;
  1071 :}
  1072 LDC Rm, DBR {:
  1073     CHECKPRIV();
  1074     sh4r.dbr = sh4r.r[Rm];
  1075 :}
  1076 STC.L Rm_BANK, @-Rn {:
  1077     CHECKPRIV();
  1078     CHECKWALIGN32( sh4r.r[Rn] );
  1079     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
  1080     sh4r.r[Rn] -= 4;
  1081 :}
  1082 LDC.L @Rm+, Rn_BANK {:
  1083     CHECKPRIV();
  1084     CHECKRALIGN32( sh4r.r[Rm] );
  1085     MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
  1086     sh4r.r[Rm] += 4;
  1087 :}
  1088 LDC Rm, Rn_BANK {:
  1089     CHECKPRIV();
  1090     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1091 :}
  1092 STC SR, Rn {: 
  1093     CHECKPRIV();
  1094     sh4r.r[Rn] = sh4_read_sr();
  1095 :}
  1096 STC GBR, Rn {:
  1097     sh4r.r[Rn] = sh4r.gbr;
  1098 :}
  1099 STC VBR, Rn {:
  1100     CHECKPRIV();
  1101     sh4r.r[Rn] = sh4r.vbr;
  1102 :}
  1103 STC SSR, Rn {:
  1104     CHECKPRIV();
  1105     sh4r.r[Rn] = sh4r.ssr;
  1106 :}
  1107 STC SPC, Rn {:
  1108     CHECKPRIV();
  1109     sh4r.r[Rn] = sh4r.spc;
  1110 :}
  1111 STC Rm_BANK, Rn {:
  1112     CHECKPRIV();
  1113     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
  1114 :}
  1116 FADD FRm, FRn {:
  1117     CHECKFPUEN();
  1118     if( IS_FPU_DOUBLEPREC() ) {
  1119 	DR(FRn) += DR(FRm);
  1120     } else {
  1121 	FR(FRn) += FR(FRm);
  1123 :}
  1124 FSUB FRm, FRn {:
  1125     CHECKFPUEN();
  1126     if( IS_FPU_DOUBLEPREC() ) {
  1127 	DR(FRn) -= DR(FRm);
  1128     } else {
  1129 	FR(FRn) -= FR(FRm);
  1131 :}
  1133 FMUL FRm, FRn {:
  1134     CHECKFPUEN();
  1135     if( IS_FPU_DOUBLEPREC() ) {
  1136 	DR(FRn) *= DR(FRm);
  1137     } else {
  1138 	FR(FRn) *= FR(FRm);
  1140 :}
  1142 FDIV FRm, FRn {:
  1143     CHECKFPUEN();
  1144     if( IS_FPU_DOUBLEPREC() ) {
  1145 	DR(FRn) /= DR(FRm);
  1146     } else {
  1147 	FR(FRn) /= FR(FRm);
  1149 :}
  1151 FCMP/EQ FRm, FRn {:
  1152     CHECKFPUEN();
  1153     if( IS_FPU_DOUBLEPREC() ) {
  1154 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1155     } else {
  1156 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1158 :}
  1160 FCMP/GT FRm, FRn {:
  1161     CHECKFPUEN();
  1162     if( IS_FPU_DOUBLEPREC() ) {
  1163 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1164     } else {
  1165 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1167 :}
  1169 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
  1170 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
  1171 FLOAT FPUL, FRn {: 
  1172     CHECKFPUEN();
  1173     if( IS_FPU_DOUBLEPREC() ) {
  1174 	if( FRn&1 ) { // No, really...
  1175 	    dtmp = (double)FPULi;
  1176 	    FR(FRn) = *(((float *)&dtmp)+1);
  1177 	} else {
  1178 	    DRF(FRn>>1) = (double)FPULi;
  1180     } else {
  1181 	FR(FRn) = (float)FPULi;
  1183 :}
  1184 FTRC FRm, FPUL {:
  1185     CHECKFPUEN();
  1186     if( IS_FPU_DOUBLEPREC() ) {
  1187 	if( FRm&1 ) {
  1188 	    dtmp = 0;
  1189 	    *(((float *)&dtmp)+1) = FR(FRm);
  1190 	} else {
  1191 	    dtmp = DRF(FRm>>1);
  1193         if( dtmp >= MAX_INTF )
  1194             FPULi = MAX_INT;
  1195         else if( dtmp <= MIN_INTF )
  1196             FPULi = MIN_INT;
  1197         else 
  1198             FPULi = (int32_t)dtmp;
  1199     } else {
  1200 	ftmp = FR(FRm);
  1201 	if( ftmp >= MAX_INTF )
  1202 	    FPULi = MAX_INT;
  1203 	else if( ftmp <= MIN_INTF )
  1204 	    FPULi = MIN_INT;
  1205 	else
  1206 	    FPULi = (int32_t)ftmp;
  1208 :}
  1209 FNEG FRn {:
  1210     CHECKFPUEN();
  1211     if( IS_FPU_DOUBLEPREC() ) {
  1212 	DR(FRn) = -DR(FRn);
  1213     } else {
  1214         FR(FRn) = -FR(FRn);
  1216 :}
  1217 FABS FRn {:
  1218     CHECKFPUEN();
  1219     if( IS_FPU_DOUBLEPREC() ) {
  1220 	DR(FRn) = fabs(DR(FRn));
  1221     } else {
  1222         FR(FRn) = fabsf(FR(FRn));
  1224 :}
  1225 FSQRT FRn {:
  1226     CHECKFPUEN();
  1227     if( IS_FPU_DOUBLEPREC() ) {
  1228 	DR(FRn) = sqrt(DR(FRn));
  1229     } else {
  1230         FR(FRn) = sqrtf(FR(FRn));
  1232 :}
  1233 FLDI0 FRn {:
  1234     CHECKFPUEN();
  1235     if( IS_FPU_DOUBLEPREC() ) {
  1236 	DR(FRn) = 0.0;
  1237     } else {
  1238         FR(FRn) = 0.0;
  1240 :}
  1241 FLDI1 FRn {:
  1242     CHECKFPUEN();
  1243     if( IS_FPU_DOUBLEPREC() ) {
  1244 	DR(FRn) = 1.0;
  1245     } else {
  1246         FR(FRn) = 1.0;
  1248 :}
  1249 FMAC FR0, FRm, FRn {:
  1250     CHECKFPUEN();
  1251     if( IS_FPU_DOUBLEPREC() ) {
  1252         DR(FRn) += DR(FRm)*DR(0);
  1253     } else {
  1254 	FR(FRn) += FR(FRm)*FR(0);
  1256 :}
  1257 FRCHG {: 
  1258     CHECKFPUEN(); 
  1259     sh4r.fpscr ^= FPSCR_FR; 
  1260     sh4_switch_fr_banks();
  1261 :}
  1262 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1263 FCNVSD FPUL, FRn {:
  1264     CHECKFPUEN();
  1265     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1266 	DR(FRn) = (double)FPULf;
  1268 :}
  1269 FCNVDS FRm, FPUL {:
  1270     CHECKFPUEN();
  1271     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1272 	FPULf = (float)DR(FRm);
  1274 :}
  1276 FSRRA FRn {:
  1277     CHECKFPUEN();
  1278     if( !IS_FPU_DOUBLEPREC() ) {
  1279 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1281 :}
  1282 FIPR FVm, FVn {:
  1283     CHECKFPUEN();
  1284     if( !IS_FPU_DOUBLEPREC() ) {
  1285         int tmp2 = FVn<<2;
  1286         tmp = FVm<<2;
  1287         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1288             FR(tmp+1)*FR(tmp2+1) +
  1289             FR(tmp+2)*FR(tmp2+2) +
  1290             FR(tmp+3)*FR(tmp2+3);
  1292 :}
  1293 FSCA FPUL, FRn {:
  1294     CHECKFPUEN();
  1295     if( !IS_FPU_DOUBLEPREC() ) {
  1296 	sh4_fsca( FPULi, (float *)&(DRF(FRn>>1)) );
  1298 :}
  1299 FTRV XMTRX, FVn {:
  1300     CHECKFPUEN();
  1301     if( !IS_FPU_DOUBLEPREC() ) {
  1302 	sh4_ftrv((float *)&(DRF(FVn<<1)) );
  1304 :}
  1305 UNDEF {:
  1306     UNDEF(ir);
  1307 :}
  1308 %%
  1309     sh4r.pc = sh4r.new_pc;
  1310     sh4r.new_pc += 2;
  1312 except:
  1313     sh4r.in_delay_slot = 0;
  1314     return TRUE;
.