filename | src/pvr2/pvr2.c |
changeset | 586:2a3ba82cf243 |
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author | nkeynes |
date | Tue Feb 12 08:36:29 2008 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Bug #55: Fix relative path handling Canonicalize paths before passing to the file dialog |
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1 /**
2 * $Id$
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include <assert.h>
21 #include "dream.h"
22 #include "eventq.h"
23 #include "display.h"
24 #include "mem.h"
25 #include "asic.h"
26 #include "clock.h"
27 #include "pvr2/pvr2.h"
28 #include "sh4/sh4.h"
29 #define MMIO_IMPL
30 #include "pvr2/pvr2mmio.h"
32 unsigned char *video_base;
34 #define MAX_RENDER_BUFFERS 4
36 #define HPOS_PER_FRAME 0
37 #define HPOS_PER_LINECOUNT 1
39 static void pvr2_init( void );
40 static void pvr2_reset( void );
41 static uint32_t pvr2_run_slice( uint32_t );
42 static void pvr2_save_state( FILE *f );
43 static int pvr2_load_state( FILE *f );
44 static void pvr2_update_raster_posn( uint32_t nanosecs );
45 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
46 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
47 static render_buffer_t pvr2_next_render_buffer( );
48 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
49 uint32_t pvr2_get_sync_status();
51 void pvr2_display_frame( void );
53 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
55 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
56 pvr2_run_slice, NULL,
57 pvr2_save_state, pvr2_load_state };
60 display_driver_t display_driver = NULL;
62 struct pvr2_state {
63 uint32_t frame_count;
64 uint32_t line_count;
65 uint32_t line_remainder;
66 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
67 uint32_t irq_hpos_line;
68 uint32_t irq_hpos_line_count;
69 uint32_t irq_hpos_mode;
70 uint32_t irq_hpos_time_ns; /* Time within the line */
71 uint32_t irq_vpos1;
72 uint32_t irq_vpos2;
73 uint32_t odd_even_field; /* 1 = odd, 0 = even */
74 gboolean palette_changed; /* TRUE if palette has changed since last render */
75 gchar *save_next_render_filename;
76 /* timing */
77 uint32_t dot_clock;
78 uint32_t total_lines;
79 uint32_t line_size;
80 uint32_t line_time_ns;
81 uint32_t vsync_lines;
82 uint32_t hsync_width_ns;
83 uint32_t front_porch_ns;
84 uint32_t back_porch_ns;
85 uint32_t retrace_start_line;
86 uint32_t retrace_end_line;
87 gboolean interlaced;
88 } pvr2_state;
90 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
91 static int render_buffer_count = 0;
92 static render_buffer_t displayed_render_buffer = NULL;
93 static uint32_t displayed_border_colour = 0;
95 /**
96 * Event handler for the hpos callback
97 */
98 static void pvr2_hpos_callback( int eventid ) {
99 asic_event( eventid );
100 pvr2_update_raster_posn(sh4r.slice_cycle);
101 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
102 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
103 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
104 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
105 }
106 }
107 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
108 pvr2_state.irq_hpos_time_ns );
109 }
111 /**
112 * Event handler for the scanline callbacks. Fires the corresponding
113 * ASIC event, and resets the timer for the next field.
114 */
115 static void pvr2_scanline_callback( int eventid ) {
116 asic_event( eventid );
117 pvr2_update_raster_posn(sh4r.slice_cycle);
118 if( eventid == EVENT_SCANLINE1 ) {
119 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
120 } else {
121 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
122 }
123 }
125 static void pvr2_init( void )
126 {
127 int i;
128 register_io_region( &mmio_region_PVR2 );
129 register_io_region( &mmio_region_PVR2PAL );
130 register_io_region( &mmio_region_PVR2TA );
131 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
132 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
133 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
134 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
135 texcache_init();
136 pvr2_reset();
137 pvr2_ta_reset();
138 pvr2_state.save_next_render_filename = NULL;
139 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
140 render_buffers[i] = NULL;
141 }
142 render_buffer_count = 0;
143 displayed_render_buffer = NULL;
144 displayed_border_colour = 0;
145 }
147 static void pvr2_reset( void )
148 {
149 int i;
150 pvr2_state.line_count = 0;
151 pvr2_state.line_remainder = 0;
152 pvr2_state.cycles_run = 0;
153 pvr2_state.irq_vpos1 = 0;
154 pvr2_state.irq_vpos2 = 0;
155 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
156 pvr2_state.back_porch_ns = 4000;
157 pvr2_state.palette_changed = FALSE;
158 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
159 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
160 mmio_region_PVR2_write( YUV_ADDR, 0 );
161 mmio_region_PVR2_write( YUV_CFG, 0 );
163 pvr2_ta_init();
164 texcache_flush();
165 if( display_driver ) {
166 display_driver->display_blank(0);
167 for( i=0; i<render_buffer_count; i++ ) {
168 display_driver->destroy_render_buffer(render_buffers[i]);
169 render_buffers[i] = NULL;
170 }
171 render_buffer_count = 0;
172 }
173 }
175 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
176 {
177 struct frame_buffer fbuf;
179 fbuf.width = buffer->width;
180 fbuf.height = buffer->height;
181 fbuf.rowstride = fbuf.width*3;
182 fbuf.colour_format = COLFMT_BGR888;
183 fbuf.inverted = buffer->inverted;
184 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
186 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
187 write_png_to_stream( f, &fbuf );
188 g_free( fbuf.data );
190 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
191 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
192 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
193 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
194 fwrite( &buffer->flushed, sizeof(buffer->flushed), 1, f );
196 }
198 render_buffer_t pvr2_load_render_buffer( FILE *f )
199 {
200 frame_buffer_t frame = read_png_from_stream( f );
201 if( frame == NULL ) {
202 return NULL;
203 }
205 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
206 assert( buffer != NULL );
207 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
208 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
209 fread( &buffer->address, sizeof(buffer->address), 1, f );
210 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
211 fread( &buffer->flushed, sizeof(buffer->flushed), 1, f );
212 return buffer;
213 }
218 void pvr2_save_render_buffers( FILE *f )
219 {
220 int i;
221 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
222 if( displayed_render_buffer != NULL ) {
223 i = 1;
224 fwrite( &i, sizeof(i), 1, f );
225 pvr2_save_render_buffer( f, displayed_render_buffer );
226 } else {
227 i = 0;
228 fwrite( &i, sizeof(i), 1, f );
229 }
231 for( i=0; i<render_buffer_count; i++ ) {
232 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
233 pvr2_save_render_buffer( f, render_buffers[i] );
234 }
235 }
236 }
238 gboolean pvr2_load_render_buffers( FILE *f )
239 {
240 uint32_t count;
241 int i, has_frontbuffer;
243 fread( &count, sizeof(count), 1, f );
244 if( count > MAX_RENDER_BUFFERS ) {
245 return FALSE;
246 }
247 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
248 for( i=0; i<render_buffer_count; i++ ) {
249 display_driver->destroy_render_buffer(render_buffers[i]);
250 render_buffers[i] = NULL;
251 }
252 render_buffer_count = 0;
254 if( has_frontbuffer ) {
255 displayed_render_buffer = pvr2_load_render_buffer(f);
256 display_driver->display_render_buffer( displayed_render_buffer );
257 count--;
258 }
260 for( i=0; i<count; i++ ) {
261 if( pvr2_load_render_buffer( f ) == NULL ) {
262 return FALSE;
263 }
264 }
265 return TRUE;
266 }
269 static void pvr2_save_state( FILE *f )
270 {
271 pvr2_save_render_buffers( f );
272 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
273 pvr2_ta_save_state( f );
274 pvr2_yuv_save_state( f );
275 }
277 static int pvr2_load_state( FILE *f )
278 {
279 if( !pvr2_load_render_buffers(f) )
280 return 1;
281 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
282 return 1;
283 if( pvr2_ta_load_state(f) ) {
284 return 1;
285 }
286 return pvr2_yuv_load_state(f);
287 }
289 /**
290 * Update the current raster position to the given number of nanoseconds,
291 * relative to the last time slice. (ie the raster will be adjusted forward
292 * by nanosecs - nanosecs_already_run_this_timeslice)
293 */
294 static void pvr2_update_raster_posn( uint32_t nanosecs )
295 {
296 uint32_t old_line_count = pvr2_state.line_count;
297 if( pvr2_state.line_time_ns == 0 ) {
298 return; /* do nothing */
299 }
300 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
301 pvr2_state.cycles_run = nanosecs;
302 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
303 pvr2_state.line_count ++;
304 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
305 }
307 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
308 pvr2_state.line_count -= pvr2_state.total_lines;
309 if( pvr2_state.interlaced ) {
310 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
311 }
312 }
313 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
314 (old_line_count < pvr2_state.retrace_end_line ||
315 old_line_count > pvr2_state.line_count) ) {
316 pvr2_state.frame_count++;
317 pvr2_display_frame();
318 }
319 }
321 static uint32_t pvr2_run_slice( uint32_t nanosecs )
322 {
323 pvr2_update_raster_posn( nanosecs );
324 pvr2_state.cycles_run = 0;
325 return nanosecs;
326 }
328 int pvr2_get_frame_count()
329 {
330 return pvr2_state.frame_count;
331 }
333 render_buffer_t pvr2_get_front_buffer()
334 {
335 return displayed_render_buffer;
336 }
338 uint32_t pvr2_get_border_colour()
339 {
340 return displayed_border_colour;
341 }
343 gboolean pvr2_save_next_scene( const gchar *filename )
344 {
345 if( pvr2_state.save_next_render_filename != NULL ) {
346 g_free( pvr2_state.save_next_render_filename );
347 }
348 pvr2_state.save_next_render_filename = g_strdup(filename);
349 return TRUE;
350 }
354 /**
355 * Display the next frame, copying the current contents of video ram to
356 * the window. If the video configuration has changed, first recompute the
357 * new frame size/depth.
358 */
359 void pvr2_display_frame( void )
360 {
361 int dispmode = MMIO_READ( PVR2, DISP_MODE );
362 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
363 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
365 if( display_driver == NULL ) {
366 return; /* can't really do anything much */
367 } else if( !bEnabled ) {
368 /* Output disabled == black */
369 displayed_render_buffer = NULL;
370 displayed_border_colour = 0;
371 display_driver->display_blank( 0 );
372 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
373 /* Enabled but blanked - border colour */
374 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
375 displayed_render_buffer = NULL;
376 display_driver->display_blank( displayed_border_colour );
377 } else {
378 /* Real output - determine dimensions etc */
379 struct frame_buffer fbuf;
380 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
381 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
382 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
384 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
385 fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
386 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
387 fbuf.size = vid_ppl << 2 * fbuf.height;
388 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
390 /* Determine the field to display, and deinterlace if possible */
391 if( pvr2_state.interlaced ) {
392 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
393 fbuf.height = fbuf.height << 1;
394 fbuf.rowstride = vid_ppl << 2;
395 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
396 } else {
397 /* Just display the field as is, folks. This is slightly tricky -
398 * we pick the field based on which frame is about to come through,
399 * which may not be the same as the odd_even_field.
400 */
401 gboolean oddfield = pvr2_state.odd_even_field;
402 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
403 oddfield = !oddfield;
404 }
405 if( oddfield ) {
406 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
407 } else {
408 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
409 }
410 }
411 } else {
412 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
413 }
414 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
415 fbuf.inverted = FALSE;
416 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
418 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
419 if( rbuf == NULL ) {
420 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
421 }
422 displayed_render_buffer = rbuf;
423 if( rbuf != NULL ) {
424 display_driver->display_render_buffer( rbuf );
425 }
426 }
427 }
429 /**
430 * This has to handle every single register individually as they all get masked
431 * off differently (and its easier to do it at write time)
432 */
433 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
434 {
435 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
436 MMIO_WRITE( PVR2, reg, val );
437 return;
438 }
440 switch(reg) {
441 case PVRID:
442 case PVRVER:
443 case GUNPOS: /* Read only registers */
444 break;
445 case PVRRESET:
446 val &= 0x00000007; /* Do stuff? */
447 MMIO_WRITE( PVR2, reg, val );
448 break;
449 case RENDER_START: /* Don't really care what value */
450 if( pvr2_state.save_next_render_filename != NULL ) {
451 if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
452 INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
453 }
454 g_free( pvr2_state.save_next_render_filename );
455 pvr2_state.save_next_render_filename = NULL;
456 }
457 render_buffer_t buffer = pvr2_next_render_buffer();
458 if( buffer != NULL ) {
459 pvr2_render_scene( buffer );
460 }
461 asic_event( EVENT_PVR_RENDER_DONE );
462 break;
463 case RENDER_POLYBASE:
464 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
465 break;
466 case RENDER_TSPCFG:
467 MMIO_WRITE( PVR2, reg, val&0x00010101 );
468 break;
469 case DISP_BORDER:
470 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
471 break;
472 case DISP_MODE:
473 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
474 break;
475 case RENDER_MODE:
476 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
477 break;
478 case RENDER_SIZE:
479 MMIO_WRITE( PVR2, reg, val&0x000001FF );
480 break;
481 case DISP_ADDR1:
482 val &= 0x00FFFFFC;
483 MMIO_WRITE( PVR2, reg, val );
484 pvr2_update_raster_posn(sh4r.slice_cycle);
485 break;
486 case DISP_ADDR2:
487 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
488 pvr2_update_raster_posn(sh4r.slice_cycle);
489 break;
490 case DISP_SIZE:
491 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
492 break;
493 case RENDER_ADDR1:
494 case RENDER_ADDR2:
495 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
496 break;
497 case RENDER_HCLIP:
498 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
499 break;
500 case RENDER_VCLIP:
501 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
502 break;
503 case DISP_HPOSIRQ:
504 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
505 pvr2_state.irq_hpos_line = val & 0x03FF;
506 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
507 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
508 switch( pvr2_state.irq_hpos_mode ) {
509 case 3: /* Reserved - treat as 0 */
510 case 0: /* Once per frame at specified line */
511 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
512 break;
513 case 2: /* Once per line - as per-line-count */
514 pvr2_state.irq_hpos_line = 1;
515 pvr2_state.irq_hpos_mode = 1;
516 case 1: /* Once per N lines */
517 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
518 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
519 pvr2_state.irq_hpos_line_count;
520 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
521 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
522 }
523 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
524 }
525 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
526 pvr2_state.irq_hpos_time_ns );
527 break;
528 case DISP_VPOSIRQ:
529 val = val & 0x03FF03FF;
530 pvr2_state.irq_vpos1 = (val >> 16);
531 pvr2_state.irq_vpos2 = val & 0x03FF;
532 pvr2_update_raster_posn(sh4r.slice_cycle);
533 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
534 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
535 MMIO_WRITE( PVR2, reg, val );
536 break;
537 case RENDER_NEARCLIP:
538 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
539 break;
540 case RENDER_SHADOW:
541 MMIO_WRITE( PVR2, reg, val&0x000001FF );
542 break;
543 case RENDER_OBJCFG:
544 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
545 break;
546 case RENDER_TSPCLIP:
547 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
548 break;
549 case RENDER_FARCLIP:
550 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
551 break;
552 case RENDER_BGPLANE:
553 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
554 break;
555 case RENDER_ISPCFG:
556 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
557 break;
558 case VRAM_CFG1:
559 MMIO_WRITE( PVR2, reg, val&0x000000FF );
560 break;
561 case VRAM_CFG2:
562 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
563 break;
564 case VRAM_CFG3:
565 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
566 break;
567 case RENDER_FOGTBLCOL:
568 case RENDER_FOGVRTCOL:
569 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
570 break;
571 case RENDER_FOGCOEFF:
572 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
573 break;
574 case RENDER_CLAMPHI:
575 case RENDER_CLAMPLO:
576 MMIO_WRITE( PVR2, reg, val );
577 break;
578 case RENDER_TEXSIZE:
579 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
580 break;
581 case RENDER_PALETTE:
582 MMIO_WRITE( PVR2, reg, val&0x00000003 );
583 break;
585 /********** CRTC registers *************/
586 case DISP_HBORDER:
587 case DISP_VBORDER:
588 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
589 break;
590 case DISP_TOTAL:
591 val = val & 0x03FF03FF;
592 MMIO_WRITE( PVR2, reg, val );
593 pvr2_update_raster_posn(sh4r.slice_cycle);
594 pvr2_state.total_lines = (val >> 16) + 1;
595 pvr2_state.line_size = (val & 0x03FF) + 1;
596 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
597 pvr2_state.retrace_end_line = 0x2A;
598 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
599 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
600 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
601 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
602 pvr2_state.irq_hpos_time_ns );
603 break;
604 case DISP_SYNCCFG:
605 MMIO_WRITE( PVR2, reg, val&0x000003FF );
606 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
607 break;
608 case DISP_SYNCTIME:
609 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
610 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
611 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
612 break;
613 case DISP_CFG2:
614 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
615 break;
616 case DISP_HPOS:
617 val = val & 0x03FF;
618 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
619 MMIO_WRITE( PVR2, reg, val );
620 break;
621 case DISP_VPOS:
622 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
623 break;
625 /*********** Tile accelerator registers ***********/
626 case TA_POLYPOS:
627 case TA_LISTPOS:
628 /* Readonly registers */
629 break;
630 case TA_TILEBASE:
631 case TA_LISTEND:
632 case TA_LISTBASE:
633 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
634 break;
635 case RENDER_TILEBASE:
636 case TA_POLYBASE:
637 case TA_POLYEND:
638 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
639 break;
640 case TA_TILESIZE:
641 MMIO_WRITE( PVR2, reg, val&0x000F003F );
642 break;
643 case TA_TILECFG:
644 MMIO_WRITE( PVR2, reg, val&0x00133333 );
645 break;
646 case TA_INIT:
647 if( val & 0x80000000 )
648 pvr2_ta_init();
649 break;
650 case TA_REINIT:
651 break;
652 /**************** Scaler registers? ****************/
653 case RENDER_SCALER:
654 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
655 break;
657 case YUV_ADDR:
658 val = val & 0x00FFFFF8;
659 MMIO_WRITE( PVR2, reg, val );
660 pvr2_yuv_init( val );
661 break;
662 case YUV_CFG:
663 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
664 pvr2_yuv_set_config(val);
665 break;
667 /**************** Unknowns ***************/
668 case PVRUNK1:
669 MMIO_WRITE( PVR2, reg, val&0x000007FF );
670 break;
671 case PVRUNK2:
672 MMIO_WRITE( PVR2, reg, val&0x00000007 );
673 break;
674 case PVRUNK3:
675 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
676 break;
677 case PVRUNK5:
678 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
679 break;
680 case PVRUNK6:
681 MMIO_WRITE( PVR2, reg, val&0x000000FF );
682 break;
683 case PVRUNK7:
684 MMIO_WRITE( PVR2, reg, val&0x00000001 );
685 break;
686 }
687 }
689 /**
690 * Calculate the current read value of the syncstat register, using
691 * the current SH4 clock time as an offset from the last timeslice.
692 * The register reads (LSB to MSB) as:
693 * 0..9 Current scan line
694 * 10 Odd/even field (1 = odd, 0 = even)
695 * 11 Display active (including border and overscan)
696 * 12 Horizontal sync off
697 * 13 Vertical sync off
698 * Note this method is probably incorrect for anything other than straight
699 * interlaced PAL/NTSC, and needs further testing.
700 */
701 uint32_t pvr2_get_sync_status()
702 {
703 pvr2_update_raster_posn(sh4r.slice_cycle);
704 uint32_t result = pvr2_state.line_count;
706 if( pvr2_state.odd_even_field ) {
707 result |= 0x0400;
708 }
709 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
710 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
711 result |= 0x1000; /* !HSYNC */
712 }
713 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
714 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
715 result |= 0x2800; /* Display active */
716 } else {
717 result |= 0x2000; /* Front porch */
718 }
719 }
720 } else {
721 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
722 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
723 result |= 0x3800; /* Display active */
724 } else {
725 result |= 0x3000;
726 }
727 } else {
728 result |= 0x1000; /* Back porch */
729 }
730 }
731 return result;
732 }
734 /**
735 * Schedule a "scanline" event. This actually goes off at
736 * 2 * line in even fields and 2 * line + 1 in odd fields.
737 * Otherwise this behaves as per pvr2_schedule_line_event().
738 * The raster position should be updated before calling this
739 * method.
740 * @param eventid Event to fire at the specified time
741 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
742 * displays).
743 * @param hpos_ns Nanoseconds into the line at which to fire.
744 */
745 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
746 {
747 uint32_t field = pvr2_state.odd_even_field;
748 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
749 field = !field;
750 }
751 if( hpos_ns > pvr2_state.line_time_ns ) {
752 hpos_ns = pvr2_state.line_time_ns;
753 }
755 line <<= 1;
756 if( field ) {
757 line += 1;
758 }
760 if( line < pvr2_state.total_lines ) {
761 uint32_t lines;
762 uint32_t time;
763 if( line <= pvr2_state.line_count ) {
764 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
765 } else {
766 lines = (line - pvr2_state.line_count);
767 }
768 if( lines <= minimum_lines ) {
769 lines += pvr2_state.total_lines;
770 }
771 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
772 event_schedule( eventid, time );
773 } else {
774 event_cancel( eventid );
775 }
776 }
778 MMIO_REGION_READ_FN( PVR2, reg )
779 {
780 switch( reg ) {
781 case DISP_SYNCSTAT:
782 return pvr2_get_sync_status();
783 default:
784 return MMIO_READ( PVR2, reg );
785 }
786 }
788 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
789 {
790 MMIO_WRITE( PVR2PAL, reg, val );
791 pvr2_state.palette_changed = TRUE;
792 }
794 void pvr2_check_palette_changed()
795 {
796 if( pvr2_state.palette_changed ) {
797 texcache_invalidate_palette();
798 pvr2_state.palette_changed = FALSE;
799 }
800 }
802 MMIO_REGION_READ_DEFFN( PVR2PAL );
804 void pvr2_set_base_address( uint32_t base )
805 {
806 mmio_region_PVR2_write( DISP_ADDR1, base );
807 }
812 int32_t mmio_region_PVR2TA_read( uint32_t reg )
813 {
814 return 0xFFFFFFFF;
815 }
817 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
818 {
819 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
820 }
822 /**
823 * Find the render buffer corresponding to the requested output frame
824 * (does not consider texture renders).
825 * @return the render_buffer if found, or null if no such buffer.
826 *
827 * Note: Currently does not consider "partial matches", ie partial
828 * frame overlap - it probably needs to do this.
829 */
830 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
831 {
832 int i;
833 for( i=0; i<render_buffer_count; i++ ) {
834 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
835 return render_buffers[i];
836 }
837 }
838 return NULL;
839 }
841 /**
842 * Allocate a render buffer with the requested parameters.
843 * The order of preference is:
844 * 1. An existing buffer with the same address. (not flushed unless the new
845 * size is smaller than the old one).
846 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
847 * is flushed to vram.
848 * 3. A new buffer if one can be created.
849 * 4. The current display buff
850 * Note: The current display field(s) will never be overwritten except as a last
851 * resort.
852 */
853 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
854 {
855 int i;
856 render_buffer_t result = NULL;
858 /* Check existing buffers for an available buffer */
859 for( i=0; i<render_buffer_count; i++ ) {
860 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
861 /* needs to be the right dimensions */
862 if( render_buffers[i]->address == render_addr ) {
863 if( displayed_render_buffer == render_buffers[i] ) {
864 /* Same address, but we can't use it because the
865 * display has it. Mark it as unaddressed for later.
866 */
867 render_buffers[i]->address = -1;
868 } else {
869 /* perfect */
870 result = render_buffers[i];
871 break;
872 }
873 } else if( render_buffers[i]->address == -1 && result == NULL &&
874 displayed_render_buffer != render_buffers[i] ) {
875 result = render_buffers[i];
876 }
878 } else if( render_buffers[i]->address == render_addr ) {
879 /* right address, wrong size - if it's larger, flush it, otherwise
880 * nuke it quietly */
881 if( render_buffers[i]->width * render_buffers[i]->height >
882 width*height ) {
883 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
884 }
885 render_buffers[i]->address = -1;
886 }
887 }
889 /* Nothing available - make one */
890 if( result == NULL ) {
891 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
892 /* maximum buffers reached - need to throw one away */
893 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
894 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
895 for( i=0; i<render_buffer_count; i++ ) {
896 if( render_buffers[i]->address != field1_addr &&
897 render_buffers[i]->address != field2_addr &&
898 render_buffers[i] != displayed_render_buffer ) {
899 /* Never throw away the current "front buffer(s)" */
900 result = render_buffers[i];
901 if( !result->flushed ) {
902 pvr2_render_buffer_copy_to_sh4( result );
903 }
904 if( result->width != width || result->height != height ) {
905 display_driver->destroy_render_buffer(render_buffers[i]);
906 result = display_driver->create_render_buffer(width,height);
907 render_buffers[i] = result;
908 }
909 break;
910 }
911 }
912 } else {
913 result = display_driver->create_render_buffer(width,height);
914 if( result != NULL ) {
915 render_buffers[render_buffer_count++] = result;
916 }
917 }
918 }
920 if( result != NULL ) {
921 result->address = render_addr;
922 }
923 return result;
924 }
926 /**
927 * Allocate a render buffer based on the current rendering settings
928 */
929 render_buffer_t pvr2_next_render_buffer()
930 {
931 render_buffer_t result = NULL;
932 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
933 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
934 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
935 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
937 if( render_addr & 0x01000000 ) { /* vram64 */
938 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
939 } else { /* vram32 */
940 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
941 }
943 int width, height;
944 int colour_format = pvr2_render_colour_format[render_mode&0x07];
945 pvr2_render_getsize( &width, &height );
947 result = pvr2_alloc_render_buffer( render_addr, width, height );
948 /* Setup the buffer */
949 if( result != NULL ) {
950 result->rowstride = render_stride;
951 result->colour_format = colour_format;
952 result->scale = render_scale;
953 result->size = width * height * colour_formats[colour_format].bpp;
954 result->flushed = FALSE;
955 result->inverted = TRUE; // render buffers are inverted normally
956 }
957 return result;
958 }
960 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
961 {
962 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
963 if( result != NULL ) {
964 int bpp = colour_formats[frame->colour_format].bpp;
965 result->rowstride = frame->rowstride;
966 result->colour_format = frame->colour_format;
967 result->scale = 0x400;
968 result->size = frame->width * frame->height * bpp;
969 result->flushed = TRUE;
970 result->inverted = frame->inverted;
971 display_driver->load_frame_buffer( frame, result );
972 }
973 return result;
974 }
977 /**
978 * Invalidate any caching on the supplied address. Specifically, if it falls
979 * within any of the render buffers, flush the buffer back to PVR2 ram.
980 */
981 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
982 {
983 int i;
984 address = address & 0x1FFFFFFF;
985 for( i=0; i<render_buffer_count; i++ ) {
986 uint32_t bufaddr = render_buffers[i]->address;
987 if( bufaddr != -1 && bufaddr <= address &&
988 (bufaddr + render_buffers[i]->size) > address ) {
989 if( !render_buffers[i]->flushed ) {
990 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
991 render_buffers[i]->flushed = TRUE;
992 }
993 if( isWrite ) {
994 render_buffers[i]->address = -1; /* Invalid */
995 }
996 return TRUE; /* should never have overlapping buffers */
997 }
998 }
999 return FALSE;
1000 }
.