14 * 1) Does changing the mask after event occurance result in the
15 * interrupt being delivered immediately?
16 * 2) If the pending register is not cleared after an interrupt, does
17 * the interrupt line remain high? (ie does the IRQ reoccur?)
18 * TODO: Logic diagram of ASIC event/interrupt logic.
20 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
21 * practically nothing is publicly known...
24 struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
27 void asic_init( void )
29 register_io_region( &mmio_region_ASIC );
30 register_io_region( &mmio_region_EXTDMA );
31 mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
32 asic_event( EVENT_GDROM_CMD );
35 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
41 /* Clear any interrupts */
42 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
45 MMIO_WRITE( ASIC, reg, val );
47 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
48 WARN( "Maple request initiated at %08X, halting", maple_addr );
49 maple_handle_buffer( maple_addr );
50 MMIO_WRITE( ASIC, reg, 0 );
55 MMIO_WRITE( ASIC, reg, val );
56 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
57 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
61 int32_t mmio_region_ASIC_read( uint32_t reg )
73 val = MMIO_READ(ASIC, reg);
74 // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
75 // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
78 return 0; /* find out later if there's any cases we actually need to care about */
80 val = MMIO_READ(ASIC, reg);
81 WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
82 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
88 void asic_event( int event )
90 int offset = ((event&0x60)>>3);
91 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
93 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
94 intc_raise_interrupt( INT_IRQ13 );
95 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
96 intc_raise_interrupt( INT_IRQ11 );
97 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
98 intc_raise_interrupt( INT_IRQ9 );
103 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
106 case IDEALTSTATUS: /* Device control */
107 ide_write_control( val );
110 ide_write_data_pio( val );
113 if( ide_can_write_regs() )
114 idereg.feature = (uint8_t)val;
117 if( ide_can_write_regs() )
118 idereg.count = (uint8_t)val;
121 if( ide_can_write_regs() )
122 idereg.lba0 = (uint8_t)val;
125 if( ide_can_write_regs() )
126 idereg.lba1 = (uint8_t)val;
129 if( ide_can_write_regs() )
130 idereg.lba2 = (uint8_t)val;
133 if( ide_can_write_regs() )
134 idereg.device = (uint8_t)val;
137 if( ide_can_write_regs() ) {
138 ide_clear_interrupt();
139 ide_write_command( (uint8_t)val );
144 MMIO_WRITE( EXTDMA, reg, val );
148 MMIO_REGION_READ_FN( EXTDMA, reg )
151 case IDEALTSTATUS: return idereg.status;
152 case IDEDATA: return ide_read_data_pio( );
153 case IDEFEAT: return idereg.error;
154 case IDECOUNT:return idereg.count;
155 case IDELBA0: return idereg.disc;
156 case IDELBA1: return idereg.lba1;
157 case IDELBA2: return idereg.lba2;
158 case IDEDEV: return idereg.device;
160 ide_clear_interrupt();
161 return idereg.status;
163 return MMIO_READ( EXTDMA, reg );
.