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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 15:5194dd0fdb60
prev10:c898b37506e0
next16:f383e7640da4
author nkeynes
date Mon Dec 12 13:11:11 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Add dreamcast_module module structure
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     1 #include <math.h>
     2 #include "dream.h"
     3 #include "modules.h"
     4 #include "sh4core.h"
     5 #include "sh4mmio.h"
     6 #include "mem.h"
     7 #include "intc.h"
     9 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    10 				       NULL, sh4_stop,
    11 				       NULL, NULL };
    13 struct sh4_registers sh4r;
    14 static int running = 0;
    16 void sh4_init(void)
    17 {
    18     mem_create_ram_region( 0x0C000000, 16 MB, MEM_REGION_MAIN );
    19     register_io_regions( mmio_list_sh4mmio );
    20     mmu_init();
    21 }
    23 void sh4_reset(void)
    24 {
    25     sh4r.pc    = 0xA0000000;
    26     sh4r.new_pc= 0xA0000002;
    27     sh4r.vbr   = 0x00000000;
    28     sh4r.fpscr = 0x00040001;
    29     sh4r.sr    = 0x700000F0;
    30     sh4r.icount= 0;
    31     /* Everything else is undefined anyway, so don't bother setting it */
    32     intc_reset();
    33 }
    35 void sh4_set_pc( int pc )
    36 {
    37     sh4r.pc = pc;
    38     sh4r.new_pc = pc+2;
    39 }
    41 void sh4_stop(void)
    42 {
    43     running = 0;
    44 }
    46 void sh4_run(void)
    47 {
    48     running = 1;
    49     while( running ) {
    50         sh4_execute_instruction();
    51     }
    52 }
    54 void sh4_runfor(uint32_t count)
    55 {
    56     running = 1;
    57     while( running && count--) {
    58         int pc = sh4r.pc;
    59         sh4_execute_instruction();
    60         /*
    61         if( sh4r.pc == 0x8C0C1636 ||
    62             sh4r.pc == 0x8C0C1634 ) {
    63             WARN( "Branching to %08X from %08X", sh4r.pc, pc );
    64             sh4_stop();
    65             }*/
    66     }
    67 }
    69 int sh4_isrunning(void)
    70 {
    71     return running;
    72 }
    74 void sh4_runto( uint32_t target_pc, uint32_t count )
    75 {
    76     running = 1;
    77     while( running && count--) {
    78         sh4_execute_instruction();
    79         if( sh4r.pc == target_pc ) {
    80             running = 0;
    81             break;
    82         }
    83     }
    84 }
    86 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
    87 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); return; }while(0)
    89 #define RAISE( x, v ) do{ \
    90     if( sh4r.vbr == 0 ) { \
    91         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
    92         sh4_stop(); \
    93     } else { \
    94         sh4r.spc = sh4r.pc + 2; \
    95         sh4r.ssr = sh4_read_sr(); \
    96         sh4r.sgr = sh4r.r[15]; \
    97         MMIO_WRITE(MMU,EXPEVT,x); \
    98         sh4r.pc = sh4r.vbr + v; \
    99         sh4r.new_pc = sh4r.pc + 2; \
   100         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   101     } \
   102     return; } while(0)
   104 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   105 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   106 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   107 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   108 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   109 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   111 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   112     ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
   113     ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
   114 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
   116 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   117     sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
   118     sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
   119 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
   121 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   123 #define EXC_POWER_RESET  0x000 /* vector special */
   124 #define EXC_MANUAL_RESET 0x020
   125 #define EXC_SLOT_ILLEGAL 0x1A0
   126 #define EXC_ILLEGAL      0x180
   127 #define EXV_ILLEGAL      0x100
   128 #define EXC_TRAP         0x160
   129 #define EXV_TRAP         0x100
   130 #define EXC_FPDISABLE    0x800
   131 #define EXV_FPDISABLE    0x100
   133 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
   134 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
   135 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
   136 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
   137 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
   139 static void sh4_switch_banks( )
   140 {
   141     uint32_t tmp[8];
   143     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   144     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   145     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   146 }
   148 static void sh4_load_sr( uint32_t newval )
   149 {
   150     if( (newval ^ sh4r.sr) & SR_RB )
   151         sh4_switch_banks();
   152     sh4r.sr = newval;
   153     sh4r.t = (newval&SR_T) ? 1 : 0;
   154     sh4r.s = (newval&SR_S) ? 1 : 0;
   155     sh4r.m = (newval&SR_M) ? 1 : 0;
   156     sh4r.q = (newval&SR_Q) ? 1 : 0;
   157     intc_mask_changed();
   158 }
   160 static uint32_t sh4_read_sr( void )
   161 {
   162     /* synchronize sh4r.sr with the various bitflags */
   163     sh4r.sr &= SR_MQSTMASK;
   164     if( sh4r.t ) sh4r.sr |= SR_T;
   165     if( sh4r.s ) sh4r.sr |= SR_S;
   166     if( sh4r.m ) sh4r.sr |= SR_M;
   167     if( sh4r.q ) sh4r.sr |= SR_Q;
   168     return sh4r.sr;
   169 }
   170 /* function for external use */
   171 void sh4_raise_exception( int code, int vector )
   172 {
   173     RAISE(code, vector);
   174 }
   176 static void sh4_accept_interrupt( void )
   177 {
   178     uint32_t code = intc_accept_interrupt();
   179     sh4r.ssr = sh4_read_sr();
   180     sh4r.spc = sh4r.pc;
   181     sh4r.sgr = sh4r.r[15];
   182     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   183     MMIO_WRITE( MMU, INTEVT, code );
   184     sh4r.pc = sh4r.vbr + 0x600;
   185     sh4r.new_pc = sh4r.pc + 2;
   186     WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   187 }
   189 void sh4_execute_instruction( void )
   190 {
   191     int pc;
   192     unsigned short ir;
   193     uint32_t tmp;
   194     uint64_t tmpl;
   196 #define R0 sh4r.r[0]
   197 #define FR0 (FR[0])
   198 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   199 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   200 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   201 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   202 #define DISP8(ir) (ir&0x00FF)
   203 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   204 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   205 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   206 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   207 #define FVN(ir) ((ir&0x0C00)>>8)
   208 #define FVM(ir) ((ir&0x0300)>>6)
   209 #define FRN(ir) (FR[(ir&0x0F00)>>8])
   210 #define FRM(ir) (FR[(ir&0x00F0)>>4])
   211 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
   212 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
   213 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
   214 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
   215 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
   216 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
   217 #define FRNn(ir) ((ir&0x0F00)>>8)
   218 #define FRMn(ir) ((ir&0x00F0)>>4)
   219 #define FPULf   *((float *)&sh4r.fpul)
   220 #define FPULi    (sh4r.fpul)
   222     if( SH4_INT_PENDING() ) 
   223         sh4_accept_interrupt();
   225     pc = sh4r.pc;
   226     ir = MEM_READ_WORD(pc);
   227     sh4r.icount++;
   229     switch( (ir&0xF000)>>12 ) {
   230         case 0: /* 0000nnnnmmmmxxxx */
   231             switch( ir&0x000F ) {
   232                 case 2:
   233                     switch( (ir&0x00F0)>>4 ) {
   234                         case 0: /* STC     SR, Rn */
   235                             CHECKPRIV();
   236                             RN(ir) = sh4_read_sr();
   237                             break;
   238                         case 1: /* STC     GBR, Rn */
   239                             RN(ir) = sh4r.gbr;
   240                             break;
   241                         case 2: /* STC     VBR, Rn */
   242                             CHECKPRIV();
   243                             RN(ir) = sh4r.vbr;
   244                             break;
   245                         case 3: /* STC     SSR, Rn */
   246                             CHECKPRIV();
   247                             RN(ir) = sh4r.ssr;
   248                             break;
   249                         case 4: /* STC     SPC, Rn */
   250                             CHECKPRIV();
   251                             RN(ir) = sh4r.spc;
   252                             break;
   253                         case 8: case 9: case 10: case 11: case 12: case 13:
   254                         case 14: case 15:/* STC     Rm_bank, Rn */
   255                             CHECKPRIV();
   256                             RN(ir) = RN_BANK(ir);
   257                             break;
   258                         default: UNDEF(ir);
   259                     }
   260                     break;
   261                 case 3:
   262                     switch( (ir&0x00F0)>>4 ) {
   263                         case 0: /* BSRF    Rn */
   264                             CHECKDEST( pc + 4 + RN(ir) );
   265                             CHECKSLOTILLEGAL();
   266                             sh4r.in_delay_slot = 1;
   267                             sh4r.pr = sh4r.pc + 4;
   268                             sh4r.pc = sh4r.new_pc;
   269                             sh4r.new_pc = pc + 4 + RN(ir);
   270                             return;
   271                         case 2: /* BRAF    Rn */
   272                             CHECKDEST( pc + 4 + RN(ir) );
   273                             CHECKSLOTILLEGAL();
   274                             sh4r.in_delay_slot = 1;
   275                             sh4r.pc = sh4r.new_pc;
   276                             sh4r.new_pc = pc + 4 + RN(ir);
   277                             return;
   278                         case 8: /* PREF    [Rn] */
   279                             tmp = RN(ir);
   280                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   281                                 /* Store queue operation */
   282                                 int queue = (tmp&0x20)>>2;
   283                                 int32_t *src = &sh4r.store_queue[queue];
   284                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   285                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   286                                 mem_copy_to_sh4( target, src, 32 );
   287                                 WARN( "Executed SQ%c => %08X",
   288                                       (queue == 0 ? '0' : '1'), target );
   289                             }
   290                             break;
   291                         case 9: /* OCBI    [Rn] */
   292                         case 10:/* OCBP    [Rn] */
   293                         case 11:/* OCBWB   [Rn] */
   294                             /* anything? */
   295                             break;
   296                         case 12:/* MOVCA.L R0, [Rn] */
   297                             UNIMP(ir);
   298                         default: UNDEF(ir);
   299                     }
   300                     break;
   301                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   302                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   303                     break;
   304                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   305                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   306                     break;
   307                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   308                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   309                     break;
   310                 case 7: /* MUL.L   Rm, Rn */
   311                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   312                         (RM(ir) * RN(ir));
   313                     break;
   314                 case 8: 
   315                     switch( (ir&0x0FF0)>>4 ) {
   316                         case 0: /* CLRT    */
   317                             sh4r.t = 0;
   318                             break;
   319                         case 1: /* SETT    */
   320                             sh4r.t = 1;
   321                             break;
   322                         case 2: /* CLRMAC  */
   323                             sh4r.mac = 0;
   324                             break;
   325                         case 3: /* LDTLB   */
   326                             break;
   327                         case 4: /* CLRS    */
   328                             sh4r.s = 0;
   329                             break;
   330                         case 5: /* SETS    */
   331                             sh4r.s = 1;
   332                             break;
   333                         default: UNDEF(ir);
   334                     }
   335                     break;
   336                 case 9: 
   337                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   338                         RN(ir) = sh4r.t;
   339                     else if( ir == 0x0019 ) /* DIV0U   */
   340                         sh4r.m = sh4r.q = sh4r.t = 0;
   341                     else if( ir == 0x0009 )
   342                         /* NOP     */;
   343                     else UNDEF(ir);
   344                     break;
   345                 case 10:
   346                     switch( (ir&0x00F0) >> 4 ) {
   347                         case 0: /* STS     MACH, Rn */
   348                             RN(ir) = sh4r.mac >> 32;
   349                             break;
   350                         case 1: /* STS     MACL, Rn */
   351                             RN(ir) = (uint32_t)sh4r.mac;
   352                             break;
   353                         case 2: /* STS     PR, Rn */
   354                             RN(ir) = sh4r.pr;
   355                             break;
   356                         case 3: /* STC     SGR, Rn */
   357                             CHECKPRIV();
   358                             RN(ir) = sh4r.sgr;
   359                             break;
   360                         case 5:/* STS      FPUL, Rn */
   361                             RN(ir) = sh4r.fpul;
   362                             break;
   363                         case 6: /* STS     FPSCR, Rn */
   364                             RN(ir) = sh4r.fpscr;
   365                             break;
   366                         case 15:/* STC     DBR, Rn */
   367                             CHECKPRIV();
   368                             RN(ir) = sh4r.dbr;
   369                             break;
   370                         default: UNDEF(ir);
   371                     }
   372                     break;
   373                 case 11:
   374                     switch( (ir&0x0FF0)>>4 ) {
   375                         case 0: /* RTS     */
   376                             CHECKDEST( sh4r.pr );
   377                             CHECKSLOTILLEGAL();
   378                             sh4r.in_delay_slot = 1;
   379                             sh4r.pc = sh4r.new_pc;
   380                             sh4r.new_pc = sh4r.pr;
   381                             return;
   382                         case 1: /* SLEEP   */
   383                             running = 0;
   384                             break;
   385                         case 2: /* RTE     */
   386                             CHECKPRIV();
   387                             CHECKDEST( sh4r.spc );
   388                             CHECKSLOTILLEGAL();
   389                             sh4r.in_delay_slot = 1;
   390                             sh4r.pc = sh4r.new_pc;
   391                             sh4r.new_pc = sh4r.spc;
   392                             sh4_load_sr( sh4r.ssr );
   393                             WARN( "RTE => %08X", sh4r.new_pc );
   394                             return;
   395                         default:UNDEF(ir);
   396                     }
   397                     break;
   398                 case 12:/* MOV.B   [R0+R%d], R%d */
   399                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   400                     break;
   401                 case 13:/* MOV.W   [R0+R%d], R%d */
   402                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   403                     break;
   404                 case 14:/* MOV.L   [R0+R%d], R%d */
   405                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   406                     break;
   407                 case 15:/* MAC.L   [Rm++], [Rn++] */
   408                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   409                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   410                     if( sh4r.s ) {
   411                         /* 48-bit Saturation. Yuch */
   412                         tmpl += SIGNEXT48(sh4r.mac);
   413                         if( tmpl < 0xFFFF800000000000LL )
   414                             tmpl = 0xFFFF800000000000LL;
   415                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   416                             tmpl = 0x00007FFFFFFFFFFFLL;
   417                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   418                             (tmpl&0x0000FFFFFFFFFFFFLL);
   419                     } else sh4r.mac = tmpl;
   421                     RM(ir) += 4;
   422                     RN(ir) += 4;
   424                     break;
   425                 default: UNDEF(ir);
   426             }
   427             break;
   428         case 1: /* 0001nnnnmmmmdddd */
   429             /* MOV.L   Rm, [Rn + disp4*4] */
   430             MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
   431             break;
   432         case 2: /* 0010nnnnmmmmxxxx */
   433             switch( ir&0x000F ) {
   434                 case 0: /* MOV.B   Rm, [Rn] */
   435                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   436                     break;
   437                 case 1: /* MOV.W   Rm, [Rn] */
   438                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   439                     break;
   440                 case 2: /* MOV.L   Rm, [Rn] */
   441                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   442                     break;
   443                 case 3: UNDEF(ir);
   444                     break;
   445                 case 4: /* MOV.B   Rm, [--Rn] */
   446                     RN(ir) --;
   447                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   448                     break;
   449                 case 5: /* MOV.W   Rm, [--Rn] */
   450                     RN(ir) -= 2;
   451                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   452                     break;
   453                 case 6: /* MOV.L   Rm, [--Rn] */
   454                     RN(ir) -= 4;
   455                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   456                     break;
   457                 case 7: /* DIV0S   Rm, Rn */
   458                     sh4r.q = RN(ir)>>31;
   459                     sh4r.m = RM(ir)>>31;
   460                     sh4r.t = sh4r.q ^ sh4r.m;
   461                     break;
   462                 case 8: /* TST     Rm, Rn */
   463                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   464                     break;
   465                 case 9: /* AND     Rm, Rn */
   466                     RN(ir) &= RM(ir);
   467                     break;
   468                 case 10:/* XOR     Rm, Rn */
   469                     RN(ir) ^= RM(ir);
   470                     break;
   471                 case 11:/* OR      Rm, Rn */
   472                     RN(ir) |= RM(ir);
   473                     break;
   474                 case 12:/* CMP/STR Rm, Rn */
   475                     /* set T = 1 if any byte in RM & RN is the same */
   476                     tmp = RM(ir) ^ RN(ir);
   477                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   478                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   479                     break;
   480                 case 13:/* XTRCT   Rm, Rn */
   481                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   482                     break;
   483                 case 14:/* MULU.W  Rm, Rn */
   484                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   485                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   486                     break;
   487                 case 15:/* MULS.W  Rm, Rn */
   488                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   489                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   490                     break;
   491             }
   492             break;
   493         case 3: /* 0011nnnnmmmmxxxx */
   494             switch( ir&0x000F ) {
   495                 case 0: /* CMP/EQ  Rm, Rn */
   496                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   497                     break;
   498                 case 2: /* CMP/HS  Rm, Rn */
   499                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   500                     break;
   501                 case 3: /* CMP/GE  Rm, Rn */
   502                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   503                     break;
   504                 case 4: { /* DIV1    Rm, Rn */
   505                     /* This is just from the sh4p manual with some
   506                      * simplifications (someone want to check it's correct? :)
   507                      * Why they couldn't just provide a real DIV instruction...
   508                      * Please oh please let the translator batch these things
   509                      * up into a single DIV... */
   510                     uint32_t tmp0, tmp1, tmp2, dir;
   512                     dir = sh4r.q ^ sh4r.m;
   513                     sh4r.q = (RN(ir) >> 31);
   514                     tmp2 = RM(ir);
   515                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   516                     tmp0 = RN(ir);
   517                     if( dir ) {
   518                         RN(ir) += tmp2;
   519                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   520                     } else {
   521                         RN(ir) -= tmp2;
   522                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   523                     }
   524                     sh4r.q ^= sh4r.m ^ tmp1;
   525                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   526                     break; }
   527                 case 5: /* DMULU.L Rm, Rn */
   528                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   529                     break;
   530                 case 6: /* CMP/HI  Rm, Rn */
   531                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   532                     break;
   533                 case 7: /* CMP/GT  Rm, Rn */
   534                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   535                     break;
   536                 case 8: /* SUB     Rm, Rn */
   537                     RN(ir) -= RM(ir);
   538                     break;
   539                 case 10:/* SUBC    Rm, Rn */
   540                     tmp = RN(ir);
   541                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   542                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   543                     break;
   544                 case 11:/* SUBV    Rm, Rn */
   545                     UNIMP(ir);
   546                     break;
   547                 case 12:/* ADD     Rm, Rn */
   548                     RN(ir) += RM(ir);
   549                     break;
   550                 case 13:/* DMULS.L Rm, Rn */
   551                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   552                     break;
   553                 case 14:/* ADDC    Rm, Rn */
   554                     tmp = RN(ir);
   555                     RN(ir) += RM(ir) + sh4r.t;
   556                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   557                     break;
   558                 case 15:/* ADDV    Rm, Rn */
   559                     UNIMP(ir);
   560                     break;
   561                 default: UNDEF(ir);
   562             }
   563             break;
   564         case 4: /* 0100nnnnxxxxxxxx */
   565             switch( ir&0x00FF ) {
   566                 case 0x00: /* SHLL    Rn */
   567                     sh4r.t = RN(ir) >> 31;
   568                     RN(ir) <<= 1;
   569                     break;
   570                 case 0x01: /* SHLR    Rn */
   571                     sh4r.t = RN(ir) & 0x00000001;
   572                     RN(ir) >>= 1;
   573                     break;
   574                 case 0x02: /* STS.L   MACH, [--Rn] */
   575                     RN(ir) -= 4;
   576                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   577                     break;
   578                 case 0x03: /* STC.L   SR, [--Rn] */
   579                     CHECKPRIV();
   580                     RN(ir) -= 4;
   581                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   582                     break;
   583                 case 0x04: /* ROTL    Rn */
   584                     sh4r.t = RN(ir) >> 31;
   585                     RN(ir) <<= 1;
   586                     RN(ir) |= sh4r.t;
   587                     break;
   588                 case 0x05: /* ROTR    Rn */
   589                     sh4r.t = RN(ir) & 0x00000001;
   590                     RN(ir) >>= 1;
   591                     RN(ir) |= (sh4r.t << 31);
   592                     break;
   593                 case 0x06: /* LDS.L   [Rn++], MACH */
   594                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   595                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   596                     RN(ir) += 4;
   597                     break;
   598                 case 0x07: /* LDC.L   [Rn++], SR */
   599                     CHECKPRIV();
   600                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   601                     RN(ir) +=4;
   602                     break;
   603                 case 0x08: /* SHLL2   Rn */
   604                     RN(ir) <<= 2;
   605                     break;
   606                 case 0x09: /* SHLR2   Rn */
   607                     RN(ir) >>= 2;
   608                     break;
   609                 case 0x0A: /* LDS     Rn, MACH */
   610                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   611                         (((uint64_t)RN(ir))<<32);
   612                     break;
   613                 case 0x0B: /* JSR     [Rn] */
   614                     CHECKDEST( RN(ir) );
   615                     CHECKSLOTILLEGAL();
   616                     sh4r.in_delay_slot = 1;
   617                     sh4r.pc = sh4r.new_pc;
   618                     sh4r.new_pc = RN(ir);
   619                     sh4r.pr = pc + 4;
   620                     return;
   621                 case 0x0E: /* LDC     Rn, SR */
   622                     CHECKPRIV();
   623                     sh4_load_sr( RN(ir) );
   624                     break;
   625                 case 0x10: /* DT      Rn */
   626                     RN(ir) --;
   627                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   628                     break;
   629                 case 0x11: /* CMP/PZ  Rn */
   630                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   631                     break;
   632                 case 0x12: /* STS.L   MACL, [--Rn] */
   633                     RN(ir) -= 4;
   634                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   635                     break;
   636                 case 0x13: /* STC.L   GBR, [--Rn] */
   637                     RN(ir) -= 4;
   638                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   639                     break;
   640                 case 0x15: /* CMP/PL  Rn */
   641                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   642                     break;
   643                 case 0x16: /* LDS.L   [Rn++], MACL */
   644                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   645                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   646                     RN(ir) += 4;
   647                     break;
   648                 case 0x17: /* LDC.L   [Rn++], GBR */
   649                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   650                     RN(ir) +=4;
   651                     break;
   652                 case 0x18: /* SHLL8   Rn */
   653                     RN(ir) <<= 8;
   654                     break;
   655                 case 0x19: /* SHLR8   Rn */
   656                     RN(ir) >>= 8;
   657                     break;
   658                 case 0x1A: /* LDS     Rn, MACL */
   659                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   660                         (uint64_t)((uint32_t)(RN(ir)));
   661                     break;
   662                 case 0x1B: /* TAS.B   [Rn] */
   663                     tmp = MEM_READ_BYTE( RN(ir) );
   664                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   665                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   666                     break;
   667                 case 0x1E: /* LDC     Rn, GBR */
   668                     sh4r.gbr = RN(ir);
   669                     break;
   670                 case 0x20: /* SHAL    Rn */
   671                     sh4r.t = RN(ir) >> 31;
   672                     RN(ir) <<= 1;
   673                     break;
   674                 case 0x21: /* SHAR    Rn */
   675                     sh4r.t = RN(ir) & 0x00000001;
   676                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   677                     break;
   678                 case 0x22: /* STS.L   PR, [--Rn] */
   679                     RN(ir) -= 4;
   680                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   681                     break;
   682                 case 0x23: /* STC.L   VBR, [--Rn] */
   683                     CHECKPRIV();
   684                     RN(ir) -= 4;
   685                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   686                     break;
   687                 case 0x24: /* ROTCL   Rn */
   688                     tmp = RN(ir) >> 31;
   689                     RN(ir) <<= 1;
   690                     RN(ir) |= sh4r.t;
   691                     sh4r.t = tmp;
   692                     break;
   693                 case 0x25: /* ROTCR   Rn */
   694                     tmp = RN(ir) & 0x00000001;
   695                     RN(ir) >>= 1;
   696                     RN(ir) |= (sh4r.t << 31 );
   697                     sh4r.t = tmp;
   698                     break;
   699                 case 0x26: /* LDS.L   [Rn++], PR */
   700                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   701                     RN(ir) += 4;
   702                     break;
   703                 case 0x27: /* LDC.L   [Rn++], VBR */
   704                     CHECKPRIV();
   705                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   706                     RN(ir) +=4;
   707                     break;
   708                 case 0x28: /* SHLL16  Rn */
   709                     RN(ir) <<= 16;
   710                     break;
   711                 case 0x29: /* SHLR16  Rn */
   712                     RN(ir) >>= 16;
   713                     break;
   714                 case 0x2A: /* LDS     Rn, PR */
   715                     sh4r.pr = RN(ir);
   716                     break;
   717                 case 0x2B: /* JMP     [Rn] */
   718                     CHECKDEST( RN(ir) );
   719                     CHECKSLOTILLEGAL();
   720                     sh4r.in_delay_slot = 1;
   721                     sh4r.pc = sh4r.new_pc;
   722                     sh4r.new_pc = RN(ir);
   723                     return;
   724                 case 0x2E: /* LDC     Rn, VBR */
   725                     CHECKPRIV();
   726                     sh4r.vbr = RN(ir);
   727                     break;
   728                 case 0x32: /* STC.L   SGR, [--Rn] */
   729                     CHECKPRIV();
   730                     RN(ir) -= 4;
   731                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
   732                     break;
   733                 case 0x33: /* STC.L   SSR, [--Rn] */
   734                     CHECKPRIV();
   735                     RN(ir) -= 4;
   736                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
   737                     break;
   738                 case 0x37: /* LDC.L   [Rn++], SSR */
   739                     CHECKPRIV();
   740                     sh4r.ssr = MEM_READ_LONG(RN(ir));
   741                     RN(ir) +=4;
   742                     break;
   743                 case 0x3E: /* LDC     Rn, SSR */
   744                     CHECKPRIV();
   745                     sh4r.ssr = RN(ir);
   746                     break;
   747                 case 0x43: /* STC.L   SPC, [--Rn] */
   748                     CHECKPRIV();
   749                     RN(ir) -= 4;
   750                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
   751                     break;
   752                 case 0x47: /* LDC.L   [Rn++], SPC */
   753                     CHECKPRIV();
   754                     sh4r.spc = MEM_READ_LONG(RN(ir));
   755                     RN(ir) +=4;
   756                     break;
   757                 case 0x4E: /* LDC     Rn, SPC */
   758                     CHECKPRIV();
   759                     sh4r.spc = RN(ir);
   760                     break;
   761                 case 0x52: /* STS.L   FPUL, [--Rn] */
   762                     RN(ir) -= 4;
   763                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
   764                     break;
   765                 case 0x56: /* LDS.L   [Rn++], FPUL */
   766                     sh4r.fpul = MEM_READ_LONG(RN(ir));
   767                     RN(ir) +=4;
   768                     break;
   769                 case 0x5A: /* LDS     Rn, FPUL */
   770                     sh4r.fpul = RN(ir);
   771                     break;
   772                 case 0x62: /* STS.L   FPSCR, [--Rn] */
   773                     RN(ir) -= 4;
   774                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
   775                     break;
   776                 case 0x66: /* LDS.L   [Rn++], FPSCR */
   777                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
   778                     RN(ir) +=4;
   779                     break;
   780                 case 0x6A: /* LDS     Rn, FPSCR */
   781                     sh4r.fpscr = RN(ir);
   782                     break;
   783                 case 0xF2: /* STC.L   DBR, [--Rn] */
   784                     CHECKPRIV();
   785                     RN(ir) -= 4;
   786                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
   787                     break;
   788                 case 0xF6: /* LDC.L   [Rn++], DBR */
   789                     CHECKPRIV();
   790                     sh4r.dbr = MEM_READ_LONG(RN(ir));
   791                     RN(ir) +=4;
   792                     break;
   793                 case 0xFA: /* LDC     Rn, DBR */
   794                     CHECKPRIV();
   795                     sh4r.dbr = RN(ir);
   796                     break;
   797                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
   798                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
   799                     CHECKPRIV();
   800                     RN(ir) -= 4;
   801                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
   802                     break;
   803                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
   804                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
   805                     CHECKPRIV();
   806                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
   807                     RN(ir) += 4;
   808                     break;
   809                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
   810                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
   811                     CHECKPRIV();
   812                     RN_BANK(ir) = RM(ir);
   813                     break;
   814                 default:
   815                     if( (ir&0x000F) == 0x0F ) {
   816                         /* MAC.W   [Rm++], [Rn++] */
   817                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
   818                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
   819                         if( sh4r.s ) {
   820                             /* FIXME */
   821                             UNIMP(ir);
   822                         } else sh4r.mac += SIGNEXT32(tmp);
   823                         RM(ir) += 2;
   824                         RN(ir) += 2;
   825                     } else if( (ir&0x000F) == 0x0C ) {
   826                         /* SHAD    Rm, Rn */
   827                         tmp = RM(ir);
   828                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   829                         else if( (tmp & 0x1F) == 0 )  
   830 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
   831                         else 
   832 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
   833                     } else if( (ir&0x000F) == 0x0D ) {
   834                         /* SHLD    Rm, Rn */
   835                         tmp = RM(ir);
   836                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   837                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
   838                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
   839                     } else UNDEF(ir);
   840             }
   841             break;
   842         case 5: /* 0101nnnnmmmmdddd */
   843             /* MOV.L   [Rm + disp4*4], Rn */
   844             RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
   845             break;
   846         case 6: /* 0110xxxxxxxxxxxx */
   847             switch( ir&0x000f ) {
   848                 case 0: /* MOV.B   [Rm], Rn */
   849                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   850                     break;
   851                 case 1: /* MOV.W   [Rm], Rn */
   852                     RN(ir) = MEM_READ_WORD( RM(ir) );
   853                     break;
   854                 case 2: /* MOV.L   [Rm], Rn */
   855                     RN(ir) = MEM_READ_LONG( RM(ir) );
   856                     break;
   857                 case 3: /* MOV     Rm, Rn */
   858                     RN(ir) = RM(ir);
   859                     break;
   860                 case 4: /* MOV.B   [Rm++], Rn */
   861                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   862                     RM(ir) ++;
   863                     break;
   864                 case 5: /* MOV.W   [Rm++], Rn */
   865                     RN(ir) = MEM_READ_WORD( RM(ir) );
   866                     RM(ir) += 2;
   867                     break;
   868                 case 6: /* MOV.L   [Rm++], Rn */
   869                     RN(ir) = MEM_READ_LONG( RM(ir) );
   870                     RM(ir) += 4;
   871                     break;
   872                 case 7: /* NOT     Rm, Rn */
   873                     RN(ir) = ~RM(ir);
   874                     break;
   875                 case 8: /* SWAP.B  Rm, Rn */
   876                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
   877                         ((RM(ir)&0x000000FF)<<8);
   878                     break;
   879                 case 9: /* SWAP.W  Rm, Rn */
   880                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
   881                     break;
   882                 case 10:/* NEGC    Rm, Rn */
   883                     tmp = 0 - RM(ir);
   884                     RN(ir) = tmp - sh4r.t;
   885                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
   886                     break;
   887                 case 11:/* NEG     Rm, Rn */
   888                     RN(ir) = 0 - RM(ir);
   889                     break;
   890                 case 12:/* EXTU.B  Rm, Rn */
   891                     RN(ir) = RM(ir)&0x000000FF;
   892                     break;
   893                 case 13:/* EXTU.W  Rm, Rn */
   894                     RN(ir) = RM(ir)&0x0000FFFF;
   895                     break;
   896                 case 14:/* EXTS.B  Rm, Rn */
   897                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
   898                     break;
   899                 case 15:/* EXTS.W  Rm, Rn */
   900                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
   901                     break;
   902             }
   903             break;
   904         case 7: /* 0111nnnniiiiiiii */
   905             /* ADD    imm8, Rn */
   906             RN(ir) += IMM8(ir);
   907             break;
   908         case 8: /* 1000xxxxxxxxxxxx */
   909             switch( (ir&0x0F00) >> 8 ) {
   910                 case 0: /* MOV.B   R0, [Rm + disp4] */
   911                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
   912                     break;
   913                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
   914                     MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
   915                     break;
   916                 case 4: /* MOV.B   [Rm + disp4], R0 */
   917                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
   918                     break;
   919                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
   920                     R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
   921                     break;
   922                 case 8: /* CMP/EQ  imm, R0 */
   923                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
   924                     break;
   925                 case 9: /* BT      disp8 */
   926                     CHECKSLOTILLEGAL()
   927                     if( sh4r.t ) {
   928                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   929                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
   930                         sh4r.new_pc = sh4r.pc + 2;
   931                         return;
   932                     }
   933                     break;
   934                 case 11:/* BF      disp8 */
   935                     CHECKSLOTILLEGAL()
   936                     if( !sh4r.t ) {
   937                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   938                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
   939                         sh4r.new_pc = sh4r.pc + 2;
   940                         return;
   941                     }
   942                     break;
   943                 case 13:/* BT/S    disp8 */
   944                     CHECKSLOTILLEGAL()
   945                     if( sh4r.t ) {
   946                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   947                         sh4r.in_delay_slot = 1;
   948                         sh4r.pc = sh4r.new_pc;
   949                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
   950                         sh4r.in_delay_slot = 1;
   951                         return;
   952                     }
   953                     break;
   954                 case 15:/* BF/S    disp8 */
   955                     CHECKSLOTILLEGAL()
   956                     if( !sh4r.t ) {
   957                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   958                         sh4r.in_delay_slot = 1;
   959                         sh4r.pc = sh4r.new_pc;
   960                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
   961                         return;
   962                     }
   963                     break;
   964                 default: UNDEF(ir);
   965             }
   966             break;
   967         case 9: /* 1001xxxxxxxxxxxx */
   968             /* MOV.W   [disp8*2 + pc + 4], Rn */
   969             RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
   970             break;
   971         case 10:/* 1010dddddddddddd */
   972             /* BRA     disp12 */
   973             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
   974             CHECKSLOTILLEGAL()
   975             sh4r.in_delay_slot = 1;
   976             sh4r.pc = sh4r.new_pc;
   977             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
   978             return;
   979         case 11:/* 1011dddddddddddd */
   980             /* BSR     disp12 */
   981             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
   982             CHECKSLOTILLEGAL()
   983             sh4r.in_delay_slot = 1;
   984             sh4r.pr = pc + 4;
   985             sh4r.pc = sh4r.new_pc;
   986             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
   987             return;
   988         case 12:/* 1100xxxxdddddddd */
   989         switch( (ir&0x0F00)>>8 ) {
   990                 case 0: /* MOV.B  R0, [GBR + disp8] */
   991                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
   992                     break;
   993                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
   994                     MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
   995                     break;
   996                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
   997                     MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
   998                     break;
   999                 case 3: /* TRAPA   imm8 */
  1000                     CHECKSLOTILLEGAL()
  1001                     sh4r.in_delay_slot = 1;
  1002                     MMIO_WRITE( MMU, TRA, UIMM8(ir) );
  1003                     sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */
  1004                     sh4r.new_pc += 2;
  1005                     RAISE( EXC_TRAP, EXV_TRAP );
  1006                     break;
  1007                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1008                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1009                     break;
  1010                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1011                     R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
  1012                     break;
  1013                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1014                     R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
  1015                     break;
  1016                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1017                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1018                     break;
  1019                 case 8: /* TST     imm8, R0 */
  1020                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1021                     break;
  1022                 case 9: /* AND     imm8, R0 */
  1023                     R0 &= UIMM8(ir);
  1024                     break;
  1025                 case 10:/* XOR     imm8, R0 */
  1026                     R0 ^= UIMM8(ir);
  1027                     break;
  1028                 case 11:/* OR      imm8, R0 */
  1029                     R0 |= UIMM8(ir);
  1030                     break;
  1031                 case 12:/* TST.B   imm8, [R0+GBR] */
  1032                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1033                     break;
  1034                 case 13:/* AND.B   imm8, [R0+GBR] */
  1035                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1036                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1037                     break;
  1038                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1039                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1040                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1041                     break;
  1042                 case 15:/* OR.B    imm8, [R0+GBR] */
  1043                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1044                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1045                     break;
  1047             break;
  1048         case 13:/* 1101nnnndddddddd */
  1049             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1050             RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
  1051             break;
  1052         case 14:/* 1110nnnniiiiiiii */
  1053             /* MOV     imm8, Rn */
  1054             RN(ir) = IMM8(ir);
  1055             break;
  1056         case 15:/* 1111xxxxxxxxxxxx */
  1057             CHECKFPUEN();
  1058             switch( ir&0x000F ) {
  1059                 case 0: /* FADD    FRm, FRn */
  1060                     FRN(ir) += FRM(ir);
  1061                     break;
  1062                 case 1: /* FSUB    FRm, FRn */
  1063                     FRN(ir) -= FRM(ir);
  1064                     break;
  1065                 case 2: /* FMUL    FRm, FRn */
  1066                     FRN(ir) = FRN(ir) * FRM(ir);
  1067                     break;
  1068                 case 3: /* FDIV    FRm, FRn */
  1069                     FRN(ir) = FRN(ir) / FRM(ir);
  1070                     break;
  1071                 case 4: /* FCMP/EQ FRm, FRn */
  1072                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1073                     break;
  1074                 case 5: /* FCMP/GT FRm, FRn */
  1075                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1076                     break;
  1077                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1078                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1079                     break;
  1080                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1081                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1082                     break;
  1083                 case 8: /* FMOV.S  [Rm], FRn */
  1084                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1085                     break;
  1086                 case 9: /* FMOV.S  [Rm++], FRn */
  1087                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1088                     RM(ir) += FP_WIDTH;
  1089                     break;
  1090                 case 10:/* FMOV.S  FRm, [Rn] */
  1091                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1092                     break;
  1093                 case 11:/* FMOV.S  FRm, [--Rn] */
  1094                     RN(ir) -= FP_WIDTH;
  1095                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1096                     break;
  1097                 case 12:/* FMOV    FRm, FRn */
  1098                     if( IS_FPU_DOUBLESIZE() ) {
  1099                         DRN(ir) = DRM(ir);
  1100                     } else {
  1101                         FRN(ir) = FRM(ir);
  1103                     break;
  1104                 case 13:
  1105                     switch( (ir&0x00F0) >> 4 ) {
  1106                         case 0: /* FSTS    FPUL, FRn */
  1107                             FRN(ir) = FPULf;
  1108                             break;
  1109                         case 1: /* FLDS    FRn, FPUL */
  1110                             FPULf = FRN(ir);
  1111                             break;
  1112                         case 2: /* FLOAT   FPUL, FRn */
  1113                             FRN(ir) = (float)FPULi;
  1114                             break;
  1115                         case 3: /* FTRC    FRn, FPUL */
  1116                             FPULi = (uint32_t)FRN(ir);
  1117                             /* FIXME: is this sufficient? */
  1118                             break;
  1119                         case 4: /* FNEG    FRn */
  1120                             FRN(ir) = -FRN(ir);
  1121                             break;
  1122                         case 5: /* FABS    FRn */
  1123                             FRN(ir) = fabsf(FRN(ir));
  1124                             break;
  1125                         case 6: /* FSQRT   FRn */
  1126                             FRN(ir) = sqrtf(FRN(ir));
  1127                             break;
  1128                         case 7: /* FSRRA FRn */
  1129                             FRN(ir) = 1.0/sqrtf(FRN(ir));
  1130                             break;
  1131                         case 8: /* FLDI0   FRn */
  1132                             FRN(ir) = 0.0;
  1133                             break;
  1134                         case 9: /* FLDI1   FRn */
  1135                             FRN(ir) = 1.0;
  1136                             break;
  1137                         case 10: /* FCNVSD FPUL, DRn */
  1138                             if( IS_FPU_DOUBLEPREC() )
  1139                                 DRN(ir) = (double)FPULf;
  1140                             else UNDEF(ir);
  1141                             break;
  1142                         case 11: /* FCNVDS DRn, FPUL */
  1143                             if( IS_FPU_DOUBLEPREC() ) 
  1144                                 FPULf = (float)DRN(ir);
  1145                             else UNDEF(ir);
  1146                             break;
  1147                         case 14:/* FIPR    FVm, FVn */
  1148                             /* FIXME: This is not going to be entirely accurate
  1149                              * as the SH4 instruction is less precise. Also
  1150                              * need to check for 0s and infinities.
  1151                              */
  1153                             float *fr_bank = FR;
  1154                             int tmp2 = FVN(ir);
  1155                             tmp = FVM(ir);
  1156                             fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
  1157                                 fr_bank[tmp+1]*fr_bank[tmp2+1] +
  1158                                 fr_bank[tmp+2]*fr_bank[tmp2+2] +
  1159                                 fr_bank[tmp+3]*fr_bank[tmp2+3];
  1160                             break;
  1162                         case 15:
  1163                             if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1164                                 float *fvout = FR+FVN(ir);
  1165                                 float *xm = XF;
  1166                                 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
  1167                                 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
  1168                                     xm[8]*fv[2] + xm[12]*fv[3];
  1169                                 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
  1170                                     xm[9]*fv[2] + xm[13]*fv[3];
  1171                                 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
  1172                                     xm[10]*fv[2] + xm[14]*fv[3];
  1173                                 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
  1174                                     xm[11]*fv[2] + xm[15]*fv[3];
  1175                                 break;
  1177                             else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1178                                 float angle = (((float)(short)(FPULi>>16)) +
  1179                                                ((float)(FPULi&16)/65536.0)) *
  1180                                     2 * M_PI;
  1181                                 int reg = FRNn(ir);
  1182                                 FR[reg] = sinf(angle);
  1183                                 FR[reg+1] = cosf(angle);
  1184                                 break;
  1186                             else if( ir == 0xFBFD ) {
  1187                                 /* FRCHG   */
  1188                                 sh4r.fpscr ^= FPSCR_FR;
  1189                                 break;
  1191                             else if( ir == 0xF3FD ) {
  1192                                 /* FSCHG   */
  1193                                 sh4r.fpscr ^= FPSCR_SZ;
  1194                                 break;
  1196                         default: UNDEF(ir);
  1198                     break;
  1199                 case 14:/* FMAC    FR0, FRm, FRn */
  1200                     FRN(ir) += FRM(ir)*FR0;
  1201                     break;
  1202                 default: UNDEF(ir);
  1204             break;
  1206     sh4r.pc = sh4r.new_pc;
  1207     sh4r.new_pc += 2;
  1208     sh4r.in_delay_slot = 0;
.