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lxdream.org :: lxdream/src/sh4/intc.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/intc.h
changeset 561:533f6b478071
prev31:495e480360d7
next736:a02d1475ccfd
author nkeynes
date Tue Jan 01 05:08:38 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Enable Id keyword on all source files
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     1 /**
     2  * $Id$
     3  *
     4  * SH4 onboard interrupt controller (INTC) definitions.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    19 #ifndef sh4intc_H
    20 #define sh4intc_H 1
    22 #include "sh4core.h"
    24 #ifdef __cplusplus
    25 extern "C" {
    26 #if 0
    27 }
    28 #endif
    29 #endif
    31 #define INT_IRQ0        0     /* External Interrupt request 0 */
    32 #define INT_IRQ1        1
    33 #define INT_IRQ2        2
    34 #define INT_IRQ3        3
    35 #define INT_IRQ4        4
    36 #define INT_IRQ5        5
    37 #define INT_IRQ6        6
    38 #define INT_IRQ7        7
    39 #define INT_IRQ8        8
    40 #define INT_IRQ9        9
    41 #define INT_IRQ10      10
    42 #define INT_IRQ11      11
    43 #define INT_IRQ12      12
    44 #define INT_IRQ13      13
    45 #define INT_IRQ14      14
    46 #define INT_NMI        15     /* Non-Maskable Interrupt */
    47 #define INT_HUDI       16     /* Hitachi use debug interface */
    48 #define INT_GPIO       17     /* I/O port interrupt */
    49 #define INT_DMA_DMTE0  18     /* DMA transfer end 0 */
    50 #define INT_DMA_DMTE1  19     /* DMA transfer end 1 */
    51 #define INT_DMA_DMTE2  20     /* DMA transfer end 2 */
    52 #define INT_DMA_DMTE3  21     /* DMA transfer end 3 */
    53 #define INT_DMA_DMAE   22     /* DMA address error */
    54 #define INT_TMU_TUNI0  23     /* Timer underflow interrupt 0 */
    55 #define INT_TMU_TUNI1  24     /* Timer underflow interrupt 1 */
    56 #define INT_TMU_TUNI2  25     /* Timer underflow interrupt 2 */
    57 #define INT_TMU_TICPI2 26     /* Timer input capture interrupt */
    58 #define INT_RTC_ATI    27     /* RTC Alarm interrupt */
    59 #define INT_RTC_PRI    28     /* RTC periodic interrupt */
    60 #define INT_RTC_CUI    29     /* RTC Carry-up interrupt */
    61 #define INT_SCI_ERI    30     /* SCI receive-error interrupt */
    62 #define INT_SCI_RXI    31     /* SCI receive-data-full interrupt */
    63 #define INT_SCI_TXI    32     /* SCI transmit-data-empty interrupt */
    64 #define INT_SCI_TEI    33     /* SCI transmit-end interrupt */
    65 #define INT_SCIF_ERI   34     /* SCIF receive-error interrupt */
    66 #define INT_SCIF_RXI   35     /* SCIF receive-data-full interrupt */
    67 #define INT_SCIF_BRI   36     /* SCIF break interrupt request */
    68 #define INT_SCIF_TXI   37     /* SCIF Transmit-data-empty interrupt */
    69 #define INT_WDT_ITI    38     /* WDT Interval timer interval (CPG) */
    70 #define INT_REF_RCMI   39     /* Compare-match interrupt */
    71 #define INT_REF_ROVI   40     /* Refresh counter overflow interrupt */
    73 #define INT_NUM_SOURCES 41
    75 char *intc_get_interrupt_name( int which );
    76 void intc_raise_interrupt( int which );
    77 void intc_clear_interrupt( int which );
    78 uint32_t intc_accept_interrupt( void );
    79 void intc_reset( void );
    80 void intc_mask_changed( void );
    82 #ifdef __cplusplus
    83 }
    84 #endif
    86 #endif /* !sh4intc_H */
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