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lxdream.org :: lxdream/src/sh4/sh4core.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 561:533f6b478071
prev559:06714bc64271
next564:dc7b5ffb0535
author nkeynes
date Tue Jan 01 05:08:38 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Enable Id keyword on all source files
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     1 /**
     2  * $Id$
     3  * 
     4  * This file defines the internal functions exported/used by the SH4 core, 
     5  * except for disassembly functions defined in sh4dasm.h
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #ifndef sh4core_H
    21 #define sh4core_H 1
    23 #include <glib/gtypes.h>
    24 #include <stdint.h>
    25 #include <stdio.h>
    26 #include "mem.h"
    28 #ifdef __cplusplus
    29 extern "C" {
    30 #if 0
    31 }
    32 #endif
    33 #endif
    36 /**
    37  * SH4 is running normally 
    38  */
    39 #define SH4_STATE_RUNNING 1
    40 /**
    41  * SH4 is not executing instructions but all peripheral modules are still
    42  * running
    43  */
    44 #define SH4_STATE_SLEEP 2
    45 /**
    46  * SH4 is not executing instructions, DMAC is halted, but all other peripheral
    47  * modules are still running
    48  */
    49 #define SH4_STATE_DEEP_SLEEP 3
    50 /**
    51  * SH4 is not executing instructions and all peripheral modules are also
    52  * stopped. As close as you can get to powered-off without actually being
    53  * off.
    54  */
    55 #define SH4_STATE_STANDBY 4
    57 #define PENDING_IRQ 1
    58 #define PENDING_EVENT 2
    60 struct sh4_registers {
    61     uint32_t r[16];
    62     uint32_t sr, pr, pc, fpscr;
    63     uint32_t t, m, q, s; /* really boolean - 0 or 1 */
    64     int32_t fpul;
    65     float *fr_bank;
    66     float fr[2][16];
    67     uint64_t mac;
    68     uint32_t gbr, ssr, spc, sgr, dbr, vbr;
    70     uint32_t r_bank[8]; /* hidden banked registers */
    71     int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
    73     uint32_t new_pc; /* Not a real register, but used to handle delay slots */
    74     uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
    75                              when no events are pending */
    76     uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
    77     int in_delay_slot; /* flag to indicate the current instruction is in
    78                              * a delay slot (certain rules apply) */
    79     uint32_t slice_cycle; /* Current nanosecond within the timeslice */
    80     int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
    81 };
    83 extern struct sh4_registers sh4r;
    84 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    85 extern int sh4_breakpoint_count;
    88 /* Public functions */
    89 void sh4_set_use_xlat( gboolean use );
    90 void sh4_init( void );
    91 void sh4_reset( void );
    92 void sh4_run( void );
    93 void sh4_runto( uint32_t pc, uint32_t count );
    94 void sh4_runfor( uint32_t count );
    95 int sh4_isrunning( void );
    96 void sh4_stop( void );
    97 void sh4_set_pc( int );
    98 void sh4_sleep( void );
    99 void sh4_fsca( uint32_t angle, float *fr );
   100 void sh4_ftrv( float *fv, float *xmtrx );
   101 void signsat48(void);
   103 gboolean sh4_execute_instruction( void );
   104 gboolean sh4_raise_exception( int );
   105 gboolean sh4_raise_reset( int );
   106 gboolean sh4_raise_trap( int );
   107 gboolean sh4_raise_slot_exception( int, int );
   108 gboolean sh4_raise_tlb_exception( int );
   109 void sh4_set_breakpoint( uint32_t pc, int type );
   110 gboolean sh4_clear_breakpoint( uint32_t pc, int type );
   111 int sh4_get_breakpoint( uint32_t pc );
   112 void sh4_accept_interrupt( void );
   114 #define BREAK_ONESHOT 1
   115 #define BREAK_PERM 2
   117 /* SH4 Memory */
   118 uint64_t mmu_vma_to_phys_read( sh4addr_t addr );
   119 uint64_t mmu_vma_to_phys_write( sh4addr_t addr );
   120 uint64_t mmu_vma_to_phys_exec( sh4addr_t addr );
   122 int64_t sh4_read_quad( sh4addr_t addr );
   123 int64_t sh4_read_long( sh4addr_t addr );
   124 int64_t sh4_read_word( sh4addr_t addr );
   125 int64_t sh4_read_byte( sh4addr_t addr );
   126 void sh4_write_quad( sh4addr_t addr, uint64_t val );
   127 int32_t sh4_write_long( sh4addr_t addr, uint32_t val );
   128 int32_t sh4_write_word( sh4addr_t addr, uint32_t val );
   129 int32_t sh4_write_byte( sh4addr_t addr, uint32_t val );
   130 int32_t sh4_read_phys_word( sh4addr_t addr );
   131 void sh4_flush_store_queue( sh4addr_t addr );
   132 sh4ptr_t sh4_get_region_by_vma( sh4addr_t addr );
   134 /* SH4 Support methods */
   135 uint32_t sh4_read_sr(void);
   136 void sh4_write_sr(uint32_t val);
   138 /* Peripheral functions */
   139 void CPG_reset( void );
   140 void TMU_run_slice( uint32_t );
   141 void TMU_update_clocks( void );
   142 void TMU_reset( void );
   143 void TMU_save_state( FILE * );
   144 int TMU_load_state( FILE * );
   145 void DMAC_reset( void );
   146 void DMAC_run_slice( uint32_t );
   147 void DMAC_save_state( FILE * );
   148 int DMAC_load_state( FILE * );
   149 void SCIF_reset( void );
   150 void SCIF_run_slice( uint32_t );
   151 void SCIF_save_state( FILE *f );
   152 int SCIF_load_state( FILE *f );
   153 void INTC_reset( void );
   154 void INTC_save_state( FILE *f );
   155 int INTC_load_state( FILE *f );
   156 void MMU_init( void );
   157 void MMU_reset( void );
   158 void MMU_save_state( FILE *f );
   159 int MMU_load_state( FILE *f );
   160 void MMU_ldtlb();
   161 void SCIF_update_line_speed(void);
   163 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
   164 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
   165 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
   166 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
   167 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
   168 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
   169 #define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n))))
   171 /* Status Register (SR) bits */
   172 #define SR_MD    0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ 
   173 #define SR_RB    0x20000000 /* Register bank (priviledged mode only) */
   174 #define SR_BL    0x10000000 /* Exception/interupt block (1 = masked) */
   175 #define SR_FD    0x00008000 /* FPU disable */
   176 #define SR_M     0x00000200
   177 #define SR_Q     0x00000100
   178 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
   179 #define SR_S     0x00000002 /* Saturation operation for MAC instructions */
   180 #define SR_T     0x00000001 /* True/false or carry/borrow */
   181 #define SR_MASK  0x700083F3
   182 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
   184 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
   185 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
   186 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
   188 #define FPSCR_FR     0x00200000 /* FPU register bank */
   189 #define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
   190 #define FPSCR_PR     0x00080000 /* Precision (0=32 bites, 1=64 bits) */
   191 #define FPSCR_DN     0x00040000 /* Denormalization mode (1 = treat as 0) */
   192 #define FPSCR_CAUSE  0x0003F000
   193 #define FPSCR_ENABLE 0x00000F80
   194 #define FPSCR_FLAG   0x0000007C
   195 #define FPSCR_RM     0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
   197 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
   198 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
   199 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
   201 #define FR(x) sh4r.fr_bank[(x)^1]
   202 #define DRF(x) ((double *)sh4r.fr_bank)[x]
   203 #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
   204 #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
   205 #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
   206 #define DR(x) DRb((x>>1), (x&1))
   207 #define FPULf   *((float *)&sh4r.fpul)
   208 #define FPULi    (sh4r.fpul)
   210 /* CPU-generated exception code/vector pairs */
   211 #define EXC_POWER_RESET     0x000 /* vector special */
   212 #define EXC_MANUAL_RESET    0x020
   213 #define EXC_TLB_MISS_READ   0x040
   214 #define EXC_TLB_MISS_WRITE  0x060
   215 #define EXC_INIT_PAGE_WRITE 0x080
   216 #define EXC_TLB_PROT_READ   0x0A0
   217 #define EXC_TLB_PROT_WRITE  0x0C0
   218 #define EXC_DATA_ADDR_READ  0x0E0
   219 #define EXC_DATA_ADDR_WRITE 0x100
   220 #define EXC_TLB_MULTI_HIT   0x140
   221 #define EXC_SLOT_ILLEGAL    0x1A0
   222 #define EXC_ILLEGAL         0x180
   223 #define EXC_TRAP            0x160
   224 #define EXC_FPU_DISABLED    0x800
   225 #define EXC_SLOT_FPU_DISABLED 0x820
   227 #define EXV_EXCEPTION    0x100  /* General exception vector */
   228 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
   229 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
   231 /* Exceptions (for use with sh4_raise_exception) */
   233 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
   234 #define EX_SLOT_ILLEGAL        0x1A0, 0x100
   235 #define EX_TLB_MISS_READ       0x040, 0x400
   236 #define EX_TLB_MISS_WRITE      0x060, 0x400
   237 #define EX_INIT_PAGE_WRITE     0x080, 0x100
   238 #define EX_TLB_PROT_READ       0x0A0, 0x100
   239 #define EX_TLB_PROT_WRITE      0x0C0, 0x100
   240 #define EX_DATA_ADDR_READ      0x0E0, 0x100
   241 #define EX_DATA_ADDR_WRITE     0x100, 0x100
   242 #define EX_FPU_EXCEPTION       0x120, 0x100
   243 #define EX_TRAPA               0x160, 0x100
   244 #define EX_BREAKPOINT          0x1E0, 0x100
   245 #define EX_FPU_DISABLED        0x800, 0x100
   246 #define EX_SLOT_FPU_DISABLED   0x820, 0x100
   248 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
   250 #ifdef __cplusplus
   251 }
   252 #endif
   253 #endif
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