4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "dreamcast.h"
28 #include "sh4/sh4core.h"
29 #include "sh4/sh4mmio.h"
32 #define SH4_CALLTRACE 1
34 #define MAX_INT 0x7FFFFFFF
35 #define MIN_INT 0x80000000
36 #define MAX_INTF 2147483647.0
37 #define MIN_INTF -2147483648.0
39 /********************** SH4 Module Definition ****************************/
41 uint16_t *sh4_icache = NULL;
42 uint32_t sh4_icache_addr = 0;
44 uint32_t sh4_run_slice( uint32_t nanosecs )
49 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
50 if( sh4r.event_pending < nanosecs ) {
51 sh4r.sh4_state = SH4_STATE_RUNNING;
52 sh4r.slice_cycle = sh4r.event_pending;
56 if( sh4_breakpoint_count == 0 ) {
57 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
58 if( SH4_EVENT_PENDING() ) {
59 if( sh4r.event_types & PENDING_EVENT ) {
62 /* Eventq execute may (quite likely) deliver an immediate IRQ */
63 if( sh4r.event_types & PENDING_IRQ ) {
64 sh4_accept_interrupt();
67 if( !sh4_execute_instruction() ) {
72 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
73 if( SH4_EVENT_PENDING() ) {
74 if( sh4r.event_types & PENDING_EVENT ) {
77 /* Eventq execute may (quite likely) deliver an immediate IRQ */
78 if( sh4r.event_types & PENDING_IRQ ) {
79 sh4_accept_interrupt();
83 if( !sh4_execute_instruction() )
85 #ifdef ENABLE_DEBUG_MODE
86 for( i=0; i<sh4_breakpoint_count; i++ ) {
87 if( sh4_breakpoints[i].address == sh4r.pc ) {
91 if( i != sh4_breakpoint_count ) {
93 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
94 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
101 /* If we aborted early, but the cpu is still technically running,
102 * we're doing a hard abort - cut the timeslice back to what we
105 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
106 nanosecs = sh4r.slice_cycle;
108 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
109 TMU_run_slice( nanosecs );
110 SCIF_run_slice( nanosecs );
115 /********************** SH4 emulation core ****************************/
117 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
118 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
120 #if(SH4_CALLTRACE == 1)
121 #define MAX_CALLSTACK 32
122 static struct call_stack {
124 sh4addr_t target_addr;
125 sh4addr_t stack_pointer;
126 } call_stack[MAX_CALLSTACK];
128 static int call_stack_depth = 0;
129 int sh4_call_trace_on = 0;
131 static inline void trace_call( sh4addr_t source, sh4addr_t dest )
133 if( call_stack_depth < MAX_CALLSTACK ) {
134 call_stack[call_stack_depth].call_addr = source;
135 call_stack[call_stack_depth].target_addr = dest;
136 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
141 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
143 if( call_stack_depth > 0 ) {
148 void fprint_stack_trace( FILE *f )
150 int i = call_stack_depth -1;
151 if( i >= MAX_CALLSTACK )
152 i = MAX_CALLSTACK - 1;
153 for( ; i >= 0; i-- ) {
154 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
155 (call_stack_depth - i), call_stack[i].call_addr,
156 call_stack[i].target_addr, call_stack[i].stack_pointer );
160 #define TRACE_CALL( source, dest ) trace_call(source, dest)
161 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
163 #define TRACE_CALL( dest, rts )
164 #define TRACE_RETURN( source, dest )
167 #define MEM_READ_BYTE( addr, val ) memtmp = sh4_read_byte(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }
168 #define MEM_READ_WORD( addr, val ) memtmp = sh4_read_word(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }
169 #define MEM_READ_LONG( addr, val ) memtmp = sh4_read_long(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }
170 #define MEM_WRITE_BYTE( addr, val ) if( sh4_write_byte(addr, val) ) { return TRUE; }
171 #define MEM_WRITE_WORD( addr, val ) if( sh4_write_word(addr, val) ) { return TRUE; }
172 #define MEM_WRITE_LONG( addr, val ) if( sh4_write_long(addr, val) ) { return TRUE; }
174 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
176 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
177 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
179 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
180 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
181 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
182 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
183 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
185 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
186 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
187 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
189 static void sh4_write_float( uint32_t addr, int reg )
191 if( IS_FPU_DOUBLESIZE() ) {
193 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
194 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
196 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
197 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
200 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
204 static void sh4_read_float( uint32_t addr, int reg )
206 if( IS_FPU_DOUBLESIZE() ) {
208 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
209 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
211 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
212 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
215 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
219 gboolean sh4_execute_instruction( void )
226 int64_t memtmp; // temporary holder for memory reads
230 if( pc > 0xFFFFFF00 ) {
232 syscall_invoke( pc );
233 sh4r.in_delay_slot = 0;
234 pc = sh4r.pc = sh4r.pr;
235 sh4r.new_pc = sh4r.pc + 2;
239 /* Read instruction */
240 uint32_t pageaddr = pc >> 12;
241 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
242 ir = sh4_icache[(pc&0xFFF)>>1];
244 sh4_icache = (uint16_t *)mem_get_page(pc);
245 if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
246 /* If someone's actually been so daft as to try to execute out of an IO
247 * region, fallback on the full-blown memory read
250 MEM_READ_WORD(pc, ir);
252 sh4_icache_addr = pageaddr;
253 ir = sh4_icache[(pc&0xFFF)>>1];
257 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
258 AND #imm, R0 {: R0 &= imm; :}
259 AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
260 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
261 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
262 OR #imm, R0 {: R0 |= imm; :}
263 OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
265 MEM_READ_BYTE( sh4r.r[Rn], tmp );
266 sh4r.t = ( tmp == 0 ? 1 : 0 );
267 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
269 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
270 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
271 TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
272 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
273 XOR #imm, R0 {: R0 ^= imm; :}
274 XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
275 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
278 sh4r.t = sh4r.r[Rn] >> 31;
280 sh4r.r[Rn] |= sh4r.t;
283 sh4r.t = sh4r.r[Rn] & 0x00000001;
285 sh4r.r[Rn] |= (sh4r.t << 31);
288 tmp = sh4r.r[Rn] >> 31;
290 sh4r.r[Rn] |= sh4r.t;
294 tmp = sh4r.r[Rn] & 0x00000001;
296 sh4r.r[Rn] |= (sh4r.t << 31 );
301 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
302 else if( (tmp & 0x1F) == 0 )
303 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
305 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
309 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
310 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
311 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
314 sh4r.t = sh4r.r[Rn] >> 31;
318 sh4r.t = sh4r.r[Rn] & 0x00000001;
319 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
321 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
322 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
323 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
324 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
325 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
326 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
327 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
328 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
330 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
331 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
332 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
333 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
334 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
335 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
337 CLRT {: sh4r.t = 0; :}
338 SETT {: sh4r.t = 1; :}
339 CLRMAC {: sh4r.mac = 0; :}
340 LDTLB {: MMU_ldtlb(); :}
341 CLRS {: sh4r.s = 0; :}
342 SETS {: sh4r.s = 1; :}
343 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
348 if( (tmp & 0xFC000000) == 0xE0000000 ) {
349 sh4_flush_store_queue(tmp);
358 MEM_WRITE_LONG( tmp, R0 );
360 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
361 MOV.W Rm, @(R0, Rn) {:
362 CHECKWALIGN16( R0 + sh4r.r[Rn] );
363 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
365 MOV.L Rm, @(R0, Rn) {:
366 CHECKWALIGN32( R0 + sh4r.r[Rn] );
367 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
369 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
370 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
371 MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
373 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
374 MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
376 MOV.L Rm, @(disp, Rn) {:
377 tmp = sh4r.r[Rn] + disp;
378 CHECKWALIGN32( tmp );
379 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
381 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
382 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
383 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
384 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
385 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
386 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
387 MOV.L @(disp, Rm), Rn {:
388 tmp = sh4r.r[Rm] + disp;
389 CHECKRALIGN32( tmp );
390 MEM_READ_LONG( tmp, sh4r.r[Rn] );
392 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
393 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
394 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
395 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
396 MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
397 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
398 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
399 MOV.L @(disp, PC), Rn {:
401 tmp = (pc&0xFFFFFFFC) + disp + 4;
402 MEM_READ_LONG( tmp, sh4r.r[Rn] );
404 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
405 MOV.W R0, @(disp, GBR) {:
406 tmp = sh4r.gbr + disp;
407 CHECKWALIGN16( tmp );
408 MEM_WRITE_WORD( tmp, R0 );
410 MOV.L R0, @(disp, GBR) {:
411 tmp = sh4r.gbr + disp;
412 CHECKWALIGN32( tmp );
413 MEM_WRITE_LONG( tmp, R0 );
415 MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
416 MOV.W @(disp, GBR), R0 {:
417 tmp = sh4r.gbr + disp;
418 CHECKRALIGN16( tmp );
419 MEM_READ_WORD( tmp, R0 );
421 MOV.L @(disp, GBR), R0 {:
422 tmp = sh4r.gbr + disp;
423 CHECKRALIGN32( tmp );
424 MEM_READ_LONG( tmp, R0 );
426 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
427 MOV.W R0, @(disp, Rn) {:
428 tmp = sh4r.r[Rn] + disp;
429 CHECKWALIGN16( tmp );
430 MEM_WRITE_WORD( tmp, R0 );
432 MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
433 MOV.W @(disp, Rm), R0 {:
434 tmp = sh4r.r[Rm] + disp;
435 CHECKRALIGN16( tmp );
436 MEM_READ_WORD( tmp, R0 );
438 MOV.W @(disp, PC), Rn {:
441 MEM_READ_WORD( tmp, sh4r.r[Rn] );
443 MOVA @(disp, PC), R0 {:
445 R0 = (pc&0xFFFFFFFC) + disp + 4;
447 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
449 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
450 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
451 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
452 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
453 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
454 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
455 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
456 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
458 /* set T = 1 if any byte in RM & RN is the same */
459 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
460 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
461 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
464 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
465 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
468 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
469 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
472 tmp = sh4r.r[Rn] + sh4r.r[Rm];
473 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
476 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
478 sh4r.q = sh4r.r[Rn]>>31;
479 sh4r.m = sh4r.r[Rm]>>31;
480 sh4r.t = sh4r.q ^ sh4r.m;
483 /* This is derived from the sh4 manual with some simplifications */
484 uint32_t tmp0, tmp1, tmp2, dir;
486 dir = sh4r.q ^ sh4r.m;
487 sh4r.q = (sh4r.r[Rn] >> 31);
489 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
493 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
496 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
498 sh4r.q ^= sh4r.m ^ tmp1;
499 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
501 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
502 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
505 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
508 CHECKRALIGN16( sh4r.r[Rn] );
509 CHECKRALIGN16( sh4r.r[Rm] );
510 MEM_READ_WORD(sh4r.r[Rn], tmp);
511 int32_t stmp = SIGNEXT16(tmp);
513 MEM_READ_WORD(sh4r.r[Rm], tmp);
514 stmp = stmp * SIGNEXT16(tmp);
517 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
518 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
519 sh4r.mac = 0x000000017FFFFFFFLL;
520 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
521 sh4r.mac = 0x0000000180000000LL;
523 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
524 ((uint32_t)(sh4r.mac + stmp));
527 sh4r.mac += SIGNEXT32(stmp);
531 CHECKRALIGN32( sh4r.r[Rm] );
532 CHECKRALIGN32( sh4r.r[Rn] );
533 MEM_READ_LONG(sh4r.r[Rn], tmp);
534 int64_t tmpl = SIGNEXT32(tmp);
536 MEM_READ_LONG(sh4r.r[Rm], tmp);
537 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
540 /* 48-bit Saturation. Yuch */
541 if( tmpl < (int64_t)0xFFFF800000000000LL )
542 tmpl = 0xFFFF800000000000LL;
543 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
544 tmpl = 0x00007FFFFFFFFFFFLL;
548 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
549 (sh4r.r[Rm] * sh4r.r[Rn]); :}
551 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
552 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
555 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
556 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
559 tmp = 0 - sh4r.r[Rm];
560 sh4r.r[Rn] = tmp - sh4r.t;
561 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
563 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
564 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
567 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
568 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
573 CHECKDEST( pc + 4 + sh4r.r[Rn] );
574 sh4r.in_delay_slot = 1;
575 sh4r.pc = sh4r.new_pc;
576 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
581 CHECKDEST( pc + 4 + sh4r.r[Rn] );
582 sh4r.in_delay_slot = 1;
583 sh4r.pr = sh4r.pc + 4;
584 sh4r.pc = sh4r.new_pc;
585 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
586 TRACE_CALL( pc, sh4r.new_pc );
592 CHECKDEST( sh4r.pc + disp + 4 )
594 sh4r.new_pc = sh4r.pc + 2;
601 CHECKDEST( sh4r.pc + disp + 4 )
603 sh4r.new_pc = sh4r.pc + 2;
610 CHECKDEST( sh4r.pc + disp + 4 )
611 sh4r.in_delay_slot = 1;
612 sh4r.pc = sh4r.new_pc;
613 sh4r.new_pc = pc + disp + 4;
614 sh4r.in_delay_slot = 1;
621 CHECKDEST( sh4r.pc + disp + 4 )
622 sh4r.in_delay_slot = 1;
623 sh4r.pc = sh4r.new_pc;
624 sh4r.new_pc = pc + disp + 4;
630 CHECKDEST( sh4r.pc + disp + 4 );
631 sh4r.in_delay_slot = 1;
632 sh4r.pc = sh4r.new_pc;
633 sh4r.new_pc = pc + 4 + disp;
637 CHECKDEST( sh4r.pc + disp + 4 );
639 sh4r.in_delay_slot = 1;
641 sh4r.pc = sh4r.new_pc;
642 sh4r.new_pc = pc + 4 + disp;
643 TRACE_CALL( pc, sh4r.new_pc );
648 MMIO_WRITE( MMU, TRA, imm<<2 );
650 sh4_raise_exception( EXC_TRAP );
654 CHECKDEST( sh4r.pr );
655 sh4r.in_delay_slot = 1;
656 sh4r.pc = sh4r.new_pc;
657 sh4r.new_pc = sh4r.pr;
658 TRACE_RETURN( pc, sh4r.new_pc );
662 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
663 sh4r.sh4_state = SH4_STATE_STANDBY;
665 sh4r.sh4_state = SH4_STATE_SLEEP;
667 return FALSE; /* Halt CPU */
671 CHECKDEST( sh4r.spc );
673 sh4r.in_delay_slot = 1;
674 sh4r.pc = sh4r.new_pc;
675 sh4r.new_pc = sh4r.spc;
676 sh4_write_sr( sh4r.ssr );
680 CHECKDEST( sh4r.r[Rn] );
682 sh4r.in_delay_slot = 1;
683 sh4r.pc = sh4r.new_pc;
684 sh4r.new_pc = sh4r.r[Rn];
688 CHECKDEST( sh4r.r[Rn] );
690 sh4r.in_delay_slot = 1;
691 sh4r.pc = sh4r.new_pc;
692 sh4r.new_pc = sh4r.r[Rn];
694 TRACE_CALL( pc, sh4r.new_pc );
697 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
700 CHECKWALIGN32( sh4r.r[Rn] );
701 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
706 CHECKWALIGN32( sh4r.r[Rn] );
707 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
710 CHECKRALIGN32( sh4r.r[Rm] );
711 MEM_READ_LONG(sh4r.r[Rm], tmp);
712 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
713 (((uint64_t)tmp)<<32);
719 CHECKWALIGN32( sh4r.r[Rm] );
720 MEM_READ_LONG(sh4r.r[Rm], tmp);
725 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
726 (((uint64_t)sh4r.r[Rm])<<32);
731 sh4_write_sr( sh4r.r[Rm] );
735 sh4r.sgr = sh4r.r[Rm];
739 CHECKRALIGN32( sh4r.r[Rm] );
740 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
743 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
746 CHECKWALIGN32( sh4r.r[Rn] );
747 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
751 CHECKWALIGN32( sh4r.r[Rn] );
752 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
755 CHECKRALIGN32( sh4r.r[Rm] );
756 MEM_READ_LONG(sh4r.r[Rm], tmp);
757 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
758 (uint64_t)((uint32_t)tmp);
762 CHECKRALIGN32( sh4r.r[Rm] );
763 MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
767 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
768 (uint64_t)((uint32_t)(sh4r.r[Rm]));
770 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
771 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
774 CHECKWALIGN32( sh4r.r[Rn] );
775 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
780 CHECKWALIGN32( sh4r.r[Rn] );
781 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
784 CHECKRALIGN32( sh4r.r[Rm] );
785 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
790 CHECKRALIGN32( sh4r.r[Rm] );
791 MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
794 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
797 sh4r.vbr = sh4r.r[Rm];
801 sh4r.r[Rn] = sh4r.sgr;
806 CHECKWALIGN32( sh4r.r[Rn] );
807 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
812 CHECKWALIGN32( sh4r.r[Rn] );
813 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
817 CHECKRALIGN32( sh4r.r[Rm] );
818 MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
823 sh4r.ssr = sh4r.r[Rm];
828 CHECKWALIGN32( sh4r.r[Rn] );
829 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
833 CHECKRALIGN32( sh4r.r[Rm] );
834 MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
839 sh4r.spc = sh4r.r[Rm];
841 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
844 CHECKWALIGN32( sh4r.r[Rn] );
845 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
848 CHECKRALIGN32( sh4r.r[Rm] );
849 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
852 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
853 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
856 CHECKWALIGN32( sh4r.r[Rn] );
857 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
860 CHECKRALIGN32( sh4r.r[Rm] );
861 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
863 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
866 sh4r.fpscr = sh4r.r[Rm];
867 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
869 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
873 CHECKWALIGN32( sh4r.r[Rn] );
874 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
878 CHECKRALIGN32( sh4r.r[Rm] );
879 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
884 sh4r.dbr = sh4r.r[Rm];
886 STC.L Rm_BANK, @-Rn {:
889 CHECKWALIGN32( sh4r.r[Rn] );
890 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
892 LDC.L @Rm+, Rn_BANK {:
894 CHECKRALIGN32( sh4r.r[Rm] );
895 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
900 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
904 sh4r.r[Rn] = sh4_read_sr();
908 sh4r.r[Rn] = sh4r.gbr;
912 sh4r.r[Rn] = sh4r.vbr;
916 sh4r.r[Rn] = sh4r.ssr;
920 sh4r.r[Rn] = sh4r.spc;
924 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
929 if( IS_FPU_DOUBLEPREC() ) {
937 if( IS_FPU_DOUBLEPREC() ) {
946 if( IS_FPU_DOUBLEPREC() ) {
955 if( IS_FPU_DOUBLEPREC() ) {
964 if( IS_FPU_DOUBLEPREC() ) {
965 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
967 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
973 if( IS_FPU_DOUBLEPREC() ) {
974 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
976 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
980 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
981 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
982 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
983 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
984 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
985 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
987 if( IS_FPU_DOUBLESIZE() )
992 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
993 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
996 if( IS_FPU_DOUBLEPREC() ) {
997 if( FRn&1 ) { // No, really...
998 dtmp = (double)FPULi;
999 FR(FRn) = *(((float *)&dtmp)+1);
1001 DRF(FRn>>1) = (double)FPULi;
1004 FR(FRn) = (float)FPULi;
1009 if( IS_FPU_DOUBLEPREC() ) {
1012 *(((float *)&dtmp)+1) = FR(FRm);
1016 if( dtmp >= MAX_INTF )
1018 else if( dtmp <= MIN_INTF )
1021 FPULi = (int32_t)dtmp;
1024 if( ftmp >= MAX_INTF )
1026 else if( ftmp <= MIN_INTF )
1029 FPULi = (int32_t)ftmp;
1034 if( IS_FPU_DOUBLEPREC() ) {
1042 if( IS_FPU_DOUBLEPREC() ) {
1043 DR(FRn) = fabs(DR(FRn));
1045 FR(FRn) = fabsf(FR(FRn));
1050 if( IS_FPU_DOUBLEPREC() ) {
1051 DR(FRn) = sqrt(DR(FRn));
1053 FR(FRn) = sqrtf(FR(FRn));
1058 if( IS_FPU_DOUBLEPREC() ) {
1066 if( IS_FPU_DOUBLEPREC() ) {
1072 FMAC FR0, FRm, FRn {:
1074 if( IS_FPU_DOUBLEPREC() ) {
1075 DR(FRn) += DR(FRm)*DR(0);
1077 FR(FRn) += FR(FRm)*FR(0);
1082 sh4r.fpscr ^= FPSCR_FR;
1083 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1085 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1088 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1089 DR(FRn) = (double)FPULf;
1094 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1095 FPULf = (float)DR(FRm);
1101 if( !IS_FPU_DOUBLEPREC() ) {
1102 FR(FRn) = 1.0/sqrtf(FR(FRn));
1107 if( !IS_FPU_DOUBLEPREC() ) {
1110 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1111 FR(tmp+1)*FR(tmp2+1) +
1112 FR(tmp+2)*FR(tmp2+2) +
1113 FR(tmp+3)*FR(tmp2+3);
1118 if( !IS_FPU_DOUBLEPREC() ) {
1119 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
1121 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1122 FR(FRn) = sinf(angle);
1123 FR((FRn)+1) = cosf(angle);
1129 if( !IS_FPU_DOUBLEPREC() ) {
1130 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
1133 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
1134 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1135 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
1136 xf[9]*fv[2] + xf[13]*fv[3];
1137 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
1138 xf[8]*fv[2] + xf[12]*fv[3];
1139 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
1140 xf[11]*fv[2] + xf[15]*fv[3];
1141 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
1142 xf[10]*fv[2] + xf[14]*fv[3];
1150 sh4r.pc = sh4r.new_pc;
1152 sh4r.in_delay_slot = 0;
.