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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 561:533f6b478071
prev559:06714bc64271
next569:a1c49e1e8776
author nkeynes
date Tue Jan 01 05:08:38 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Enable Id keyword on all source files
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "sh4/xltcache.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4trans.h"
    31 #include "sh4/sh4mmio.h"
    32 #include "sh4/x86op.h"
    33 #include "clock.h"
    35 #define DEFAULT_BACKPATCH_SIZE 4096
    37 struct backpatch_record {
    38     uint32_t *fixup_addr;
    39     uint32_t fixup_icount;
    40     uint32_t exc_code;
    41 };
    43 /** 
    44  * Struct to manage internal translation state. This state is not saved -
    45  * it is only valid between calls to sh4_translate_begin_block() and
    46  * sh4_translate_end_block()
    47  */
    48 struct sh4_x86_state {
    49     gboolean in_delay_slot;
    50     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    51     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    52     gboolean branch_taken; /* true if we branched unconditionally */
    53     uint32_t block_start_pc;
    54     uint32_t stack_posn;   /* Trace stack height for alignment purposes */
    55     int tstate;
    57     /* Allocated memory for the (block-wide) back-patch list */
    58     struct backpatch_record *backpatch_list;
    59     uint32_t backpatch_posn;
    60     uint32_t backpatch_size;
    61 };
    63 #define TSTATE_NONE -1
    64 #define TSTATE_O    0
    65 #define TSTATE_C    2
    66 #define TSTATE_E    4
    67 #define TSTATE_NE   5
    68 #define TSTATE_G    0xF
    69 #define TSTATE_GE   0xD
    70 #define TSTATE_A    7
    71 #define TSTATE_AE   3
    73 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
    74 #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    75 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    76     OP(0x70+sh4_x86.tstate); OP(rel8); \
    77     MARK_JMP(rel8,label)
    78 /** Branch if T is clear (either in the current cflags or in sh4r.t) */
    79 #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    80 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    81     OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
    82     MARK_JMP(rel8, label)
    84 static struct sh4_x86_state sh4_x86;
    86 static uint32_t max_int = 0x7FFFFFFF;
    87 static uint32_t min_int = 0x80000000;
    88 static uint32_t save_fcw; /* save value for fpu control word */
    89 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
    91 void sh4_x86_init()
    92 {
    93     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
    94     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
    95 }
    98 static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
    99 {
   100     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
   101 	sh4_x86.backpatch_size <<= 1;
   102 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
   103 					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
   104 	assert( sh4_x86.backpatch_list != NULL );
   105     }
   106     if( sh4_x86.in_delay_slot ) {
   107 	fixup_pc -= 2;
   108     }
   109     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
   110     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
   111     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
   112     sh4_x86.backpatch_posn++;
   113 }
   115 /**
   116  * Emit an instruction to load an SH4 reg into a real register
   117  */
   118 static inline void load_reg( int x86reg, int sh4reg ) 
   119 {
   120     /* mov [bp+n], reg */
   121     OP(0x8B);
   122     OP(0x45 + (x86reg<<3));
   123     OP(REG_OFFSET(r[sh4reg]));
   124 }
   126 static inline void load_reg16s( int x86reg, int sh4reg )
   127 {
   128     OP(0x0F);
   129     OP(0xBF);
   130     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   131 }
   133 static inline void load_reg16u( int x86reg, int sh4reg )
   134 {
   135     OP(0x0F);
   136     OP(0xB7);
   137     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   139 }
   141 #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
   142 #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
   143 /**
   144  * Emit an instruction to load an immediate value into a register
   145  */
   146 static inline void load_imm32( int x86reg, uint32_t value ) {
   147     /* mov #value, reg */
   148     OP(0xB8 + x86reg);
   149     OP32(value);
   150 }
   152 /**
   153  * Load an immediate 64-bit quantity (note: x86-64 only)
   154  */
   155 static inline void load_imm64( int x86reg, uint32_t value ) {
   156     /* mov #value, reg */
   157     REXW();
   158     OP(0xB8 + x86reg);
   159     OP64(value);
   160 }
   163 /**
   164  * Emit an instruction to store an SH4 reg (RN)
   165  */
   166 void static inline store_reg( int x86reg, int sh4reg ) {
   167     /* mov reg, [bp+n] */
   168     OP(0x89);
   169     OP(0x45 + (x86reg<<3));
   170     OP(REG_OFFSET(r[sh4reg]));
   171 }
   173 #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
   175 /**
   176  * Load an FR register (single-precision floating point) into an integer x86
   177  * register (eg for register-to-register moves)
   178  */
   179 void static inline load_fr( int bankreg, int x86reg, int frm )
   180 {
   181     OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
   182 }
   184 /**
   185  * Store an FR register (single-precision floating point) into an integer x86
   186  * register (eg for register-to-register moves)
   187  */
   188 void static inline store_fr( int bankreg, int x86reg, int frn )
   189 {
   190     OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
   191 }
   194 /**
   195  * Load a pointer to the back fp back into the specified x86 register. The
   196  * bankreg must have been previously loaded with FPSCR.
   197  * NB: 12 bytes
   198  */
   199 static inline void load_xf_bank( int bankreg )
   200 {
   201     NOT_r32( bankreg );
   202     SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
   203     AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
   204     OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
   205 }
   207 /**
   208  * Update the fr_bank pointer based on the current fpscr value.
   209  */
   210 static inline void update_fr_bank( int fpscrreg )
   211 {
   212     SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
   213     AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
   214     OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
   215     store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
   216 }
   217 /**
   218  * Push FPUL (as a 32-bit float) onto the FPU stack
   219  */
   220 static inline void push_fpul( )
   221 {
   222     OP(0xD9); OP(0x45); OP(R_FPUL);
   223 }
   225 /**
   226  * Pop FPUL (as a 32-bit float) from the FPU stack
   227  */
   228 static inline void pop_fpul( )
   229 {
   230     OP(0xD9); OP(0x5D); OP(R_FPUL);
   231 }
   233 /**
   234  * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
   235  * with the location of the current fp bank.
   236  */
   237 static inline void push_fr( int bankreg, int frm ) 
   238 {
   239     OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
   240 }
   242 /**
   243  * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
   244  * with bankreg previously loaded with the location of the current fp bank.
   245  */
   246 static inline void pop_fr( int bankreg, int frm )
   247 {
   248     OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
   249 }
   251 /**
   252  * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
   253  * with the location of the current fp bank.
   254  */
   255 static inline void push_dr( int bankreg, int frm )
   256 {
   257     OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
   258 }
   260 static inline void pop_dr( int bankreg, int frm )
   261 {
   262     OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
   263 }
   265 /* Exception checks - Note that all exception checks will clobber EAX */
   267 #define check_priv( ) \
   268     if( !sh4_x86.priv_checked ) { \
   269 	sh4_x86.priv_checked = TRUE;\
   270 	load_spreg( R_EAX, R_SR );\
   271 	AND_imm32_r32( SR_MD, R_EAX );\
   272 	if( sh4_x86.in_delay_slot ) {\
   273 	    JE_exc( EXC_SLOT_ILLEGAL );\
   274 	} else {\
   275 	    JE_exc( EXC_ILLEGAL );\
   276 	}\
   277     }\
   279 #define check_fpuen( ) \
   280     if( !sh4_x86.fpuen_checked ) {\
   281 	sh4_x86.fpuen_checked = TRUE;\
   282 	load_spreg( R_EAX, R_SR );\
   283 	AND_imm32_r32( SR_FD, R_EAX );\
   284 	if( sh4_x86.in_delay_slot ) {\
   285 	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
   286 	} else {\
   287 	    JNE_exc(EXC_FPU_DISABLED);\
   288 	}\
   289     }
   291 #define check_ralign16( x86reg ) \
   292     TEST_imm32_r32( 0x00000001, x86reg ); \
   293     JNE_exc(EXC_DATA_ADDR_READ)
   295 #define check_walign16( x86reg ) \
   296     TEST_imm32_r32( 0x00000001, x86reg ); \
   297     JNE_exc(EXC_DATA_ADDR_WRITE);
   299 #define check_ralign32( x86reg ) \
   300     TEST_imm32_r32( 0x00000003, x86reg ); \
   301     JNE_exc(EXC_DATA_ADDR_READ)
   303 #define check_walign32( x86reg ) \
   304     TEST_imm32_r32( 0x00000003, x86reg ); \
   305     JNE_exc(EXC_DATA_ADDR_WRITE);
   307 #define UNDEF()
   308 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   309 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
   310 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
   311 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); TEST_r32_r32( R_EDX, R_EDX ); JNE_exc(-1); MEM_RESULT(value_reg) 
   312 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
   313 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
   314 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg); TEST_r32_r32( R_EAX, R_EAX ); JNE_exc(-1);
   316 #define MEM_READ_SIZE  (CALL_FUNC1_SIZE+8)
   317 #define MEM_WRITE_SIZE (CALL_FUNC2_SIZE+8)
   319 #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
   321 extern uint16_t *sh4_icache;
   322 extern uint32_t sh4_icache_addr;
   324 /****** Import appropriate calling conventions ******/
   325 #if SH4_TRANSLATOR == TARGET_X86_64
   326 #include "sh4/ia64abi.h"
   327 #else /* SH4_TRANSLATOR == TARGET_X86 */
   328 #ifdef APPLE_BUILD
   329 #include "sh4/ia32mac.h"
   330 #else
   331 #include "sh4/ia32abi.h"
   332 #endif
   333 #endif
   336 /**
   337  * Translate a single instruction. Delayed branches are handled specially
   338  * by translating both branch and delayed instruction as a single unit (as
   339  * 
   340  *
   341  * @return true if the instruction marks the end of a basic block
   342  * (eg a branch or 
   343  */
   344 uint32_t sh4_translate_instruction( sh4addr_t pc )
   345 {
   346     uint32_t ir;
   347     /* Read instruction */
   348     uint32_t pageaddr = pc >> 12;
   349     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   350 	ir = sh4_icache[(pc&0xFFF)>>1];
   351     } else {
   352 	uint64_t phys = mmu_vma_to_phys_exec(pc);
   353 	sh4_icache = (uint16_t *)mem_get_page((uint32_t)phys);
   354 	if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
   355 	    /* If someone's actually been so daft as to try to execute out of an IO
   356 	     * region, fallback on the full-blown memory read
   357 	     */
   358 	    sh4_icache = NULL;
   359 	    ir = sh4_read_word(pc);
   360 	} else {
   361 	    sh4_icache_addr = pageaddr;
   362 	    ir = sh4_icache[(pc&0xFFF)>>1];
   363 	}
   364     }
   366         switch( (ir&0xF000) >> 12 ) {
   367             case 0x0:
   368                 switch( ir&0xF ) {
   369                     case 0x2:
   370                         switch( (ir&0x80) >> 7 ) {
   371                             case 0x0:
   372                                 switch( (ir&0x70) >> 4 ) {
   373                                     case 0x0:
   374                                         { /* STC SR, Rn */
   375                                         uint32_t Rn = ((ir>>8)&0xF); 
   376                                         check_priv();
   377                                         call_func0(sh4_read_sr);
   378                                         store_reg( R_EAX, Rn );
   379                                         sh4_x86.tstate = TSTATE_NONE;
   380                                         }
   381                                         break;
   382                                     case 0x1:
   383                                         { /* STC GBR, Rn */
   384                                         uint32_t Rn = ((ir>>8)&0xF); 
   385                                         load_spreg( R_EAX, R_GBR );
   386                                         store_reg( R_EAX, Rn );
   387                                         }
   388                                         break;
   389                                     case 0x2:
   390                                         { /* STC VBR, Rn */
   391                                         uint32_t Rn = ((ir>>8)&0xF); 
   392                                         check_priv();
   393                                         load_spreg( R_EAX, R_VBR );
   394                                         store_reg( R_EAX, Rn );
   395                                         sh4_x86.tstate = TSTATE_NONE;
   396                                         }
   397                                         break;
   398                                     case 0x3:
   399                                         { /* STC SSR, Rn */
   400                                         uint32_t Rn = ((ir>>8)&0xF); 
   401                                         check_priv();
   402                                         load_spreg( R_EAX, R_SSR );
   403                                         store_reg( R_EAX, Rn );
   404                                         sh4_x86.tstate = TSTATE_NONE;
   405                                         }
   406                                         break;
   407                                     case 0x4:
   408                                         { /* STC SPC, Rn */
   409                                         uint32_t Rn = ((ir>>8)&0xF); 
   410                                         check_priv();
   411                                         load_spreg( R_EAX, R_SPC );
   412                                         store_reg( R_EAX, Rn );
   413                                         sh4_x86.tstate = TSTATE_NONE;
   414                                         }
   415                                         break;
   416                                     default:
   417                                         UNDEF();
   418                                         break;
   419                                 }
   420                                 break;
   421                             case 0x1:
   422                                 { /* STC Rm_BANK, Rn */
   423                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   424                                 check_priv();
   425                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
   426                                 store_reg( R_EAX, Rn );
   427                                 sh4_x86.tstate = TSTATE_NONE;
   428                                 }
   429                                 break;
   430                         }
   431                         break;
   432                     case 0x3:
   433                         switch( (ir&0xF0) >> 4 ) {
   434                             case 0x0:
   435                                 { /* BSRF Rn */
   436                                 uint32_t Rn = ((ir>>8)&0xF); 
   437                                 if( sh4_x86.in_delay_slot ) {
   438                             	SLOTILLEGAL();
   439                                 } else {
   440                             	load_imm32( R_ECX, pc + 4 );
   441                             	store_spreg( R_ECX, R_PR );
   442                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
   443                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   444                             	sh4_x86.in_delay_slot = TRUE;
   445                             	sh4_x86.tstate = TSTATE_NONE;
   446                             	sh4_translate_instruction( pc + 2 );
   447                             	exit_block_pcset(pc+2);
   448                             	sh4_x86.branch_taken = TRUE;
   449                             	return 4;
   450                                 }
   451                                 }
   452                                 break;
   453                             case 0x2:
   454                                 { /* BRAF Rn */
   455                                 uint32_t Rn = ((ir>>8)&0xF); 
   456                                 if( sh4_x86.in_delay_slot ) {
   457                             	SLOTILLEGAL();
   458                                 } else {
   459                             	load_reg( R_EAX, Rn );
   460                             	ADD_imm32_r32( pc + 4, R_EAX );
   461                             	store_spreg( R_EAX, REG_OFFSET(pc) );
   462                             	sh4_x86.in_delay_slot = TRUE;
   463                             	sh4_x86.tstate = TSTATE_NONE;
   464                             	sh4_translate_instruction( pc + 2 );
   465                             	exit_block_pcset(pc+2);
   466                             	sh4_x86.branch_taken = TRUE;
   467                             	return 4;
   468                                 }
   469                                 }
   470                                 break;
   471                             case 0x8:
   472                                 { /* PREF @Rn */
   473                                 uint32_t Rn = ((ir>>8)&0xF); 
   474                                 load_reg( R_EAX, Rn );
   475                                 MOV_r32_r32( R_EAX, R_ECX );
   476                                 AND_imm32_r32( 0xFC000000, R_EAX );
   477                                 CMP_imm32_r32( 0xE0000000, R_EAX );
   478                                 JNE_rel8(CALL_FUNC1_SIZE, end);
   479                                 call_func1( sh4_flush_store_queue, R_ECX );
   480                                 JMP_TARGET(end);
   481                                 sh4_x86.tstate = TSTATE_NONE;
   482                                 }
   483                                 break;
   484                             case 0x9:
   485                                 { /* OCBI @Rn */
   486                                 uint32_t Rn = ((ir>>8)&0xF); 
   487                                 }
   488                                 break;
   489                             case 0xA:
   490                                 { /* OCBP @Rn */
   491                                 uint32_t Rn = ((ir>>8)&0xF); 
   492                                 }
   493                                 break;
   494                             case 0xB:
   495                                 { /* OCBWB @Rn */
   496                                 uint32_t Rn = ((ir>>8)&0xF); 
   497                                 }
   498                                 break;
   499                             case 0xC:
   500                                 { /* MOVCA.L R0, @Rn */
   501                                 uint32_t Rn = ((ir>>8)&0xF); 
   502                                 load_reg( R_EAX, 0 );
   503                                 load_reg( R_ECX, Rn );
   504                                 check_walign32( R_ECX );
   505                                 MEM_WRITE_LONG( R_ECX, R_EAX );
   506                                 sh4_x86.tstate = TSTATE_NONE;
   507                                 }
   508                                 break;
   509                             default:
   510                                 UNDEF();
   511                                 break;
   512                         }
   513                         break;
   514                     case 0x4:
   515                         { /* MOV.B Rm, @(R0, Rn) */
   516                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   517                         load_reg( R_EAX, 0 );
   518                         load_reg( R_ECX, Rn );
   519                         ADD_r32_r32( R_EAX, R_ECX );
   520                         load_reg( R_EAX, Rm );
   521                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   522                         sh4_x86.tstate = TSTATE_NONE;
   523                         }
   524                         break;
   525                     case 0x5:
   526                         { /* MOV.W Rm, @(R0, Rn) */
   527                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   528                         load_reg( R_EAX, 0 );
   529                         load_reg( R_ECX, Rn );
   530                         ADD_r32_r32( R_EAX, R_ECX );
   531                         check_walign16( R_ECX );
   532                         load_reg( R_EAX, Rm );
   533                         MEM_WRITE_WORD( R_ECX, R_EAX );
   534                         sh4_x86.tstate = TSTATE_NONE;
   535                         }
   536                         break;
   537                     case 0x6:
   538                         { /* MOV.L Rm, @(R0, Rn) */
   539                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   540                         load_reg( R_EAX, 0 );
   541                         load_reg( R_ECX, Rn );
   542                         ADD_r32_r32( R_EAX, R_ECX );
   543                         check_walign32( R_ECX );
   544                         load_reg( R_EAX, Rm );
   545                         MEM_WRITE_LONG( R_ECX, R_EAX );
   546                         sh4_x86.tstate = TSTATE_NONE;
   547                         }
   548                         break;
   549                     case 0x7:
   550                         { /* MUL.L Rm, Rn */
   551                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   552                         load_reg( R_EAX, Rm );
   553                         load_reg( R_ECX, Rn );
   554                         MUL_r32( R_ECX );
   555                         store_spreg( R_EAX, R_MACL );
   556                         sh4_x86.tstate = TSTATE_NONE;
   557                         }
   558                         break;
   559                     case 0x8:
   560                         switch( (ir&0xFF0) >> 4 ) {
   561                             case 0x0:
   562                                 { /* CLRT */
   563                                 CLC();
   564                                 SETC_t();
   565                                 sh4_x86.tstate = TSTATE_C;
   566                                 }
   567                                 break;
   568                             case 0x1:
   569                                 { /* SETT */
   570                                 STC();
   571                                 SETC_t();
   572                                 sh4_x86.tstate = TSTATE_C;
   573                                 }
   574                                 break;
   575                             case 0x2:
   576                                 { /* CLRMAC */
   577                                 XOR_r32_r32(R_EAX, R_EAX);
   578                                 store_spreg( R_EAX, R_MACL );
   579                                 store_spreg( R_EAX, R_MACH );
   580                                 sh4_x86.tstate = TSTATE_NONE;
   581                                 }
   582                                 break;
   583                             case 0x3:
   584                                 { /* LDTLB */
   585                                 call_func0( MMU_ldtlb );
   586                                 }
   587                                 break;
   588                             case 0x4:
   589                                 { /* CLRS */
   590                                 CLC();
   591                                 SETC_sh4r(R_S);
   592                                 sh4_x86.tstate = TSTATE_C;
   593                                 }
   594                                 break;
   595                             case 0x5:
   596                                 { /* SETS */
   597                                 STC();
   598                                 SETC_sh4r(R_S);
   599                                 sh4_x86.tstate = TSTATE_C;
   600                                 }
   601                                 break;
   602                             default:
   603                                 UNDEF();
   604                                 break;
   605                         }
   606                         break;
   607                     case 0x9:
   608                         switch( (ir&0xF0) >> 4 ) {
   609                             case 0x0:
   610                                 { /* NOP */
   611                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   612                                 }
   613                                 break;
   614                             case 0x1:
   615                                 { /* DIV0U */
   616                                 XOR_r32_r32( R_EAX, R_EAX );
   617                                 store_spreg( R_EAX, R_Q );
   618                                 store_spreg( R_EAX, R_M );
   619                                 store_spreg( R_EAX, R_T );
   620                                 sh4_x86.tstate = TSTATE_C; // works for DIV1
   621                                 }
   622                                 break;
   623                             case 0x2:
   624                                 { /* MOVT Rn */
   625                                 uint32_t Rn = ((ir>>8)&0xF); 
   626                                 load_spreg( R_EAX, R_T );
   627                                 store_reg( R_EAX, Rn );
   628                                 }
   629                                 break;
   630                             default:
   631                                 UNDEF();
   632                                 break;
   633                         }
   634                         break;
   635                     case 0xA:
   636                         switch( (ir&0xF0) >> 4 ) {
   637                             case 0x0:
   638                                 { /* STS MACH, Rn */
   639                                 uint32_t Rn = ((ir>>8)&0xF); 
   640                                 load_spreg( R_EAX, R_MACH );
   641                                 store_reg( R_EAX, Rn );
   642                                 }
   643                                 break;
   644                             case 0x1:
   645                                 { /* STS MACL, Rn */
   646                                 uint32_t Rn = ((ir>>8)&0xF); 
   647                                 load_spreg( R_EAX, R_MACL );
   648                                 store_reg( R_EAX, Rn );
   649                                 }
   650                                 break;
   651                             case 0x2:
   652                                 { /* STS PR, Rn */
   653                                 uint32_t Rn = ((ir>>8)&0xF); 
   654                                 load_spreg( R_EAX, R_PR );
   655                                 store_reg( R_EAX, Rn );
   656                                 }
   657                                 break;
   658                             case 0x3:
   659                                 { /* STC SGR, Rn */
   660                                 uint32_t Rn = ((ir>>8)&0xF); 
   661                                 check_priv();
   662                                 load_spreg( R_EAX, R_SGR );
   663                                 store_reg( R_EAX, Rn );
   664                                 sh4_x86.tstate = TSTATE_NONE;
   665                                 }
   666                                 break;
   667                             case 0x5:
   668                                 { /* STS FPUL, Rn */
   669                                 uint32_t Rn = ((ir>>8)&0xF); 
   670                                 load_spreg( R_EAX, R_FPUL );
   671                                 store_reg( R_EAX, Rn );
   672                                 }
   673                                 break;
   674                             case 0x6:
   675                                 { /* STS FPSCR, Rn */
   676                                 uint32_t Rn = ((ir>>8)&0xF); 
   677                                 load_spreg( R_EAX, R_FPSCR );
   678                                 store_reg( R_EAX, Rn );
   679                                 }
   680                                 break;
   681                             case 0xF:
   682                                 { /* STC DBR, Rn */
   683                                 uint32_t Rn = ((ir>>8)&0xF); 
   684                                 check_priv();
   685                                 load_spreg( R_EAX, R_DBR );
   686                                 store_reg( R_EAX, Rn );
   687                                 sh4_x86.tstate = TSTATE_NONE;
   688                                 }
   689                                 break;
   690                             default:
   691                                 UNDEF();
   692                                 break;
   693                         }
   694                         break;
   695                     case 0xB:
   696                         switch( (ir&0xFF0) >> 4 ) {
   697                             case 0x0:
   698                                 { /* RTS */
   699                                 if( sh4_x86.in_delay_slot ) {
   700                             	SLOTILLEGAL();
   701                                 } else {
   702                             	load_spreg( R_ECX, R_PR );
   703                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   704                             	sh4_x86.in_delay_slot = TRUE;
   705                             	sh4_translate_instruction(pc+2);
   706                             	exit_block_pcset(pc+2);
   707                             	sh4_x86.branch_taken = TRUE;
   708                             	return 4;
   709                                 }
   710                                 }
   711                                 break;
   712                             case 0x1:
   713                                 { /* SLEEP */
   714                                 check_priv();
   715                                 call_func0( sh4_sleep );
   716                                 sh4_x86.tstate = TSTATE_NONE;
   717                                 sh4_x86.in_delay_slot = FALSE;
   718                                 return 2;
   719                                 }
   720                                 break;
   721                             case 0x2:
   722                                 { /* RTE */
   723                                 if( sh4_x86.in_delay_slot ) {
   724                             	SLOTILLEGAL();
   725                                 } else {
   726                             	check_priv();
   727                             	load_spreg( R_ECX, R_SPC );
   728                             	store_spreg( R_ECX, REG_OFFSET(pc) );
   729                             	load_spreg( R_EAX, R_SSR );
   730                             	call_func1( sh4_write_sr, R_EAX );
   731                             	sh4_x86.in_delay_slot = TRUE;
   732                             	sh4_x86.priv_checked = FALSE;
   733                             	sh4_x86.fpuen_checked = FALSE;
   734                             	sh4_x86.tstate = TSTATE_NONE;
   735                             	sh4_translate_instruction(pc+2);
   736                             	exit_block_pcset(pc+2);
   737                             	sh4_x86.branch_taken = TRUE;
   738                             	return 4;
   739                                 }
   740                                 }
   741                                 break;
   742                             default:
   743                                 UNDEF();
   744                                 break;
   745                         }
   746                         break;
   747                     case 0xC:
   748                         { /* MOV.B @(R0, Rm), Rn */
   749                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   750                         load_reg( R_EAX, 0 );
   751                         load_reg( R_ECX, Rm );
   752                         ADD_r32_r32( R_EAX, R_ECX );
   753                         MEM_READ_BYTE( R_ECX, R_EAX );
   754                         store_reg( R_EAX, Rn );
   755                         sh4_x86.tstate = TSTATE_NONE;
   756                         }
   757                         break;
   758                     case 0xD:
   759                         { /* MOV.W @(R0, Rm), Rn */
   760                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   761                         load_reg( R_EAX, 0 );
   762                         load_reg( R_ECX, Rm );
   763                         ADD_r32_r32( R_EAX, R_ECX );
   764                         check_ralign16( R_ECX );
   765                         MEM_READ_WORD( R_ECX, R_EAX );
   766                         store_reg( R_EAX, Rn );
   767                         sh4_x86.tstate = TSTATE_NONE;
   768                         }
   769                         break;
   770                     case 0xE:
   771                         { /* MOV.L @(R0, Rm), Rn */
   772                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   773                         load_reg( R_EAX, 0 );
   774                         load_reg( R_ECX, Rm );
   775                         ADD_r32_r32( R_EAX, R_ECX );
   776                         check_ralign32( R_ECX );
   777                         MEM_READ_LONG( R_ECX, R_EAX );
   778                         store_reg( R_EAX, Rn );
   779                         sh4_x86.tstate = TSTATE_NONE;
   780                         }
   781                         break;
   782                     case 0xF:
   783                         { /* MAC.L @Rm+, @Rn+ */
   784                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   785                         load_reg( R_ECX, Rm );
   786                         check_ralign32( R_ECX );
   787                         load_reg( R_ECX, Rn );
   788                         check_ralign32( R_ECX );
   789                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
   790                         MEM_READ_LONG( R_ECX, R_EAX );
   791                         PUSH_realigned_r32( R_EAX );
   792                         load_reg( R_ECX, Rm );
   793                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
   794                         MEM_READ_LONG( R_ECX, R_EAX );
   795                         POP_realigned_r32( R_ECX );
   796                         IMUL_r32( R_ECX );
   797                         ADD_r32_sh4r( R_EAX, R_MACL );
   798                         ADC_r32_sh4r( R_EDX, R_MACH );
   800                         load_spreg( R_ECX, R_S );
   801                         TEST_r32_r32(R_ECX, R_ECX);
   802                         JE_rel8( CALL_FUNC0_SIZE, nosat );
   803                         call_func0( signsat48 );
   804                         JMP_TARGET( nosat );
   805                         sh4_x86.tstate = TSTATE_NONE;
   806                         }
   807                         break;
   808                     default:
   809                         UNDEF();
   810                         break;
   811                 }
   812                 break;
   813             case 0x1:
   814                 { /* MOV.L Rm, @(disp, Rn) */
   815                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   816                 load_reg( R_ECX, Rn );
   817                 load_reg( R_EAX, Rm );
   818                 ADD_imm32_r32( disp, R_ECX );
   819                 check_walign32( R_ECX );
   820                 MEM_WRITE_LONG( R_ECX, R_EAX );
   821                 sh4_x86.tstate = TSTATE_NONE;
   822                 }
   823                 break;
   824             case 0x2:
   825                 switch( ir&0xF ) {
   826                     case 0x0:
   827                         { /* MOV.B Rm, @Rn */
   828                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   829                         load_reg( R_EAX, Rm );
   830                         load_reg( R_ECX, Rn );
   831                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   832                         sh4_x86.tstate = TSTATE_NONE;
   833                         }
   834                         break;
   835                     case 0x1:
   836                         { /* MOV.W Rm, @Rn */
   837                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   838                         load_reg( R_ECX, Rn );
   839                         check_walign16( R_ECX );
   840                         load_reg( R_EAX, Rm );
   841                         MEM_WRITE_WORD( R_ECX, R_EAX );
   842                         sh4_x86.tstate = TSTATE_NONE;
   843                         }
   844                         break;
   845                     case 0x2:
   846                         { /* MOV.L Rm, @Rn */
   847                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   848                         load_reg( R_EAX, Rm );
   849                         load_reg( R_ECX, Rn );
   850                         check_walign32(R_ECX);
   851                         MEM_WRITE_LONG( R_ECX, R_EAX );
   852                         sh4_x86.tstate = TSTATE_NONE;
   853                         }
   854                         break;
   855                     case 0x4:
   856                         { /* MOV.B Rm, @-Rn */
   857                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   858                         load_reg( R_EAX, Rm );
   859                         load_reg( R_ECX, Rn );
   860                         ADD_imm8s_r32( -1, R_ECX );
   861                         store_reg( R_ECX, Rn );
   862                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   863                         sh4_x86.tstate = TSTATE_NONE;
   864                         }
   865                         break;
   866                     case 0x5:
   867                         { /* MOV.W Rm, @-Rn */
   868                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   869                         load_reg( R_ECX, Rn );
   870                         check_walign16( R_ECX );
   871                         load_reg( R_EAX, Rm );
   872                         ADD_imm8s_r32( -2, R_ECX );
   873                         store_reg( R_ECX, Rn );
   874                         MEM_WRITE_WORD( R_ECX, R_EAX );
   875                         sh4_x86.tstate = TSTATE_NONE;
   876                         }
   877                         break;
   878                     case 0x6:
   879                         { /* MOV.L Rm, @-Rn */
   880                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   881                         load_reg( R_EAX, Rm );
   882                         load_reg( R_ECX, Rn );
   883                         check_walign32( R_ECX );
   884                         ADD_imm8s_r32( -4, R_ECX );
   885                         store_reg( R_ECX, Rn );
   886                         MEM_WRITE_LONG( R_ECX, R_EAX );
   887                         sh4_x86.tstate = TSTATE_NONE;
   888                         }
   889                         break;
   890                     case 0x7:
   891                         { /* DIV0S Rm, Rn */
   892                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   893                         load_reg( R_EAX, Rm );
   894                         load_reg( R_ECX, Rn );
   895                         SHR_imm8_r32( 31, R_EAX );
   896                         SHR_imm8_r32( 31, R_ECX );
   897                         store_spreg( R_EAX, R_M );
   898                         store_spreg( R_ECX, R_Q );
   899                         CMP_r32_r32( R_EAX, R_ECX );
   900                         SETNE_t();
   901                         sh4_x86.tstate = TSTATE_NE;
   902                         }
   903                         break;
   904                     case 0x8:
   905                         { /* TST Rm, Rn */
   906                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   907                         load_reg( R_EAX, Rm );
   908                         load_reg( R_ECX, Rn );
   909                         TEST_r32_r32( R_EAX, R_ECX );
   910                         SETE_t();
   911                         sh4_x86.tstate = TSTATE_E;
   912                         }
   913                         break;
   914                     case 0x9:
   915                         { /* AND Rm, Rn */
   916                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   917                         load_reg( R_EAX, Rm );
   918                         load_reg( R_ECX, Rn );
   919                         AND_r32_r32( R_EAX, R_ECX );
   920                         store_reg( R_ECX, Rn );
   921                         sh4_x86.tstate = TSTATE_NONE;
   922                         }
   923                         break;
   924                     case 0xA:
   925                         { /* XOR Rm, Rn */
   926                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   927                         load_reg( R_EAX, Rm );
   928                         load_reg( R_ECX, Rn );
   929                         XOR_r32_r32( R_EAX, R_ECX );
   930                         store_reg( R_ECX, Rn );
   931                         sh4_x86.tstate = TSTATE_NONE;
   932                         }
   933                         break;
   934                     case 0xB:
   935                         { /* OR Rm, Rn */
   936                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   937                         load_reg( R_EAX, Rm );
   938                         load_reg( R_ECX, Rn );
   939                         OR_r32_r32( R_EAX, R_ECX );
   940                         store_reg( R_ECX, Rn );
   941                         sh4_x86.tstate = TSTATE_NONE;
   942                         }
   943                         break;
   944                     case 0xC:
   945                         { /* CMP/STR Rm, Rn */
   946                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   947                         load_reg( R_EAX, Rm );
   948                         load_reg( R_ECX, Rn );
   949                         XOR_r32_r32( R_ECX, R_EAX );
   950                         TEST_r8_r8( R_AL, R_AL );
   951                         JE_rel8(13, target1);
   952                         TEST_r8_r8( R_AH, R_AH ); // 2
   953                         JE_rel8(9, target2);
   954                         SHR_imm8_r32( 16, R_EAX ); // 3
   955                         TEST_r8_r8( R_AL, R_AL ); // 2
   956                         JE_rel8(2, target3);
   957                         TEST_r8_r8( R_AH, R_AH ); // 2
   958                         JMP_TARGET(target1);
   959                         JMP_TARGET(target2);
   960                         JMP_TARGET(target3);
   961                         SETE_t();
   962                         sh4_x86.tstate = TSTATE_E;
   963                         }
   964                         break;
   965                     case 0xD:
   966                         { /* XTRCT Rm, Rn */
   967                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   968                         load_reg( R_EAX, Rm );
   969                         load_reg( R_ECX, Rn );
   970                         SHL_imm8_r32( 16, R_EAX );
   971                         SHR_imm8_r32( 16, R_ECX );
   972                         OR_r32_r32( R_EAX, R_ECX );
   973                         store_reg( R_ECX, Rn );
   974                         sh4_x86.tstate = TSTATE_NONE;
   975                         }
   976                         break;
   977                     case 0xE:
   978                         { /* MULU.W Rm, Rn */
   979                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   980                         load_reg16u( R_EAX, Rm );
   981                         load_reg16u( R_ECX, Rn );
   982                         MUL_r32( R_ECX );
   983                         store_spreg( R_EAX, R_MACL );
   984                         sh4_x86.tstate = TSTATE_NONE;
   985                         }
   986                         break;
   987                     case 0xF:
   988                         { /* MULS.W Rm, Rn */
   989                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   990                         load_reg16s( R_EAX, Rm );
   991                         load_reg16s( R_ECX, Rn );
   992                         MUL_r32( R_ECX );
   993                         store_spreg( R_EAX, R_MACL );
   994                         sh4_x86.tstate = TSTATE_NONE;
   995                         }
   996                         break;
   997                     default:
   998                         UNDEF();
   999                         break;
  1001                 break;
  1002             case 0x3:
  1003                 switch( ir&0xF ) {
  1004                     case 0x0:
  1005                         { /* CMP/EQ Rm, Rn */
  1006                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1007                         load_reg( R_EAX, Rm );
  1008                         load_reg( R_ECX, Rn );
  1009                         CMP_r32_r32( R_EAX, R_ECX );
  1010                         SETE_t();
  1011                         sh4_x86.tstate = TSTATE_E;
  1013                         break;
  1014                     case 0x2:
  1015                         { /* CMP/HS Rm, Rn */
  1016                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1017                         load_reg( R_EAX, Rm );
  1018                         load_reg( R_ECX, Rn );
  1019                         CMP_r32_r32( R_EAX, R_ECX );
  1020                         SETAE_t();
  1021                         sh4_x86.tstate = TSTATE_AE;
  1023                         break;
  1024                     case 0x3:
  1025                         { /* CMP/GE Rm, Rn */
  1026                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1027                         load_reg( R_EAX, Rm );
  1028                         load_reg( R_ECX, Rn );
  1029                         CMP_r32_r32( R_EAX, R_ECX );
  1030                         SETGE_t();
  1031                         sh4_x86.tstate = TSTATE_GE;
  1033                         break;
  1034                     case 0x4:
  1035                         { /* DIV1 Rm, Rn */
  1036                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1037                         load_spreg( R_ECX, R_M );
  1038                         load_reg( R_EAX, Rn );
  1039                         if( sh4_x86.tstate != TSTATE_C ) {
  1040                     	LDC_t();
  1042                         RCL1_r32( R_EAX );
  1043                         SETC_r8( R_DL ); // Q'
  1044                         CMP_sh4r_r32( R_Q, R_ECX );
  1045                         JE_rel8(5, mqequal);
  1046                         ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1047                         JMP_rel8(3, end);
  1048                         JMP_TARGET(mqequal);
  1049                         SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1050                         JMP_TARGET(end);
  1051                         store_reg( R_EAX, Rn ); // Done with Rn now
  1052                         SETC_r8(R_AL); // tmp1
  1053                         XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  1054                         XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  1055                         store_spreg( R_ECX, R_Q );
  1056                         XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  1057                         MOVZX_r8_r32( R_AL, R_EAX );
  1058                         store_spreg( R_EAX, R_T );
  1059                         sh4_x86.tstate = TSTATE_NONE;
  1061                         break;
  1062                     case 0x5:
  1063                         { /* DMULU.L Rm, Rn */
  1064                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1065                         load_reg( R_EAX, Rm );
  1066                         load_reg( R_ECX, Rn );
  1067                         MUL_r32(R_ECX);
  1068                         store_spreg( R_EDX, R_MACH );
  1069                         store_spreg( R_EAX, R_MACL );    
  1070                         sh4_x86.tstate = TSTATE_NONE;
  1072                         break;
  1073                     case 0x6:
  1074                         { /* CMP/HI Rm, Rn */
  1075                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1076                         load_reg( R_EAX, Rm );
  1077                         load_reg( R_ECX, Rn );
  1078                         CMP_r32_r32( R_EAX, R_ECX );
  1079                         SETA_t();
  1080                         sh4_x86.tstate = TSTATE_A;
  1082                         break;
  1083                     case 0x7:
  1084                         { /* CMP/GT Rm, Rn */
  1085                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1086                         load_reg( R_EAX, Rm );
  1087                         load_reg( R_ECX, Rn );
  1088                         CMP_r32_r32( R_EAX, R_ECX );
  1089                         SETG_t();
  1090                         sh4_x86.tstate = TSTATE_G;
  1092                         break;
  1093                     case 0x8:
  1094                         { /* SUB Rm, Rn */
  1095                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1096                         load_reg( R_EAX, Rm );
  1097                         load_reg( R_ECX, Rn );
  1098                         SUB_r32_r32( R_EAX, R_ECX );
  1099                         store_reg( R_ECX, Rn );
  1100                         sh4_x86.tstate = TSTATE_NONE;
  1102                         break;
  1103                     case 0xA:
  1104                         { /* SUBC Rm, Rn */
  1105                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1106                         load_reg( R_EAX, Rm );
  1107                         load_reg( R_ECX, Rn );
  1108                         if( sh4_x86.tstate != TSTATE_C ) {
  1109                     	LDC_t();
  1111                         SBB_r32_r32( R_EAX, R_ECX );
  1112                         store_reg( R_ECX, Rn );
  1113                         SETC_t();
  1114                         sh4_x86.tstate = TSTATE_C;
  1116                         break;
  1117                     case 0xB:
  1118                         { /* SUBV Rm, Rn */
  1119                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1120                         load_reg( R_EAX, Rm );
  1121                         load_reg( R_ECX, Rn );
  1122                         SUB_r32_r32( R_EAX, R_ECX );
  1123                         store_reg( R_ECX, Rn );
  1124                         SETO_t();
  1125                         sh4_x86.tstate = TSTATE_O;
  1127                         break;
  1128                     case 0xC:
  1129                         { /* ADD Rm, Rn */
  1130                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1131                         load_reg( R_EAX, Rm );
  1132                         load_reg( R_ECX, Rn );
  1133                         ADD_r32_r32( R_EAX, R_ECX );
  1134                         store_reg( R_ECX, Rn );
  1135                         sh4_x86.tstate = TSTATE_NONE;
  1137                         break;
  1138                     case 0xD:
  1139                         { /* DMULS.L Rm, Rn */
  1140                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1141                         load_reg( R_EAX, Rm );
  1142                         load_reg( R_ECX, Rn );
  1143                         IMUL_r32(R_ECX);
  1144                         store_spreg( R_EDX, R_MACH );
  1145                         store_spreg( R_EAX, R_MACL );
  1146                         sh4_x86.tstate = TSTATE_NONE;
  1148                         break;
  1149                     case 0xE:
  1150                         { /* ADDC Rm, Rn */
  1151                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1152                         if( sh4_x86.tstate != TSTATE_C ) {
  1153                     	LDC_t();
  1155                         load_reg( R_EAX, Rm );
  1156                         load_reg( R_ECX, Rn );
  1157                         ADC_r32_r32( R_EAX, R_ECX );
  1158                         store_reg( R_ECX, Rn );
  1159                         SETC_t();
  1160                         sh4_x86.tstate = TSTATE_C;
  1162                         break;
  1163                     case 0xF:
  1164                         { /* ADDV Rm, Rn */
  1165                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1166                         load_reg( R_EAX, Rm );
  1167                         load_reg( R_ECX, Rn );
  1168                         ADD_r32_r32( R_EAX, R_ECX );
  1169                         store_reg( R_ECX, Rn );
  1170                         SETO_t();
  1171                         sh4_x86.tstate = TSTATE_O;
  1173                         break;
  1174                     default:
  1175                         UNDEF();
  1176                         break;
  1178                 break;
  1179             case 0x4:
  1180                 switch( ir&0xF ) {
  1181                     case 0x0:
  1182                         switch( (ir&0xF0) >> 4 ) {
  1183                             case 0x0:
  1184                                 { /* SHLL Rn */
  1185                                 uint32_t Rn = ((ir>>8)&0xF); 
  1186                                 load_reg( R_EAX, Rn );
  1187                                 SHL1_r32( R_EAX );
  1188                                 SETC_t();
  1189                                 store_reg( R_EAX, Rn );
  1190                                 sh4_x86.tstate = TSTATE_C;
  1192                                 break;
  1193                             case 0x1:
  1194                                 { /* DT Rn */
  1195                                 uint32_t Rn = ((ir>>8)&0xF); 
  1196                                 load_reg( R_EAX, Rn );
  1197                                 ADD_imm8s_r32( -1, R_EAX );
  1198                                 store_reg( R_EAX, Rn );
  1199                                 SETE_t();
  1200                                 sh4_x86.tstate = TSTATE_E;
  1202                                 break;
  1203                             case 0x2:
  1204                                 { /* SHAL Rn */
  1205                                 uint32_t Rn = ((ir>>8)&0xF); 
  1206                                 load_reg( R_EAX, Rn );
  1207                                 SHL1_r32( R_EAX );
  1208                                 SETC_t();
  1209                                 store_reg( R_EAX, Rn );
  1210                                 sh4_x86.tstate = TSTATE_C;
  1212                                 break;
  1213                             default:
  1214                                 UNDEF();
  1215                                 break;
  1217                         break;
  1218                     case 0x1:
  1219                         switch( (ir&0xF0) >> 4 ) {
  1220                             case 0x0:
  1221                                 { /* SHLR Rn */
  1222                                 uint32_t Rn = ((ir>>8)&0xF); 
  1223                                 load_reg( R_EAX, Rn );
  1224                                 SHR1_r32( R_EAX );
  1225                                 SETC_t();
  1226                                 store_reg( R_EAX, Rn );
  1227                                 sh4_x86.tstate = TSTATE_C;
  1229                                 break;
  1230                             case 0x1:
  1231                                 { /* CMP/PZ Rn */
  1232                                 uint32_t Rn = ((ir>>8)&0xF); 
  1233                                 load_reg( R_EAX, Rn );
  1234                                 CMP_imm8s_r32( 0, R_EAX );
  1235                                 SETGE_t();
  1236                                 sh4_x86.tstate = TSTATE_GE;
  1238                                 break;
  1239                             case 0x2:
  1240                                 { /* SHAR Rn */
  1241                                 uint32_t Rn = ((ir>>8)&0xF); 
  1242                                 load_reg( R_EAX, Rn );
  1243                                 SAR1_r32( R_EAX );
  1244                                 SETC_t();
  1245                                 store_reg( R_EAX, Rn );
  1246                                 sh4_x86.tstate = TSTATE_C;
  1248                                 break;
  1249                             default:
  1250                                 UNDEF();
  1251                                 break;
  1253                         break;
  1254                     case 0x2:
  1255                         switch( (ir&0xF0) >> 4 ) {
  1256                             case 0x0:
  1257                                 { /* STS.L MACH, @-Rn */
  1258                                 uint32_t Rn = ((ir>>8)&0xF); 
  1259                                 load_reg( R_ECX, Rn );
  1260                                 check_walign32( R_ECX );
  1261                                 ADD_imm8s_r32( -4, R_ECX );
  1262                                 store_reg( R_ECX, Rn );
  1263                                 load_spreg( R_EAX, R_MACH );
  1264                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1265                                 sh4_x86.tstate = TSTATE_NONE;
  1267                                 break;
  1268                             case 0x1:
  1269                                 { /* STS.L MACL, @-Rn */
  1270                                 uint32_t Rn = ((ir>>8)&0xF); 
  1271                                 load_reg( R_ECX, Rn );
  1272                                 check_walign32( R_ECX );
  1273                                 ADD_imm8s_r32( -4, R_ECX );
  1274                                 store_reg( R_ECX, Rn );
  1275                                 load_spreg( R_EAX, R_MACL );
  1276                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1277                                 sh4_x86.tstate = TSTATE_NONE;
  1279                                 break;
  1280                             case 0x2:
  1281                                 { /* STS.L PR, @-Rn */
  1282                                 uint32_t Rn = ((ir>>8)&0xF); 
  1283                                 load_reg( R_ECX, Rn );
  1284                                 check_walign32( R_ECX );
  1285                                 ADD_imm8s_r32( -4, R_ECX );
  1286                                 store_reg( R_ECX, Rn );
  1287                                 load_spreg( R_EAX, R_PR );
  1288                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1289                                 sh4_x86.tstate = TSTATE_NONE;
  1291                                 break;
  1292                             case 0x3:
  1293                                 { /* STC.L SGR, @-Rn */
  1294                                 uint32_t Rn = ((ir>>8)&0xF); 
  1295                                 check_priv();
  1296                                 load_reg( R_ECX, Rn );
  1297                                 check_walign32( R_ECX );
  1298                                 ADD_imm8s_r32( -4, R_ECX );
  1299                                 store_reg( R_ECX, Rn );
  1300                                 load_spreg( R_EAX, R_SGR );
  1301                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1302                                 sh4_x86.tstate = TSTATE_NONE;
  1304                                 break;
  1305                             case 0x5:
  1306                                 { /* STS.L FPUL, @-Rn */
  1307                                 uint32_t Rn = ((ir>>8)&0xF); 
  1308                                 load_reg( R_ECX, Rn );
  1309                                 check_walign32( R_ECX );
  1310                                 ADD_imm8s_r32( -4, R_ECX );
  1311                                 store_reg( R_ECX, Rn );
  1312                                 load_spreg( R_EAX, R_FPUL );
  1313                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1314                                 sh4_x86.tstate = TSTATE_NONE;
  1316                                 break;
  1317                             case 0x6:
  1318                                 { /* STS.L FPSCR, @-Rn */
  1319                                 uint32_t Rn = ((ir>>8)&0xF); 
  1320                                 load_reg( R_ECX, Rn );
  1321                                 check_walign32( R_ECX );
  1322                                 ADD_imm8s_r32( -4, R_ECX );
  1323                                 store_reg( R_ECX, Rn );
  1324                                 load_spreg( R_EAX, R_FPSCR );
  1325                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1326                                 sh4_x86.tstate = TSTATE_NONE;
  1328                                 break;
  1329                             case 0xF:
  1330                                 { /* STC.L DBR, @-Rn */
  1331                                 uint32_t Rn = ((ir>>8)&0xF); 
  1332                                 check_priv();
  1333                                 load_reg( R_ECX, Rn );
  1334                                 check_walign32( R_ECX );
  1335                                 ADD_imm8s_r32( -4, R_ECX );
  1336                                 store_reg( R_ECX, Rn );
  1337                                 load_spreg( R_EAX, R_DBR );
  1338                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1339                                 sh4_x86.tstate = TSTATE_NONE;
  1341                                 break;
  1342                             default:
  1343                                 UNDEF();
  1344                                 break;
  1346                         break;
  1347                     case 0x3:
  1348                         switch( (ir&0x80) >> 7 ) {
  1349                             case 0x0:
  1350                                 switch( (ir&0x70) >> 4 ) {
  1351                                     case 0x0:
  1352                                         { /* STC.L SR, @-Rn */
  1353                                         uint32_t Rn = ((ir>>8)&0xF); 
  1354                                         check_priv();
  1355                                         call_func0( sh4_read_sr );
  1356                                         load_reg( R_ECX, Rn );
  1357                                         check_walign32( R_ECX );
  1358                                         ADD_imm8s_r32( -4, R_ECX );
  1359                                         store_reg( R_ECX, Rn );
  1360                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1361                                         sh4_x86.tstate = TSTATE_NONE;
  1363                                         break;
  1364                                     case 0x1:
  1365                                         { /* STC.L GBR, @-Rn */
  1366                                         uint32_t Rn = ((ir>>8)&0xF); 
  1367                                         load_reg( R_ECX, Rn );
  1368                                         check_walign32( R_ECX );
  1369                                         ADD_imm8s_r32( -4, R_ECX );
  1370                                         store_reg( R_ECX, Rn );
  1371                                         load_spreg( R_EAX, R_GBR );
  1372                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1373                                         sh4_x86.tstate = TSTATE_NONE;
  1375                                         break;
  1376                                     case 0x2:
  1377                                         { /* STC.L VBR, @-Rn */
  1378                                         uint32_t Rn = ((ir>>8)&0xF); 
  1379                                         check_priv();
  1380                                         load_reg( R_ECX, Rn );
  1381                                         check_walign32( R_ECX );
  1382                                         ADD_imm8s_r32( -4, R_ECX );
  1383                                         store_reg( R_ECX, Rn );
  1384                                         load_spreg( R_EAX, R_VBR );
  1385                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1386                                         sh4_x86.tstate = TSTATE_NONE;
  1388                                         break;
  1389                                     case 0x3:
  1390                                         { /* STC.L SSR, @-Rn */
  1391                                         uint32_t Rn = ((ir>>8)&0xF); 
  1392                                         check_priv();
  1393                                         load_reg( R_ECX, Rn );
  1394                                         check_walign32( R_ECX );
  1395                                         ADD_imm8s_r32( -4, R_ECX );
  1396                                         store_reg( R_ECX, Rn );
  1397                                         load_spreg( R_EAX, R_SSR );
  1398                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1399                                         sh4_x86.tstate = TSTATE_NONE;
  1401                                         break;
  1402                                     case 0x4:
  1403                                         { /* STC.L SPC, @-Rn */
  1404                                         uint32_t Rn = ((ir>>8)&0xF); 
  1405                                         check_priv();
  1406                                         load_reg( R_ECX, Rn );
  1407                                         check_walign32( R_ECX );
  1408                                         ADD_imm8s_r32( -4, R_ECX );
  1409                                         store_reg( R_ECX, Rn );
  1410                                         load_spreg( R_EAX, R_SPC );
  1411                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1412                                         sh4_x86.tstate = TSTATE_NONE;
  1414                                         break;
  1415                                     default:
  1416                                         UNDEF();
  1417                                         break;
  1419                                 break;
  1420                             case 0x1:
  1421                                 { /* STC.L Rm_BANK, @-Rn */
  1422                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1423                                 check_priv();
  1424                                 load_reg( R_ECX, Rn );
  1425                                 check_walign32( R_ECX );
  1426                                 ADD_imm8s_r32( -4, R_ECX );
  1427                                 store_reg( R_ECX, Rn );
  1428                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
  1429                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1430                                 sh4_x86.tstate = TSTATE_NONE;
  1432                                 break;
  1434                         break;
  1435                     case 0x4:
  1436                         switch( (ir&0xF0) >> 4 ) {
  1437                             case 0x0:
  1438                                 { /* ROTL Rn */
  1439                                 uint32_t Rn = ((ir>>8)&0xF); 
  1440                                 load_reg( R_EAX, Rn );
  1441                                 ROL1_r32( R_EAX );
  1442                                 store_reg( R_EAX, Rn );
  1443                                 SETC_t();
  1444                                 sh4_x86.tstate = TSTATE_C;
  1446                                 break;
  1447                             case 0x2:
  1448                                 { /* ROTCL Rn */
  1449                                 uint32_t Rn = ((ir>>8)&0xF); 
  1450                                 load_reg( R_EAX, Rn );
  1451                                 if( sh4_x86.tstate != TSTATE_C ) {
  1452                             	LDC_t();
  1454                                 RCL1_r32( R_EAX );
  1455                                 store_reg( R_EAX, Rn );
  1456                                 SETC_t();
  1457                                 sh4_x86.tstate = TSTATE_C;
  1459                                 break;
  1460                             default:
  1461                                 UNDEF();
  1462                                 break;
  1464                         break;
  1465                     case 0x5:
  1466                         switch( (ir&0xF0) >> 4 ) {
  1467                             case 0x0:
  1468                                 { /* ROTR Rn */
  1469                                 uint32_t Rn = ((ir>>8)&0xF); 
  1470                                 load_reg( R_EAX, Rn );
  1471                                 ROR1_r32( R_EAX );
  1472                                 store_reg( R_EAX, Rn );
  1473                                 SETC_t();
  1474                                 sh4_x86.tstate = TSTATE_C;
  1476                                 break;
  1477                             case 0x1:
  1478                                 { /* CMP/PL Rn */
  1479                                 uint32_t Rn = ((ir>>8)&0xF); 
  1480                                 load_reg( R_EAX, Rn );
  1481                                 CMP_imm8s_r32( 0, R_EAX );
  1482                                 SETG_t();
  1483                                 sh4_x86.tstate = TSTATE_G;
  1485                                 break;
  1486                             case 0x2:
  1487                                 { /* ROTCR Rn */
  1488                                 uint32_t Rn = ((ir>>8)&0xF); 
  1489                                 load_reg( R_EAX, Rn );
  1490                                 if( sh4_x86.tstate != TSTATE_C ) {
  1491                             	LDC_t();
  1493                                 RCR1_r32( R_EAX );
  1494                                 store_reg( R_EAX, Rn );
  1495                                 SETC_t();
  1496                                 sh4_x86.tstate = TSTATE_C;
  1498                                 break;
  1499                             default:
  1500                                 UNDEF();
  1501                                 break;
  1503                         break;
  1504                     case 0x6:
  1505                         switch( (ir&0xF0) >> 4 ) {
  1506                             case 0x0:
  1507                                 { /* LDS.L @Rm+, MACH */
  1508                                 uint32_t Rm = ((ir>>8)&0xF); 
  1509                                 load_reg( R_EAX, Rm );
  1510                                 check_ralign32( R_EAX );
  1511                                 MOV_r32_r32( R_EAX, R_ECX );
  1512                                 ADD_imm8s_r32( 4, R_EAX );
  1513                                 store_reg( R_EAX, Rm );
  1514                                 MEM_READ_LONG( R_ECX, R_EAX );
  1515                                 store_spreg( R_EAX, R_MACH );
  1516                                 sh4_x86.tstate = TSTATE_NONE;
  1518                                 break;
  1519                             case 0x1:
  1520                                 { /* LDS.L @Rm+, MACL */
  1521                                 uint32_t Rm = ((ir>>8)&0xF); 
  1522                                 load_reg( R_EAX, Rm );
  1523                                 check_ralign32( R_EAX );
  1524                                 MOV_r32_r32( R_EAX, R_ECX );
  1525                                 ADD_imm8s_r32( 4, R_EAX );
  1526                                 store_reg( R_EAX, Rm );
  1527                                 MEM_READ_LONG( R_ECX, R_EAX );
  1528                                 store_spreg( R_EAX, R_MACL );
  1529                                 sh4_x86.tstate = TSTATE_NONE;
  1531                                 break;
  1532                             case 0x2:
  1533                                 { /* LDS.L @Rm+, PR */
  1534                                 uint32_t Rm = ((ir>>8)&0xF); 
  1535                                 load_reg( R_EAX, Rm );
  1536                                 check_ralign32( R_EAX );
  1537                                 MOV_r32_r32( R_EAX, R_ECX );
  1538                                 ADD_imm8s_r32( 4, R_EAX );
  1539                                 store_reg( R_EAX, Rm );
  1540                                 MEM_READ_LONG( R_ECX, R_EAX );
  1541                                 store_spreg( R_EAX, R_PR );
  1542                                 sh4_x86.tstate = TSTATE_NONE;
  1544                                 break;
  1545                             case 0x3:
  1546                                 { /* LDC.L @Rm+, SGR */
  1547                                 uint32_t Rm = ((ir>>8)&0xF); 
  1548                                 check_priv();
  1549                                 load_reg( R_EAX, Rm );
  1550                                 check_ralign32( R_EAX );
  1551                                 MOV_r32_r32( R_EAX, R_ECX );
  1552                                 ADD_imm8s_r32( 4, R_EAX );
  1553                                 store_reg( R_EAX, Rm );
  1554                                 MEM_READ_LONG( R_ECX, R_EAX );
  1555                                 store_spreg( R_EAX, R_SGR );
  1556                                 sh4_x86.tstate = TSTATE_NONE;
  1558                                 break;
  1559                             case 0x5:
  1560                                 { /* LDS.L @Rm+, FPUL */
  1561                                 uint32_t Rm = ((ir>>8)&0xF); 
  1562                                 load_reg( R_EAX, Rm );
  1563                                 check_ralign32( R_EAX );
  1564                                 MOV_r32_r32( R_EAX, R_ECX );
  1565                                 ADD_imm8s_r32( 4, R_EAX );
  1566                                 store_reg( R_EAX, Rm );
  1567                                 MEM_READ_LONG( R_ECX, R_EAX );
  1568                                 store_spreg( R_EAX, R_FPUL );
  1569                                 sh4_x86.tstate = TSTATE_NONE;
  1571                                 break;
  1572                             case 0x6:
  1573                                 { /* LDS.L @Rm+, FPSCR */
  1574                                 uint32_t Rm = ((ir>>8)&0xF); 
  1575                                 load_reg( R_EAX, Rm );
  1576                                 check_ralign32( R_EAX );
  1577                                 MOV_r32_r32( R_EAX, R_ECX );
  1578                                 ADD_imm8s_r32( 4, R_EAX );
  1579                                 store_reg( R_EAX, Rm );
  1580                                 MEM_READ_LONG( R_ECX, R_EAX );
  1581                                 store_spreg( R_EAX, R_FPSCR );
  1582                                 update_fr_bank( R_EAX );
  1583                                 sh4_x86.tstate = TSTATE_NONE;
  1585                                 break;
  1586                             case 0xF:
  1587                                 { /* LDC.L @Rm+, DBR */
  1588                                 uint32_t Rm = ((ir>>8)&0xF); 
  1589                                 check_priv();
  1590                                 load_reg( R_EAX, Rm );
  1591                                 check_ralign32( R_EAX );
  1592                                 MOV_r32_r32( R_EAX, R_ECX );
  1593                                 ADD_imm8s_r32( 4, R_EAX );
  1594                                 store_reg( R_EAX, Rm );
  1595                                 MEM_READ_LONG( R_ECX, R_EAX );
  1596                                 store_spreg( R_EAX, R_DBR );
  1597                                 sh4_x86.tstate = TSTATE_NONE;
  1599                                 break;
  1600                             default:
  1601                                 UNDEF();
  1602                                 break;
  1604                         break;
  1605                     case 0x7:
  1606                         switch( (ir&0x80) >> 7 ) {
  1607                             case 0x0:
  1608                                 switch( (ir&0x70) >> 4 ) {
  1609                                     case 0x0:
  1610                                         { /* LDC.L @Rm+, SR */
  1611                                         uint32_t Rm = ((ir>>8)&0xF); 
  1612                                         if( sh4_x86.in_delay_slot ) {
  1613                                     	SLOTILLEGAL();
  1614                                         } else {
  1615                                     	check_priv();
  1616                                     	load_reg( R_EAX, Rm );
  1617                                     	check_ralign32( R_EAX );
  1618                                     	MOV_r32_r32( R_EAX, R_ECX );
  1619                                     	ADD_imm8s_r32( 4, R_EAX );
  1620                                     	store_reg( R_EAX, Rm );
  1621                                     	MEM_READ_LONG( R_ECX, R_EAX );
  1622                                     	call_func1( sh4_write_sr, R_EAX );
  1623                                     	sh4_x86.priv_checked = FALSE;
  1624                                     	sh4_x86.fpuen_checked = FALSE;
  1625                                     	sh4_x86.tstate = TSTATE_NONE;
  1628                                         break;
  1629                                     case 0x1:
  1630                                         { /* LDC.L @Rm+, GBR */
  1631                                         uint32_t Rm = ((ir>>8)&0xF); 
  1632                                         load_reg( R_EAX, Rm );
  1633                                         check_ralign32( R_EAX );
  1634                                         MOV_r32_r32( R_EAX, R_ECX );
  1635                                         ADD_imm8s_r32( 4, R_EAX );
  1636                                         store_reg( R_EAX, Rm );
  1637                                         MEM_READ_LONG( R_ECX, R_EAX );
  1638                                         store_spreg( R_EAX, R_GBR );
  1639                                         sh4_x86.tstate = TSTATE_NONE;
  1641                                         break;
  1642                                     case 0x2:
  1643                                         { /* LDC.L @Rm+, VBR */
  1644                                         uint32_t Rm = ((ir>>8)&0xF); 
  1645                                         check_priv();
  1646                                         load_reg( R_EAX, Rm );
  1647                                         check_ralign32( R_EAX );
  1648                                         MOV_r32_r32( R_EAX, R_ECX );
  1649                                         ADD_imm8s_r32( 4, R_EAX );
  1650                                         store_reg( R_EAX, Rm );
  1651                                         MEM_READ_LONG( R_ECX, R_EAX );
  1652                                         store_spreg( R_EAX, R_VBR );
  1653                                         sh4_x86.tstate = TSTATE_NONE;
  1655                                         break;
  1656                                     case 0x3:
  1657                                         { /* LDC.L @Rm+, SSR */
  1658                                         uint32_t Rm = ((ir>>8)&0xF); 
  1659                                         check_priv();
  1660                                         load_reg( R_EAX, Rm );
  1661                                         check_ralign32( R_EAX );
  1662                                         MOV_r32_r32( R_EAX, R_ECX );
  1663                                         ADD_imm8s_r32( 4, R_EAX );
  1664                                         store_reg( R_EAX, Rm );
  1665                                         MEM_READ_LONG( R_ECX, R_EAX );
  1666                                         store_spreg( R_EAX, R_SSR );
  1667                                         sh4_x86.tstate = TSTATE_NONE;
  1669                                         break;
  1670                                     case 0x4:
  1671                                         { /* LDC.L @Rm+, SPC */
  1672                                         uint32_t Rm = ((ir>>8)&0xF); 
  1673                                         check_priv();
  1674                                         load_reg( R_EAX, Rm );
  1675                                         check_ralign32( R_EAX );
  1676                                         MOV_r32_r32( R_EAX, R_ECX );
  1677                                         ADD_imm8s_r32( 4, R_EAX );
  1678                                         store_reg( R_EAX, Rm );
  1679                                         MEM_READ_LONG( R_ECX, R_EAX );
  1680                                         store_spreg( R_EAX, R_SPC );
  1681                                         sh4_x86.tstate = TSTATE_NONE;
  1683                                         break;
  1684                                     default:
  1685                                         UNDEF();
  1686                                         break;
  1688                                 break;
  1689                             case 0x1:
  1690                                 { /* LDC.L @Rm+, Rn_BANK */
  1691                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1692                                 check_priv();
  1693                                 load_reg( R_EAX, Rm );
  1694                                 check_ralign32( R_EAX );
  1695                                 MOV_r32_r32( R_EAX, R_ECX );
  1696                                 ADD_imm8s_r32( 4, R_EAX );
  1697                                 store_reg( R_EAX, Rm );
  1698                                 MEM_READ_LONG( R_ECX, R_EAX );
  1699                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  1700                                 sh4_x86.tstate = TSTATE_NONE;
  1702                                 break;
  1704                         break;
  1705                     case 0x8:
  1706                         switch( (ir&0xF0) >> 4 ) {
  1707                             case 0x0:
  1708                                 { /* SHLL2 Rn */
  1709                                 uint32_t Rn = ((ir>>8)&0xF); 
  1710                                 load_reg( R_EAX, Rn );
  1711                                 SHL_imm8_r32( 2, R_EAX );
  1712                                 store_reg( R_EAX, Rn );
  1713                                 sh4_x86.tstate = TSTATE_NONE;
  1715                                 break;
  1716                             case 0x1:
  1717                                 { /* SHLL8 Rn */
  1718                                 uint32_t Rn = ((ir>>8)&0xF); 
  1719                                 load_reg( R_EAX, Rn );
  1720                                 SHL_imm8_r32( 8, R_EAX );
  1721                                 store_reg( R_EAX, Rn );
  1722                                 sh4_x86.tstate = TSTATE_NONE;
  1724                                 break;
  1725                             case 0x2:
  1726                                 { /* SHLL16 Rn */
  1727                                 uint32_t Rn = ((ir>>8)&0xF); 
  1728                                 load_reg( R_EAX, Rn );
  1729                                 SHL_imm8_r32( 16, R_EAX );
  1730                                 store_reg( R_EAX, Rn );
  1731                                 sh4_x86.tstate = TSTATE_NONE;
  1733                                 break;
  1734                             default:
  1735                                 UNDEF();
  1736                                 break;
  1738                         break;
  1739                     case 0x9:
  1740                         switch( (ir&0xF0) >> 4 ) {
  1741                             case 0x0:
  1742                                 { /* SHLR2 Rn */
  1743                                 uint32_t Rn = ((ir>>8)&0xF); 
  1744                                 load_reg( R_EAX, Rn );
  1745                                 SHR_imm8_r32( 2, R_EAX );
  1746                                 store_reg( R_EAX, Rn );
  1747                                 sh4_x86.tstate = TSTATE_NONE;
  1749                                 break;
  1750                             case 0x1:
  1751                                 { /* SHLR8 Rn */
  1752                                 uint32_t Rn = ((ir>>8)&0xF); 
  1753                                 load_reg( R_EAX, Rn );
  1754                                 SHR_imm8_r32( 8, R_EAX );
  1755                                 store_reg( R_EAX, Rn );
  1756                                 sh4_x86.tstate = TSTATE_NONE;
  1758                                 break;
  1759                             case 0x2:
  1760                                 { /* SHLR16 Rn */
  1761                                 uint32_t Rn = ((ir>>8)&0xF); 
  1762                                 load_reg( R_EAX, Rn );
  1763                                 SHR_imm8_r32( 16, R_EAX );
  1764                                 store_reg( R_EAX, Rn );
  1765                                 sh4_x86.tstate = TSTATE_NONE;
  1767                                 break;
  1768                             default:
  1769                                 UNDEF();
  1770                                 break;
  1772                         break;
  1773                     case 0xA:
  1774                         switch( (ir&0xF0) >> 4 ) {
  1775                             case 0x0:
  1776                                 { /* LDS Rm, MACH */
  1777                                 uint32_t Rm = ((ir>>8)&0xF); 
  1778                                 load_reg( R_EAX, Rm );
  1779                                 store_spreg( R_EAX, R_MACH );
  1781                                 break;
  1782                             case 0x1:
  1783                                 { /* LDS Rm, MACL */
  1784                                 uint32_t Rm = ((ir>>8)&0xF); 
  1785                                 load_reg( R_EAX, Rm );
  1786                                 store_spreg( R_EAX, R_MACL );
  1788                                 break;
  1789                             case 0x2:
  1790                                 { /* LDS Rm, PR */
  1791                                 uint32_t Rm = ((ir>>8)&0xF); 
  1792                                 load_reg( R_EAX, Rm );
  1793                                 store_spreg( R_EAX, R_PR );
  1795                                 break;
  1796                             case 0x3:
  1797                                 { /* LDC Rm, SGR */
  1798                                 uint32_t Rm = ((ir>>8)&0xF); 
  1799                                 check_priv();
  1800                                 load_reg( R_EAX, Rm );
  1801                                 store_spreg( R_EAX, R_SGR );
  1802                                 sh4_x86.tstate = TSTATE_NONE;
  1804                                 break;
  1805                             case 0x5:
  1806                                 { /* LDS Rm, FPUL */
  1807                                 uint32_t Rm = ((ir>>8)&0xF); 
  1808                                 load_reg( R_EAX, Rm );
  1809                                 store_spreg( R_EAX, R_FPUL );
  1811                                 break;
  1812                             case 0x6:
  1813                                 { /* LDS Rm, FPSCR */
  1814                                 uint32_t Rm = ((ir>>8)&0xF); 
  1815                                 load_reg( R_EAX, Rm );
  1816                                 store_spreg( R_EAX, R_FPSCR );
  1817                                 update_fr_bank( R_EAX );
  1818                                 sh4_x86.tstate = TSTATE_NONE;
  1820                                 break;
  1821                             case 0xF:
  1822                                 { /* LDC Rm, DBR */
  1823                                 uint32_t Rm = ((ir>>8)&0xF); 
  1824                                 check_priv();
  1825                                 load_reg( R_EAX, Rm );
  1826                                 store_spreg( R_EAX, R_DBR );
  1827                                 sh4_x86.tstate = TSTATE_NONE;
  1829                                 break;
  1830                             default:
  1831                                 UNDEF();
  1832                                 break;
  1834                         break;
  1835                     case 0xB:
  1836                         switch( (ir&0xF0) >> 4 ) {
  1837                             case 0x0:
  1838                                 { /* JSR @Rn */
  1839                                 uint32_t Rn = ((ir>>8)&0xF); 
  1840                                 if( sh4_x86.in_delay_slot ) {
  1841                             	SLOTILLEGAL();
  1842                                 } else {
  1843                             	load_imm32( R_EAX, pc + 4 );
  1844                             	store_spreg( R_EAX, R_PR );
  1845                             	load_reg( R_ECX, Rn );
  1846                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1847                             	sh4_x86.in_delay_slot = TRUE;
  1848                             	sh4_translate_instruction(pc+2);
  1849                             	exit_block_pcset(pc+2);
  1850                             	sh4_x86.branch_taken = TRUE;
  1851                             	return 4;
  1854                                 break;
  1855                             case 0x1:
  1856                                 { /* TAS.B @Rn */
  1857                                 uint32_t Rn = ((ir>>8)&0xF); 
  1858                                 load_reg( R_ECX, Rn );
  1859                                 MEM_READ_BYTE( R_ECX, R_EAX );
  1860                                 TEST_r8_r8( R_AL, R_AL );
  1861                                 SETE_t();
  1862                                 OR_imm8_r8( 0x80, R_AL );
  1863                                 load_reg( R_ECX, Rn );
  1864                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  1865                                 sh4_x86.tstate = TSTATE_NONE;
  1867                                 break;
  1868                             case 0x2:
  1869                                 { /* JMP @Rn */
  1870                                 uint32_t Rn = ((ir>>8)&0xF); 
  1871                                 if( sh4_x86.in_delay_slot ) {
  1872                             	SLOTILLEGAL();
  1873                                 } else {
  1874                             	load_reg( R_ECX, Rn );
  1875                             	store_spreg( R_ECX, REG_OFFSET(pc) );
  1876                             	sh4_x86.in_delay_slot = TRUE;
  1877                             	sh4_translate_instruction(pc+2);
  1878                             	exit_block_pcset(pc+2);
  1879                             	sh4_x86.branch_taken = TRUE;
  1880                             	return 4;
  1883                                 break;
  1884                             default:
  1885                                 UNDEF();
  1886                                 break;
  1888                         break;
  1889                     case 0xC:
  1890                         { /* SHAD Rm, Rn */
  1891                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1892                         /* Annoyingly enough, not directly convertible */
  1893                         load_reg( R_EAX, Rn );
  1894                         load_reg( R_ECX, Rm );
  1895                         CMP_imm32_r32( 0, R_ECX );
  1896                         JGE_rel8(16, doshl);
  1898                         NEG_r32( R_ECX );      // 2
  1899                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1900                         JE_rel8( 4, emptysar);     // 2
  1901                         SAR_r32_CL( R_EAX );       // 2
  1902                         JMP_rel8(10, end);          // 2
  1904                         JMP_TARGET(emptysar);
  1905                         SAR_imm8_r32(31, R_EAX );  // 3
  1906                         JMP_rel8(5, end2);
  1908                         JMP_TARGET(doshl);
  1909                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1910                         SHL_r32_CL( R_EAX );       // 2
  1911                         JMP_TARGET(end);
  1912                         JMP_TARGET(end2);
  1913                         store_reg( R_EAX, Rn );
  1914                         sh4_x86.tstate = TSTATE_NONE;
  1916                         break;
  1917                     case 0xD:
  1918                         { /* SHLD Rm, Rn */
  1919                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1920                         load_reg( R_EAX, Rn );
  1921                         load_reg( R_ECX, Rm );
  1922                         CMP_imm32_r32( 0, R_ECX );
  1923                         JGE_rel8(15, doshl);
  1925                         NEG_r32( R_ECX );      // 2
  1926                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1927                         JE_rel8( 4, emptyshr );
  1928                         SHR_r32_CL( R_EAX );       // 2
  1929                         JMP_rel8(9, end);          // 2
  1931                         JMP_TARGET(emptyshr);
  1932                         XOR_r32_r32( R_EAX, R_EAX );
  1933                         JMP_rel8(5, end2);
  1935                         JMP_TARGET(doshl);
  1936                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1937                         SHL_r32_CL( R_EAX );       // 2
  1938                         JMP_TARGET(end);
  1939                         JMP_TARGET(end2);
  1940                         store_reg( R_EAX, Rn );
  1941                         sh4_x86.tstate = TSTATE_NONE;
  1943                         break;
  1944                     case 0xE:
  1945                         switch( (ir&0x80) >> 7 ) {
  1946                             case 0x0:
  1947                                 switch( (ir&0x70) >> 4 ) {
  1948                                     case 0x0:
  1949                                         { /* LDC Rm, SR */
  1950                                         uint32_t Rm = ((ir>>8)&0xF); 
  1951                                         if( sh4_x86.in_delay_slot ) {
  1952                                     	SLOTILLEGAL();
  1953                                         } else {
  1954                                     	check_priv();
  1955                                     	load_reg( R_EAX, Rm );
  1956                                     	call_func1( sh4_write_sr, R_EAX );
  1957                                     	sh4_x86.priv_checked = FALSE;
  1958                                     	sh4_x86.fpuen_checked = FALSE;
  1959                                     	sh4_x86.tstate = TSTATE_NONE;
  1962                                         break;
  1963                                     case 0x1:
  1964                                         { /* LDC Rm, GBR */
  1965                                         uint32_t Rm = ((ir>>8)&0xF); 
  1966                                         load_reg( R_EAX, Rm );
  1967                                         store_spreg( R_EAX, R_GBR );
  1969                                         break;
  1970                                     case 0x2:
  1971                                         { /* LDC Rm, VBR */
  1972                                         uint32_t Rm = ((ir>>8)&0xF); 
  1973                                         check_priv();
  1974                                         load_reg( R_EAX, Rm );
  1975                                         store_spreg( R_EAX, R_VBR );
  1976                                         sh4_x86.tstate = TSTATE_NONE;
  1978                                         break;
  1979                                     case 0x3:
  1980                                         { /* LDC Rm, SSR */
  1981                                         uint32_t Rm = ((ir>>8)&0xF); 
  1982                                         check_priv();
  1983                                         load_reg( R_EAX, Rm );
  1984                                         store_spreg( R_EAX, R_SSR );
  1985                                         sh4_x86.tstate = TSTATE_NONE;
  1987                                         break;
  1988                                     case 0x4:
  1989                                         { /* LDC Rm, SPC */
  1990                                         uint32_t Rm = ((ir>>8)&0xF); 
  1991                                         check_priv();
  1992                                         load_reg( R_EAX, Rm );
  1993                                         store_spreg( R_EAX, R_SPC );
  1994                                         sh4_x86.tstate = TSTATE_NONE;
  1996                                         break;
  1997                                     default:
  1998                                         UNDEF();
  1999                                         break;
  2001                                 break;
  2002                             case 0x1:
  2003                                 { /* LDC Rm, Rn_BANK */
  2004                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  2005                                 check_priv();
  2006                                 load_reg( R_EAX, Rm );
  2007                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2008                                 sh4_x86.tstate = TSTATE_NONE;
  2010                                 break;
  2012                         break;
  2013                     case 0xF:
  2014                         { /* MAC.W @Rm+, @Rn+ */
  2015                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2016                         load_reg( R_ECX, Rm );
  2017                         check_ralign16( R_ECX );
  2018                         load_reg( R_ECX, Rn );
  2019                         check_ralign16( R_ECX );
  2020                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  2021                         MEM_READ_WORD( R_ECX, R_EAX );
  2022                         PUSH_realigned_r32( R_EAX );
  2023                         load_reg( R_ECX, Rm );
  2024                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2025                         MEM_READ_WORD( R_ECX, R_EAX );
  2026                         POP_realigned_r32( R_ECX );
  2027                         IMUL_r32( R_ECX );
  2029                         load_spreg( R_ECX, R_S );
  2030                         TEST_r32_r32( R_ECX, R_ECX );
  2031                         JE_rel8( 47, nosat );
  2033                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2034                         JNO_rel8( 51, end );            // 2
  2035                         load_imm32( R_EDX, 1 );         // 5
  2036                         store_spreg( R_EDX, R_MACH );   // 6
  2037                         JS_rel8( 13, positive );        // 2
  2038                         load_imm32( R_EAX, 0x80000000 );// 5
  2039                         store_spreg( R_EAX, R_MACL );   // 6
  2040                         JMP_rel8( 25, end2 );           // 2
  2042                         JMP_TARGET(positive);
  2043                         load_imm32( R_EAX, 0x7FFFFFFF );// 5
  2044                         store_spreg( R_EAX, R_MACL );   // 6
  2045                         JMP_rel8( 12, end3);            // 2
  2047                         JMP_TARGET(nosat);
  2048                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2049                         ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  2050                         JMP_TARGET(end);
  2051                         JMP_TARGET(end2);
  2052                         JMP_TARGET(end3);
  2053                         sh4_x86.tstate = TSTATE_NONE;
  2055                         break;
  2057                 break;
  2058             case 0x5:
  2059                 { /* MOV.L @(disp, Rm), Rn */
  2060                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  2061                 load_reg( R_ECX, Rm );
  2062                 ADD_imm8s_r32( disp, R_ECX );
  2063                 check_ralign32( R_ECX );
  2064                 MEM_READ_LONG( R_ECX, R_EAX );
  2065                 store_reg( R_EAX, Rn );
  2066                 sh4_x86.tstate = TSTATE_NONE;
  2068                 break;
  2069             case 0x6:
  2070                 switch( ir&0xF ) {
  2071                     case 0x0:
  2072                         { /* MOV.B @Rm, Rn */
  2073                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2074                         load_reg( R_ECX, Rm );
  2075                         MEM_READ_BYTE( R_ECX, R_EAX );
  2076                         store_reg( R_EAX, Rn );
  2077                         sh4_x86.tstate = TSTATE_NONE;
  2079                         break;
  2080                     case 0x1:
  2081                         { /* MOV.W @Rm, Rn */
  2082                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2083                         load_reg( R_ECX, Rm );
  2084                         check_ralign16( R_ECX );
  2085                         MEM_READ_WORD( R_ECX, R_EAX );
  2086                         store_reg( R_EAX, Rn );
  2087                         sh4_x86.tstate = TSTATE_NONE;
  2089                         break;
  2090                     case 0x2:
  2091                         { /* MOV.L @Rm, Rn */
  2092                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2093                         load_reg( R_ECX, Rm );
  2094                         check_ralign32( R_ECX );
  2095                         MEM_READ_LONG( R_ECX, R_EAX );
  2096                         store_reg( R_EAX, Rn );
  2097                         sh4_x86.tstate = TSTATE_NONE;
  2099                         break;
  2100                     case 0x3:
  2101                         { /* MOV Rm, Rn */
  2102                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2103                         load_reg( R_EAX, Rm );
  2104                         store_reg( R_EAX, Rn );
  2106                         break;
  2107                     case 0x4:
  2108                         { /* MOV.B @Rm+, Rn */
  2109                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2110                         load_reg( R_ECX, Rm );
  2111                         MOV_r32_r32( R_ECX, R_EAX );
  2112                         ADD_imm8s_r32( 1, R_EAX );
  2113                         store_reg( R_EAX, Rm );
  2114                         MEM_READ_BYTE( R_ECX, R_EAX );
  2115                         store_reg( R_EAX, Rn );
  2116                         sh4_x86.tstate = TSTATE_NONE;
  2118                         break;
  2119                     case 0x5:
  2120                         { /* MOV.W @Rm+, Rn */
  2121                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2122                         load_reg( R_EAX, Rm );
  2123                         check_ralign16( R_EAX );
  2124                         MOV_r32_r32( R_EAX, R_ECX );
  2125                         ADD_imm8s_r32( 2, R_EAX );
  2126                         store_reg( R_EAX, Rm );
  2127                         MEM_READ_WORD( R_ECX, R_EAX );
  2128                         store_reg( R_EAX, Rn );
  2129                         sh4_x86.tstate = TSTATE_NONE;
  2131                         break;
  2132                     case 0x6:
  2133                         { /* MOV.L @Rm+, Rn */
  2134                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2135                         load_reg( R_EAX, Rm );
  2136                         check_ralign32( R_EAX );
  2137                         MOV_r32_r32( R_EAX, R_ECX );
  2138                         ADD_imm8s_r32( 4, R_EAX );
  2139                         store_reg( R_EAX, Rm );
  2140                         MEM_READ_LONG( R_ECX, R_EAX );
  2141                         store_reg( R_EAX, Rn );
  2142                         sh4_x86.tstate = TSTATE_NONE;
  2144                         break;
  2145                     case 0x7:
  2146                         { /* NOT Rm, Rn */
  2147                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2148                         load_reg( R_EAX, Rm );
  2149                         NOT_r32( R_EAX );
  2150                         store_reg( R_EAX, Rn );
  2151                         sh4_x86.tstate = TSTATE_NONE;
  2153                         break;
  2154                     case 0x8:
  2155                         { /* SWAP.B Rm, Rn */
  2156                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2157                         load_reg( R_EAX, Rm );
  2158                         XCHG_r8_r8( R_AL, R_AH );
  2159                         store_reg( R_EAX, Rn );
  2161                         break;
  2162                     case 0x9:
  2163                         { /* SWAP.W Rm, Rn */
  2164                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2165                         load_reg( R_EAX, Rm );
  2166                         MOV_r32_r32( R_EAX, R_ECX );
  2167                         SHL_imm8_r32( 16, R_ECX );
  2168                         SHR_imm8_r32( 16, R_EAX );
  2169                         OR_r32_r32( R_EAX, R_ECX );
  2170                         store_reg( R_ECX, Rn );
  2171                         sh4_x86.tstate = TSTATE_NONE;
  2173                         break;
  2174                     case 0xA:
  2175                         { /* NEGC Rm, Rn */
  2176                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2177                         load_reg( R_EAX, Rm );
  2178                         XOR_r32_r32( R_ECX, R_ECX );
  2179                         LDC_t();
  2180                         SBB_r32_r32( R_EAX, R_ECX );
  2181                         store_reg( R_ECX, Rn );
  2182                         SETC_t();
  2183                         sh4_x86.tstate = TSTATE_C;
  2185                         break;
  2186                     case 0xB:
  2187                         { /* NEG Rm, Rn */
  2188                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2189                         load_reg( R_EAX, Rm );
  2190                         NEG_r32( R_EAX );
  2191                         store_reg( R_EAX, Rn );
  2192                         sh4_x86.tstate = TSTATE_NONE;
  2194                         break;
  2195                     case 0xC:
  2196                         { /* EXTU.B Rm, Rn */
  2197                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2198                         load_reg( R_EAX, Rm );
  2199                         MOVZX_r8_r32( R_EAX, R_EAX );
  2200                         store_reg( R_EAX, Rn );
  2202                         break;
  2203                     case 0xD:
  2204                         { /* EXTU.W Rm, Rn */
  2205                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2206                         load_reg( R_EAX, Rm );
  2207                         MOVZX_r16_r32( R_EAX, R_EAX );
  2208                         store_reg( R_EAX, Rn );
  2210                         break;
  2211                     case 0xE:
  2212                         { /* EXTS.B Rm, Rn */
  2213                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2214                         load_reg( R_EAX, Rm );
  2215                         MOVSX_r8_r32( R_EAX, R_EAX );
  2216                         store_reg( R_EAX, Rn );
  2218                         break;
  2219                     case 0xF:
  2220                         { /* EXTS.W Rm, Rn */
  2221                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2222                         load_reg( R_EAX, Rm );
  2223                         MOVSX_r16_r32( R_EAX, R_EAX );
  2224                         store_reg( R_EAX, Rn );
  2226                         break;
  2228                 break;
  2229             case 0x7:
  2230                 { /* ADD #imm, Rn */
  2231                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2232                 load_reg( R_EAX, Rn );
  2233                 ADD_imm8s_r32( imm, R_EAX );
  2234                 store_reg( R_EAX, Rn );
  2235                 sh4_x86.tstate = TSTATE_NONE;
  2237                 break;
  2238             case 0x8:
  2239                 switch( (ir&0xF00) >> 8 ) {
  2240                     case 0x0:
  2241                         { /* MOV.B R0, @(disp, Rn) */
  2242                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2243                         load_reg( R_EAX, 0 );
  2244                         load_reg( R_ECX, Rn );
  2245                         ADD_imm32_r32( disp, R_ECX );
  2246                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2247                         sh4_x86.tstate = TSTATE_NONE;
  2249                         break;
  2250                     case 0x1:
  2251                         { /* MOV.W R0, @(disp, Rn) */
  2252                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2253                         load_reg( R_ECX, Rn );
  2254                         load_reg( R_EAX, 0 );
  2255                         ADD_imm32_r32( disp, R_ECX );
  2256                         check_walign16( R_ECX );
  2257                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2258                         sh4_x86.tstate = TSTATE_NONE;
  2260                         break;
  2261                     case 0x4:
  2262                         { /* MOV.B @(disp, Rm), R0 */
  2263                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2264                         load_reg( R_ECX, Rm );
  2265                         ADD_imm32_r32( disp, R_ECX );
  2266                         MEM_READ_BYTE( R_ECX, R_EAX );
  2267                         store_reg( R_EAX, 0 );
  2268                         sh4_x86.tstate = TSTATE_NONE;
  2270                         break;
  2271                     case 0x5:
  2272                         { /* MOV.W @(disp, Rm), R0 */
  2273                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2274                         load_reg( R_ECX, Rm );
  2275                         ADD_imm32_r32( disp, R_ECX );
  2276                         check_ralign16( R_ECX );
  2277                         MEM_READ_WORD( R_ECX, R_EAX );
  2278                         store_reg( R_EAX, 0 );
  2279                         sh4_x86.tstate = TSTATE_NONE;
  2281                         break;
  2282                     case 0x8:
  2283                         { /* CMP/EQ #imm, R0 */
  2284                         int32_t imm = SIGNEXT8(ir&0xFF); 
  2285                         load_reg( R_EAX, 0 );
  2286                         CMP_imm8s_r32(imm, R_EAX);
  2287                         SETE_t();
  2288                         sh4_x86.tstate = TSTATE_E;
  2290                         break;
  2291                     case 0x9:
  2292                         { /* BT disp */
  2293                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2294                         if( sh4_x86.in_delay_slot ) {
  2295                     	SLOTILLEGAL();
  2296                         } else {
  2297                     	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
  2298                     	exit_block( disp + pc + 4, pc+2 );
  2299                     	JMP_TARGET(nottaken);
  2300                     	return 2;
  2303                         break;
  2304                     case 0xB:
  2305                         { /* BF disp */
  2306                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2307                         if( sh4_x86.in_delay_slot ) {
  2308                     	SLOTILLEGAL();
  2309                         } else {
  2310                     	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
  2311                     	exit_block( disp + pc + 4, pc+2 );
  2312                     	JMP_TARGET(nottaken);
  2313                     	return 2;
  2316                         break;
  2317                     case 0xD:
  2318                         { /* BT/S disp */
  2319                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2320                         if( sh4_x86.in_delay_slot ) {
  2321                     	SLOTILLEGAL();
  2322                         } else {
  2323                     	sh4_x86.in_delay_slot = TRUE;
  2324                     	if( sh4_x86.tstate == TSTATE_NONE ) {
  2325                     	    CMP_imm8s_sh4r( 1, R_T );
  2326                     	    sh4_x86.tstate = TSTATE_E;
  2328                     	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
  2329                     	sh4_translate_instruction(pc+2);
  2330                     	exit_block( disp + pc + 4, pc+4 );
  2331                     	// not taken
  2332                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2333                     	sh4_translate_instruction(pc+2);
  2334                     	return 4;
  2337                         break;
  2338                     case 0xF:
  2339                         { /* BF/S disp */
  2340                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2341                         if( sh4_x86.in_delay_slot ) {
  2342                     	SLOTILLEGAL();
  2343                         } else {
  2344                     	sh4_x86.in_delay_slot = TRUE;
  2345                     	if( sh4_x86.tstate == TSTATE_NONE ) {
  2346                     	    CMP_imm8s_sh4r( 1, R_T );
  2347                     	    sh4_x86.tstate = TSTATE_E;
  2349                     	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
  2350                     	sh4_translate_instruction(pc+2);
  2351                     	exit_block( disp + pc + 4, pc+4 );
  2352                     	// not taken
  2353                     	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2354                     	sh4_translate_instruction(pc+2);
  2355                     	return 4;
  2358                         break;
  2359                     default:
  2360                         UNDEF();
  2361                         break;
  2363                 break;
  2364             case 0x9:
  2365                 { /* MOV.W @(disp, PC), Rn */
  2366                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  2367                 if( sh4_x86.in_delay_slot ) {
  2368             	SLOTILLEGAL();
  2369                 } else {
  2370             	load_imm32( R_ECX, pc + disp + 4 );
  2371             	MEM_READ_WORD( R_ECX, R_EAX );
  2372             	store_reg( R_EAX, Rn );
  2373             	sh4_x86.tstate = TSTATE_NONE;
  2376                 break;
  2377             case 0xA:
  2378                 { /* BRA disp */
  2379                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2380                 if( sh4_x86.in_delay_slot ) {
  2381             	SLOTILLEGAL();
  2382                 } else {
  2383             	sh4_x86.in_delay_slot = TRUE;
  2384             	sh4_translate_instruction( pc + 2 );
  2385             	exit_block( disp + pc + 4, pc+4 );
  2386             	sh4_x86.branch_taken = TRUE;
  2387             	return 4;
  2390                 break;
  2391             case 0xB:
  2392                 { /* BSR disp */
  2393                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2394                 if( sh4_x86.in_delay_slot ) {
  2395             	SLOTILLEGAL();
  2396                 } else {
  2397             	load_imm32( R_EAX, pc + 4 );
  2398             	store_spreg( R_EAX, R_PR );
  2399             	sh4_x86.in_delay_slot = TRUE;
  2400             	sh4_translate_instruction( pc + 2 );
  2401             	exit_block( disp + pc + 4, pc+4 );
  2402             	sh4_x86.branch_taken = TRUE;
  2403             	return 4;
  2406                 break;
  2407             case 0xC:
  2408                 switch( (ir&0xF00) >> 8 ) {
  2409                     case 0x0:
  2410                         { /* MOV.B R0, @(disp, GBR) */
  2411                         uint32_t disp = (ir&0xFF); 
  2412                         load_reg( R_EAX, 0 );
  2413                         load_spreg( R_ECX, R_GBR );
  2414                         ADD_imm32_r32( disp, R_ECX );
  2415                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2416                         sh4_x86.tstate = TSTATE_NONE;
  2418                         break;
  2419                     case 0x1:
  2420                         { /* MOV.W R0, @(disp, GBR) */
  2421                         uint32_t disp = (ir&0xFF)<<1; 
  2422                         load_spreg( R_ECX, R_GBR );
  2423                         load_reg( R_EAX, 0 );
  2424                         ADD_imm32_r32( disp, R_ECX );
  2425                         check_walign16( R_ECX );
  2426                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2427                         sh4_x86.tstate = TSTATE_NONE;
  2429                         break;
  2430                     case 0x2:
  2431                         { /* MOV.L R0, @(disp, GBR) */
  2432                         uint32_t disp = (ir&0xFF)<<2; 
  2433                         load_spreg( R_ECX, R_GBR );
  2434                         load_reg( R_EAX, 0 );
  2435                         ADD_imm32_r32( disp, R_ECX );
  2436                         check_walign32( R_ECX );
  2437                         MEM_WRITE_LONG( R_ECX, R_EAX );
  2438                         sh4_x86.tstate = TSTATE_NONE;
  2440                         break;
  2441                     case 0x3:
  2442                         { /* TRAPA #imm */
  2443                         uint32_t imm = (ir&0xFF); 
  2444                         if( sh4_x86.in_delay_slot ) {
  2445                     	SLOTILLEGAL();
  2446                         } else {
  2447                     	load_imm32( R_ECX, pc+2 );
  2448                     	store_spreg( R_ECX, REG_OFFSET(pc) );
  2449                     	load_imm32( R_EAX, imm );
  2450                     	call_func1( sh4_raise_trap, R_EAX );
  2451                     	sh4_x86.tstate = TSTATE_NONE;
  2452                     	exit_block_pcset(pc);
  2453                     	sh4_x86.branch_taken = TRUE;
  2454                     	return 2;
  2457                         break;
  2458                     case 0x4:
  2459                         { /* MOV.B @(disp, GBR), R0 */
  2460                         uint32_t disp = (ir&0xFF); 
  2461                         load_spreg( R_ECX, R_GBR );
  2462                         ADD_imm32_r32( disp, R_ECX );
  2463                         MEM_READ_BYTE( R_ECX, R_EAX );
  2464                         store_reg( R_EAX, 0 );
  2465                         sh4_x86.tstate = TSTATE_NONE;
  2467                         break;
  2468                     case 0x5:
  2469                         { /* MOV.W @(disp, GBR), R0 */
  2470                         uint32_t disp = (ir&0xFF)<<1; 
  2471                         load_spreg( R_ECX, R_GBR );
  2472                         ADD_imm32_r32( disp, R_ECX );
  2473                         check_ralign16( R_ECX );
  2474                         MEM_READ_WORD( R_ECX, R_EAX );
  2475                         store_reg( R_EAX, 0 );
  2476                         sh4_x86.tstate = TSTATE_NONE;
  2478                         break;
  2479                     case 0x6:
  2480                         { /* MOV.L @(disp, GBR), R0 */
  2481                         uint32_t disp = (ir&0xFF)<<2; 
  2482                         load_spreg( R_ECX, R_GBR );
  2483                         ADD_imm32_r32( disp, R_ECX );
  2484                         check_ralign32( R_ECX );
  2485                         MEM_READ_LONG( R_ECX, R_EAX );
  2486                         store_reg( R_EAX, 0 );
  2487                         sh4_x86.tstate = TSTATE_NONE;
  2489                         break;
  2490                     case 0x7:
  2491                         { /* MOVA @(disp, PC), R0 */
  2492                         uint32_t disp = (ir&0xFF)<<2; 
  2493                         if( sh4_x86.in_delay_slot ) {
  2494                     	SLOTILLEGAL();
  2495                         } else {
  2496                     	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
  2497                     	store_reg( R_ECX, 0 );
  2500                         break;
  2501                     case 0x8:
  2502                         { /* TST #imm, R0 */
  2503                         uint32_t imm = (ir&0xFF); 
  2504                         load_reg( R_EAX, 0 );
  2505                         TEST_imm32_r32( imm, R_EAX );
  2506                         SETE_t();
  2507                         sh4_x86.tstate = TSTATE_E;
  2509                         break;
  2510                     case 0x9:
  2511                         { /* AND #imm, R0 */
  2512                         uint32_t imm = (ir&0xFF); 
  2513                         load_reg( R_EAX, 0 );
  2514                         AND_imm32_r32(imm, R_EAX); 
  2515                         store_reg( R_EAX, 0 );
  2516                         sh4_x86.tstate = TSTATE_NONE;
  2518                         break;
  2519                     case 0xA:
  2520                         { /* XOR #imm, R0 */
  2521                         uint32_t imm = (ir&0xFF); 
  2522                         load_reg( R_EAX, 0 );
  2523                         XOR_imm32_r32( imm, R_EAX );
  2524                         store_reg( R_EAX, 0 );
  2525                         sh4_x86.tstate = TSTATE_NONE;
  2527                         break;
  2528                     case 0xB:
  2529                         { /* OR #imm, R0 */
  2530                         uint32_t imm = (ir&0xFF); 
  2531                         load_reg( R_EAX, 0 );
  2532                         OR_imm32_r32(imm, R_EAX);
  2533                         store_reg( R_EAX, 0 );
  2534                         sh4_x86.tstate = TSTATE_NONE;
  2536                         break;
  2537                     case 0xC:
  2538                         { /* TST.B #imm, @(R0, GBR) */
  2539                         uint32_t imm = (ir&0xFF); 
  2540                         load_reg( R_EAX, 0);
  2541                         load_reg( R_ECX, R_GBR);
  2542                         ADD_r32_r32( R_EAX, R_ECX );
  2543                         MEM_READ_BYTE( R_ECX, R_EAX );
  2544                         TEST_imm8_r8( imm, R_AL );
  2545                         SETE_t();
  2546                         sh4_x86.tstate = TSTATE_E;
  2548                         break;
  2549                     case 0xD:
  2550                         { /* AND.B #imm, @(R0, GBR) */
  2551                         uint32_t imm = (ir&0xFF); 
  2552                         load_reg( R_EAX, 0 );
  2553                         load_spreg( R_ECX, R_GBR );
  2554                         ADD_r32_r32( R_EAX, R_ECX );
  2555                         PUSH_realigned_r32(R_ECX);
  2556                         MEM_READ_BYTE( R_ECX, R_EAX );
  2557                         POP_realigned_r32(R_ECX);
  2558                         AND_imm32_r32(imm, R_EAX );
  2559                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2560                         sh4_x86.tstate = TSTATE_NONE;
  2562                         break;
  2563                     case 0xE:
  2564                         { /* XOR.B #imm, @(R0, GBR) */
  2565                         uint32_t imm = (ir&0xFF); 
  2566                         load_reg( R_EAX, 0 );
  2567                         load_spreg( R_ECX, R_GBR );
  2568                         ADD_r32_r32( R_EAX, R_ECX );
  2569                         PUSH_realigned_r32(R_ECX);
  2570                         MEM_READ_BYTE(R_ECX, R_EAX);
  2571                         POP_realigned_r32(R_ECX);
  2572                         XOR_imm32_r32( imm, R_EAX );
  2573                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2574                         sh4_x86.tstate = TSTATE_NONE;
  2576                         break;
  2577                     case 0xF:
  2578                         { /* OR.B #imm, @(R0, GBR) */
  2579                         uint32_t imm = (ir&0xFF); 
  2580                         load_reg( R_EAX, 0 );
  2581                         load_spreg( R_ECX, R_GBR );
  2582                         ADD_r32_r32( R_EAX, R_ECX );
  2583                         PUSH_realigned_r32(R_ECX);
  2584                         MEM_READ_BYTE( R_ECX, R_EAX );
  2585                         POP_realigned_r32(R_ECX);
  2586                         OR_imm32_r32(imm, R_EAX );
  2587                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2588                         sh4_x86.tstate = TSTATE_NONE;
  2590                         break;
  2592                 break;
  2593             case 0xD:
  2594                 { /* MOV.L @(disp, PC), Rn */
  2595                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2596                 if( sh4_x86.in_delay_slot ) {
  2597             	SLOTILLEGAL();
  2598                 } else {
  2599             	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  2600             	sh4ptr_t ptr = sh4_get_region_by_vma(target);
  2601             	if( ptr != NULL ) {
  2602             	    MOV_moff32_EAX( ptr );
  2603             	} else {
  2604             	    load_imm32( R_ECX, target );
  2605             	    MEM_READ_LONG( R_ECX, R_EAX );
  2607             	store_reg( R_EAX, Rn );
  2608             	sh4_x86.tstate = TSTATE_NONE;
  2611                 break;
  2612             case 0xE:
  2613                 { /* MOV #imm, Rn */
  2614                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2615                 load_imm32( R_EAX, imm );
  2616                 store_reg( R_EAX, Rn );
  2618                 break;
  2619             case 0xF:
  2620                 switch( ir&0xF ) {
  2621                     case 0x0:
  2622                         { /* FADD FRm, FRn */
  2623                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2624                         check_fpuen();
  2625                         load_spreg( R_ECX, R_FPSCR );
  2626                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2627                         load_fr_bank( R_EDX );
  2628                         JNE_rel8(13,doubleprec);
  2629                         push_fr(R_EDX, FRm);
  2630                         push_fr(R_EDX, FRn);
  2631                         FADDP_st(1);
  2632                         pop_fr(R_EDX, FRn);
  2633                         JMP_rel8(11,end);
  2634                         JMP_TARGET(doubleprec);
  2635                         push_dr(R_EDX, FRm);
  2636                         push_dr(R_EDX, FRn);
  2637                         FADDP_st(1);
  2638                         pop_dr(R_EDX, FRn);
  2639                         JMP_TARGET(end);
  2640                         sh4_x86.tstate = TSTATE_NONE;
  2642                         break;
  2643                     case 0x1:
  2644                         { /* FSUB FRm, FRn */
  2645                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2646                         check_fpuen();
  2647                         load_spreg( R_ECX, R_FPSCR );
  2648                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2649                         load_fr_bank( R_EDX );
  2650                         JNE_rel8(13, doubleprec);
  2651                         push_fr(R_EDX, FRn);
  2652                         push_fr(R_EDX, FRm);
  2653                         FSUBP_st(1);
  2654                         pop_fr(R_EDX, FRn);
  2655                         JMP_rel8(11, end);
  2656                         JMP_TARGET(doubleprec);
  2657                         push_dr(R_EDX, FRn);
  2658                         push_dr(R_EDX, FRm);
  2659                         FSUBP_st(1);
  2660                         pop_dr(R_EDX, FRn);
  2661                         JMP_TARGET(end);
  2662                         sh4_x86.tstate = TSTATE_NONE;
  2664                         break;
  2665                     case 0x2:
  2666                         { /* FMUL FRm, FRn */
  2667                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2668                         check_fpuen();
  2669                         load_spreg( R_ECX, R_FPSCR );
  2670                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2671                         load_fr_bank( R_EDX );
  2672                         JNE_rel8(13, doubleprec);
  2673                         push_fr(R_EDX, FRm);
  2674                         push_fr(R_EDX, FRn);
  2675                         FMULP_st(1);
  2676                         pop_fr(R_EDX, FRn);
  2677                         JMP_rel8(11, end);
  2678                         JMP_TARGET(doubleprec);
  2679                         push_dr(R_EDX, FRm);
  2680                         push_dr(R_EDX, FRn);
  2681                         FMULP_st(1);
  2682                         pop_dr(R_EDX, FRn);
  2683                         JMP_TARGET(end);
  2684                         sh4_x86.tstate = TSTATE_NONE;
  2686                         break;
  2687                     case 0x3:
  2688                         { /* FDIV FRm, FRn */
  2689                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2690                         check_fpuen();
  2691                         load_spreg( R_ECX, R_FPSCR );
  2692                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2693                         load_fr_bank( R_EDX );
  2694                         JNE_rel8(13, doubleprec);
  2695                         push_fr(R_EDX, FRn);
  2696                         push_fr(R_EDX, FRm);
  2697                         FDIVP_st(1);
  2698                         pop_fr(R_EDX, FRn);
  2699                         JMP_rel8(11, end);
  2700                         JMP_TARGET(doubleprec);
  2701                         push_dr(R_EDX, FRn);
  2702                         push_dr(R_EDX, FRm);
  2703                         FDIVP_st(1);
  2704                         pop_dr(R_EDX, FRn);
  2705                         JMP_TARGET(end);
  2706                         sh4_x86.tstate = TSTATE_NONE;
  2708                         break;
  2709                     case 0x4:
  2710                         { /* FCMP/EQ FRm, FRn */
  2711                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2712                         check_fpuen();
  2713                         load_spreg( R_ECX, R_FPSCR );
  2714                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2715                         load_fr_bank( R_EDX );
  2716                         JNE_rel8(8, doubleprec);
  2717                         push_fr(R_EDX, FRm);
  2718                         push_fr(R_EDX, FRn);
  2719                         JMP_rel8(6, end);
  2720                         JMP_TARGET(doubleprec);
  2721                         push_dr(R_EDX, FRm);
  2722                         push_dr(R_EDX, FRn);
  2723                         JMP_TARGET(end);
  2724                         FCOMIP_st(1);
  2725                         SETE_t();
  2726                         FPOP_st();
  2727                         sh4_x86.tstate = TSTATE_NONE;
  2729                         break;
  2730                     case 0x5:
  2731                         { /* FCMP/GT FRm, FRn */
  2732                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2733                         check_fpuen();
  2734                         load_spreg( R_ECX, R_FPSCR );
  2735                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2736                         load_fr_bank( R_EDX );
  2737                         JNE_rel8(8, doubleprec);
  2738                         push_fr(R_EDX, FRm);
  2739                         push_fr(R_EDX, FRn);
  2740                         JMP_rel8(6, end);
  2741                         JMP_TARGET(doubleprec);
  2742                         push_dr(R_EDX, FRm);
  2743                         push_dr(R_EDX, FRn);
  2744                         JMP_TARGET(end);
  2745                         FCOMIP_st(1);
  2746                         SETA_t();
  2747                         FPOP_st();
  2748                         sh4_x86.tstate = TSTATE_NONE;
  2750                         break;
  2751                     case 0x6:
  2752                         { /* FMOV @(R0, Rm), FRn */
  2753                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2754                         check_fpuen();
  2755                         load_reg( R_ECX, Rm );
  2756                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
  2757                         check_ralign32( R_ECX );
  2758                         load_spreg( R_EDX, R_FPSCR );
  2759                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2760                         JNE_rel8(8 + MEM_READ_SIZE, doublesize);
  2761                         MEM_READ_LONG( R_ECX, R_EAX );
  2762                         load_fr_bank( R_EDX );
  2763                         store_fr( R_EDX, R_EAX, FRn );
  2764                         if( FRn&1 ) {
  2765                     	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
  2766                     	JMP_TARGET(doublesize);
  2767                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2768                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2769                     	load_xf_bank( R_EDX );
  2770                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2771                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2772                     	JMP_TARGET(end);
  2773                         } else {
  2774                     	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
  2775                     	JMP_TARGET(doublesize);
  2776                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2777                     	load_fr_bank( R_EDX );
  2778                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2779                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2780                     	JMP_TARGET(end);
  2782                         sh4_x86.tstate = TSTATE_NONE;
  2784                         break;
  2785                     case 0x7:
  2786                         { /* FMOV FRm, @(R0, Rn) */
  2787                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2788                         check_fpuen();
  2789                         load_reg( R_ECX, Rn );
  2790                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
  2791                         check_walign32( R_ECX );
  2792                         load_spreg( R_EDX, R_FPSCR );
  2793                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2794                         JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
  2795                         load_fr_bank( R_EDX );
  2796                         load_fr( R_EDX, R_EAX, FRm );
  2797                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2798                         if( FRm&1 ) {
  2799                     	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
  2800                     	JMP_TARGET(doublesize);
  2801                     	load_xf_bank( R_EDX );
  2802                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2803                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2804                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2805                     	JMP_TARGET(end);
  2806                         } else {
  2807                     	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
  2808                     	JMP_TARGET(doublesize);
  2809                     	load_fr_bank( R_EDX );
  2810                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2811                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2812                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2813                     	JMP_TARGET(end);
  2815                         sh4_x86.tstate = TSTATE_NONE;
  2817                         break;
  2818                     case 0x8:
  2819                         { /* FMOV @Rm, FRn */
  2820                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2821                         check_fpuen();
  2822                         load_reg( R_ECX, Rm );
  2823                         check_ralign32( R_ECX );
  2824                         load_spreg( R_EDX, R_FPSCR );
  2825                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2826                         JNE_rel8(8 + MEM_READ_SIZE, doublesize);
  2827                         MEM_READ_LONG( R_ECX, R_EAX );
  2828                         load_fr_bank( R_EDX );
  2829                         store_fr( R_EDX, R_EAX, FRn );
  2830                         if( FRn&1 ) {
  2831                     	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
  2832                     	JMP_TARGET(doublesize);
  2833                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2834                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2835                     	load_xf_bank( R_EDX );
  2836                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2837                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2838                     	JMP_TARGET(end);
  2839                         } else {
  2840                     	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
  2841                     	JMP_TARGET(doublesize);
  2842                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2843                     	load_fr_bank( R_EDX );
  2844                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2845                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2846                     	JMP_TARGET(end);
  2848                         sh4_x86.tstate = TSTATE_NONE;
  2850                         break;
  2851                     case 0x9:
  2852                         { /* FMOV @Rm+, FRn */
  2853                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2854                         check_fpuen();
  2855                         load_reg( R_ECX, Rm );
  2856                         check_ralign32( R_ECX );
  2857                         MOV_r32_r32( R_ECX, R_EAX );
  2858                         load_spreg( R_EDX, R_FPSCR );
  2859                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2860                         JNE_rel8(14 + MEM_READ_SIZE, doublesize);
  2861                         ADD_imm8s_r32( 4, R_EAX );
  2862                         store_reg( R_EAX, Rm );
  2863                         MEM_READ_LONG( R_ECX, R_EAX );
  2864                         load_fr_bank( R_EDX );
  2865                         store_fr( R_EDX, R_EAX, FRn );
  2866                         if( FRn&1 ) {
  2867                     	JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
  2868                     	JMP_TARGET(doublesize);
  2869                     	ADD_imm8s_r32( 8, R_EAX );
  2870                     	store_reg(R_EAX, Rm);
  2871                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2872                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  2873                     	load_xf_bank( R_EDX );
  2874                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2875                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2876                     	JMP_TARGET(end);
  2877                         } else {
  2878                     	JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
  2879                     	ADD_imm8s_r32( 8, R_EAX );
  2880                     	store_reg(R_EAX, Rm);
  2881                     	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
  2882                     	load_fr_bank( R_EDX );
  2883                     	store_fr( R_EDX, R_EAX, FRn&0x0E );
  2884                     	store_fr( R_EDX, R_ECX, FRn|0x01 );
  2885                     	JMP_TARGET(end);
  2887                         sh4_x86.tstate = TSTATE_NONE;
  2889                         break;
  2890                     case 0xA:
  2891                         { /* FMOV FRm, @Rn */
  2892                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2893                         check_fpuen();
  2894                         load_reg( R_ECX, Rn );
  2895                         check_walign32( R_ECX );
  2896                         load_spreg( R_EDX, R_FPSCR );
  2897                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2898                         JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
  2899                         load_fr_bank( R_EDX );
  2900                         load_fr( R_EDX, R_EAX, FRm );
  2901                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2902                         if( FRm&1 ) {
  2903                     	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
  2904                     	JMP_TARGET(doublesize);
  2905                     	load_xf_bank( R_EDX );
  2906                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2907                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2908                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2909                     	JMP_TARGET(end);
  2910                         } else {
  2911                     	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
  2912                     	JMP_TARGET(doublesize);
  2913                     	load_fr_bank( R_EDX );
  2914                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2915                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2916                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2917                     	JMP_TARGET(end);
  2919                         sh4_x86.tstate = TSTATE_NONE;
  2921                         break;
  2922                     case 0xB:
  2923                         { /* FMOV FRm, @-Rn */
  2924                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2925                         check_fpuen();
  2926                         load_reg( R_ECX, Rn );
  2927                         check_walign32( R_ECX );
  2928                         load_spreg( R_EDX, R_FPSCR );
  2929                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  2930                         JNE_rel8(14 + MEM_WRITE_SIZE, doublesize);
  2931                         load_fr_bank( R_EDX );
  2932                         load_fr( R_EDX, R_EAX, FRm );
  2933                         ADD_imm8s_r32(-4,R_ECX);
  2934                         store_reg( R_ECX, Rn );
  2935                         MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
  2936                         if( FRm&1 ) {
  2937                     	JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
  2938                     	JMP_TARGET(doublesize);
  2939                     	load_xf_bank( R_EDX );
  2940                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2941                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2942                     	ADD_imm8s_r32(-8,R_ECX);
  2943                     	store_reg( R_ECX, Rn );
  2944                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2945                     	JMP_TARGET(end);
  2946                         } else {
  2947                     	JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
  2948                     	JMP_TARGET(doublesize);
  2949                     	load_fr_bank( R_EDX );
  2950                     	load_fr( R_EDX, R_EAX, FRm&0x0E );
  2951                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  2952                     	ADD_imm8s_r32(-8,R_ECX);
  2953                     	store_reg( R_ECX, Rn );
  2954                     	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
  2955                     	JMP_TARGET(end);
  2957                         sh4_x86.tstate = TSTATE_NONE;
  2959                         break;
  2960                     case 0xC:
  2961                         { /* FMOV FRm, FRn */
  2962                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2963                         /* As horrible as this looks, it's actually covering 5 separate cases:
  2964                          * 1. 32-bit fr-to-fr (PR=0)
  2965                          * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
  2966                          * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
  2967                          * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
  2968                          * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
  2969                          */
  2970                         check_fpuen();
  2971                         load_spreg( R_ECX, R_FPSCR );
  2972                         load_fr_bank( R_EDX );
  2973                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2974                         JNE_rel8(8, doublesize);
  2975                         load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
  2976                         store_fr( R_EDX, R_EAX, FRn );
  2977                         if( FRm&1 ) {
  2978                     	JMP_rel8(24, end);
  2979                     	JMP_TARGET(doublesize);
  2980                     	load_xf_bank( R_ECX ); 
  2981                     	load_fr( R_ECX, R_EAX, FRm-1 );
  2982                     	if( FRn&1 ) {
  2983                     	    load_fr( R_ECX, R_EDX, FRm );
  2984                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  2985                     	    store_fr( R_ECX, R_EDX, FRn );
  2986                     	} else /* FRn&1 == 0 */ {
  2987                     	    load_fr( R_ECX, R_ECX, FRm );
  2988                     	    store_fr( R_EDX, R_EAX, FRn );
  2989                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  2991                     	JMP_TARGET(end);
  2992                         } else /* FRm&1 == 0 */ {
  2993                     	if( FRn&1 ) {
  2994                     	    JMP_rel8(24, end);
  2995                     	    load_xf_bank( R_ECX );
  2996                     	    load_fr( R_EDX, R_EAX, FRm );
  2997                     	    load_fr( R_EDX, R_EDX, FRm+1 );
  2998                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  2999                     	    store_fr( R_ECX, R_EDX, FRn );
  3000                     	    JMP_TARGET(end);
  3001                     	} else /* FRn&1 == 0 */ {
  3002                     	    JMP_rel8(12, end);
  3003                     	    load_fr( R_EDX, R_EAX, FRm );
  3004                     	    load_fr( R_EDX, R_ECX, FRm+1 );
  3005                     	    store_fr( R_EDX, R_EAX, FRn );
  3006                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3007                     	    JMP_TARGET(end);
  3010                         sh4_x86.tstate = TSTATE_NONE;
  3012                         break;
  3013                     case 0xD:
  3014                         switch( (ir&0xF0) >> 4 ) {
  3015                             case 0x0:
  3016                                 { /* FSTS FPUL, FRn */
  3017                                 uint32_t FRn = ((ir>>8)&0xF); 
  3018                                 check_fpuen();
  3019                                 load_fr_bank( R_ECX );
  3020                                 load_spreg( R_EAX, R_FPUL );
  3021                                 store_fr( R_ECX, R_EAX, FRn );
  3022                                 sh4_x86.tstate = TSTATE_NONE;
  3024                                 break;
  3025                             case 0x1:
  3026                                 { /* FLDS FRm, FPUL */
  3027                                 uint32_t FRm = ((ir>>8)&0xF); 
  3028                                 check_fpuen();
  3029                                 load_fr_bank( R_ECX );
  3030                                 load_fr( R_ECX, R_EAX, FRm );
  3031                                 store_spreg( R_EAX, R_FPUL );
  3032                                 sh4_x86.tstate = TSTATE_NONE;
  3034                                 break;
  3035                             case 0x2:
  3036                                 { /* FLOAT FPUL, FRn */
  3037                                 uint32_t FRn = ((ir>>8)&0xF); 
  3038                                 check_fpuen();
  3039                                 load_spreg( R_ECX, R_FPSCR );
  3040                                 load_spreg(R_EDX, REG_OFFSET(fr_bank));
  3041                                 FILD_sh4r(R_FPUL);
  3042                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3043                                 JNE_rel8(5, doubleprec);
  3044                                 pop_fr( R_EDX, FRn );
  3045                                 JMP_rel8(3, end);
  3046                                 JMP_TARGET(doubleprec);
  3047                                 pop_dr( R_EDX, FRn );
  3048                                 JMP_TARGET(end);
  3049                                 sh4_x86.tstate = TSTATE_NONE;
  3051                                 break;
  3052                             case 0x3:
  3053                                 { /* FTRC FRm, FPUL */
  3054                                 uint32_t FRm = ((ir>>8)&0xF); 
  3055                                 check_fpuen();
  3056                                 load_spreg( R_ECX, R_FPSCR );
  3057                                 load_fr_bank( R_EDX );
  3058                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3059                                 JNE_rel8(5, doubleprec);
  3060                                 push_fr( R_EDX, FRm );
  3061                                 JMP_rel8(3, doop);
  3062                                 JMP_TARGET(doubleprec);
  3063                                 push_dr( R_EDX, FRm );
  3064                                 JMP_TARGET( doop );
  3065                                 load_imm32( R_ECX, (uint32_t)&max_int );
  3066                                 FILD_r32ind( R_ECX );
  3067                                 FCOMIP_st(1);
  3068                                 JNA_rel8( 32, sat );
  3069                                 load_imm32( R_ECX, (uint32_t)&min_int );  // 5
  3070                                 FILD_r32ind( R_ECX );           // 2
  3071                                 FCOMIP_st(1);                   // 2
  3072                                 JAE_rel8( 21, sat2 );            // 2
  3073                                 load_imm32( R_EAX, (uint32_t)&save_fcw );
  3074                                 FNSTCW_r32ind( R_EAX );
  3075                                 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
  3076                                 FLDCW_r32ind( R_EDX );
  3077                                 FISTP_sh4r(R_FPUL);             // 3
  3078                                 FLDCW_r32ind( R_EAX );
  3079                                 JMP_rel8( 9, end );             // 2
  3081                                 JMP_TARGET(sat);
  3082                                 JMP_TARGET(sat2);
  3083                                 MOV_r32ind_r32( R_ECX, R_ECX ); // 2
  3084                                 store_spreg( R_ECX, R_FPUL );
  3085                                 FPOP_st();
  3086                                 JMP_TARGET(end);
  3087                                 sh4_x86.tstate = TSTATE_NONE;
  3089                                 break;
  3090                             case 0x4:
  3091                                 { /* FNEG FRn */
  3092                                 uint32_t FRn = ((ir>>8)&0xF); 
  3093                                 check_fpuen();
  3094                                 load_spreg( R_ECX, R_FPSCR );
  3095                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3096                                 load_fr_bank( R_EDX );
  3097                                 JNE_rel8(10, doubleprec);
  3098                                 push_fr(R_EDX, FRn);
  3099                                 FCHS_st0();
  3100                                 pop_fr(R_EDX, FRn);
  3101                                 JMP_rel8(8, end);
  3102                                 JMP_TARGET(doubleprec);
  3103                                 push_dr(R_EDX, FRn);
  3104                                 FCHS_st0();
  3105                                 pop_dr(R_EDX, FRn);
  3106                                 JMP_TARGET(end);
  3107                                 sh4_x86.tstate = TSTATE_NONE;
  3109                                 break;
  3110                             case 0x5:
  3111                                 { /* FABS FRn */
  3112                                 uint32_t FRn = ((ir>>8)&0xF); 
  3113                                 check_fpuen();
  3114                                 load_spreg( R_ECX, R_FPSCR );
  3115                                 load_fr_bank( R_EDX );
  3116                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3117                                 JNE_rel8(10, doubleprec);
  3118                                 push_fr(R_EDX, FRn); // 3
  3119                                 FABS_st0(); // 2
  3120                                 pop_fr( R_EDX, FRn); //3
  3121                                 JMP_rel8(8,end); // 2
  3122                                 JMP_TARGET(doubleprec);
  3123                                 push_dr(R_EDX, FRn);
  3124                                 FABS_st0();
  3125                                 pop_dr(R_EDX, FRn);
  3126                                 JMP_TARGET(end);
  3127                                 sh4_x86.tstate = TSTATE_NONE;
  3129                                 break;
  3130                             case 0x6:
  3131                                 { /* FSQRT FRn */
  3132                                 uint32_t FRn = ((ir>>8)&0xF); 
  3133                                 check_fpuen();
  3134                                 load_spreg( R_ECX, R_FPSCR );
  3135                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3136                                 load_fr_bank( R_EDX );
  3137                                 JNE_rel8(10, doubleprec);
  3138                                 push_fr(R_EDX, FRn);
  3139                                 FSQRT_st0();
  3140                                 pop_fr(R_EDX, FRn);
  3141                                 JMP_rel8(8, end);
  3142                                 JMP_TARGET(doubleprec);
  3143                                 push_dr(R_EDX, FRn);
  3144                                 FSQRT_st0();
  3145                                 pop_dr(R_EDX, FRn);
  3146                                 JMP_TARGET(end);
  3147                                 sh4_x86.tstate = TSTATE_NONE;
  3149                                 break;
  3150                             case 0x7:
  3151                                 { /* FSRRA FRn */
  3152                                 uint32_t FRn = ((ir>>8)&0xF); 
  3153                                 check_fpuen();
  3154                                 load_spreg( R_ECX, R_FPSCR );
  3155                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3156                                 load_fr_bank( R_EDX );
  3157                                 JNE_rel8(12, end); // PR=0 only
  3158                                 FLD1_st0();
  3159                                 push_fr(R_EDX, FRn);
  3160                                 FSQRT_st0();
  3161                                 FDIVP_st(1);
  3162                                 pop_fr(R_EDX, FRn);
  3163                                 JMP_TARGET(end);
  3164                                 sh4_x86.tstate = TSTATE_NONE;
  3166                                 break;
  3167                             case 0x8:
  3168                                 { /* FLDI0 FRn */
  3169                                 uint32_t FRn = ((ir>>8)&0xF); 
  3170                                 /* IFF PR=0 */
  3171                                   check_fpuen();
  3172                                   load_spreg( R_ECX, R_FPSCR );
  3173                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3174                                   JNE_rel8(8, end);
  3175                                   XOR_r32_r32( R_EAX, R_EAX );
  3176                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3177                                   store_fr( R_ECX, R_EAX, FRn );
  3178                                   JMP_TARGET(end);
  3179                                   sh4_x86.tstate = TSTATE_NONE;
  3181                                 break;
  3182                             case 0x9:
  3183                                 { /* FLDI1 FRn */
  3184                                 uint32_t FRn = ((ir>>8)&0xF); 
  3185                                 /* IFF PR=0 */
  3186                                   check_fpuen();
  3187                                   load_spreg( R_ECX, R_FPSCR );
  3188                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3189                                   JNE_rel8(11, end);
  3190                                   load_imm32(R_EAX, 0x3F800000);
  3191                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3192                                   store_fr( R_ECX, R_EAX, FRn );
  3193                                   JMP_TARGET(end);
  3194                                   sh4_x86.tstate = TSTATE_NONE;
  3196                                 break;
  3197                             case 0xA:
  3198                                 { /* FCNVSD FPUL, FRn */
  3199                                 uint32_t FRn = ((ir>>8)&0xF); 
  3200                                 check_fpuen();
  3201                                 load_spreg( R_ECX, R_FPSCR );
  3202                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3203                                 JE_rel8(9, end); // only when PR=1
  3204                                 load_fr_bank( R_ECX );
  3205                                 push_fpul();
  3206                                 pop_dr( R_ECX, FRn );
  3207                                 JMP_TARGET(end);
  3208                                 sh4_x86.tstate = TSTATE_NONE;
  3210                                 break;
  3211                             case 0xB:
  3212                                 { /* FCNVDS FRm, FPUL */
  3213                                 uint32_t FRm = ((ir>>8)&0xF); 
  3214                                 check_fpuen();
  3215                                 load_spreg( R_ECX, R_FPSCR );
  3216                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3217                                 JE_rel8(9, end); // only when PR=1
  3218                                 load_fr_bank( R_ECX );
  3219                                 push_dr( R_ECX, FRm );
  3220                                 pop_fpul();
  3221                                 JMP_TARGET(end);
  3222                                 sh4_x86.tstate = TSTATE_NONE;
  3224                                 break;
  3225                             case 0xE:
  3226                                 { /* FIPR FVm, FVn */
  3227                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  3228                                 check_fpuen();
  3229                                 load_spreg( R_ECX, R_FPSCR );
  3230                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3231                                 JNE_rel8(44, doubleprec);
  3233                                 load_fr_bank( R_ECX );
  3234                                 push_fr( R_ECX, FVm<<2 );
  3235                                 push_fr( R_ECX, FVn<<2 );
  3236                                 FMULP_st(1);
  3237                                 push_fr( R_ECX, (FVm<<2)+1);
  3238                                 push_fr( R_ECX, (FVn<<2)+1);
  3239                                 FMULP_st(1);
  3240                                 FADDP_st(1);
  3241                                 push_fr( R_ECX, (FVm<<2)+2);
  3242                                 push_fr( R_ECX, (FVn<<2)+2);
  3243                                 FMULP_st(1);
  3244                                 FADDP_st(1);
  3245                                 push_fr( R_ECX, (FVm<<2)+3);
  3246                                 push_fr( R_ECX, (FVn<<2)+3);
  3247                                 FMULP_st(1);
  3248                                 FADDP_st(1);
  3249                                 pop_fr( R_ECX, (FVn<<2)+3);
  3250                                 JMP_TARGET(doubleprec);
  3251                                 sh4_x86.tstate = TSTATE_NONE;
  3253                                 break;
  3254                             case 0xF:
  3255                                 switch( (ir&0x100) >> 8 ) {
  3256                                     case 0x0:
  3257                                         { /* FSCA FPUL, FRn */
  3258                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  3259                                         check_fpuen();
  3260                                         load_spreg( R_ECX, R_FPSCR );
  3261                                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3262                                         JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
  3263                                         load_fr_bank( R_ECX );
  3264                                         ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
  3265                                         load_spreg( R_EDX, R_FPUL );
  3266                                         call_func2( sh4_fsca, R_EDX, R_ECX );
  3267                                         JMP_TARGET(doubleprec);
  3268                                         sh4_x86.tstate = TSTATE_NONE;
  3270                                         break;
  3271                                     case 0x1:
  3272                                         switch( (ir&0x200) >> 9 ) {
  3273                                             case 0x0:
  3274                                                 { /* FTRV XMTRX, FVn */
  3275                                                 uint32_t FVn = ((ir>>10)&0x3); 
  3276                                                 check_fpuen();
  3277                                                 load_spreg( R_ECX, R_FPSCR );
  3278                                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3279                                                 JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
  3280                                                 load_fr_bank( R_EDX );                 // 3
  3281                                                 ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
  3282                                                 load_xf_bank( R_ECX );                 // 12
  3283                                                 call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
  3284                                                 JMP_TARGET(doubleprec);
  3285                                                 sh4_x86.tstate = TSTATE_NONE;
  3287                                                 break;
  3288                                             case 0x1:
  3289                                                 switch( (ir&0xC00) >> 10 ) {
  3290                                                     case 0x0:
  3291                                                         { /* FSCHG */
  3292                                                         check_fpuen();
  3293                                                         load_spreg( R_ECX, R_FPSCR );
  3294                                                         XOR_imm32_r32( FPSCR_SZ, R_ECX );
  3295                                                         store_spreg( R_ECX, R_FPSCR );
  3296                                                         sh4_x86.tstate = TSTATE_NONE;
  3298                                                         break;
  3299                                                     case 0x2:
  3300                                                         { /* FRCHG */
  3301                                                         check_fpuen();
  3302                                                         load_spreg( R_ECX, R_FPSCR );
  3303                                                         XOR_imm32_r32( FPSCR_FR, R_ECX );
  3304                                                         store_spreg( R_ECX, R_FPSCR );
  3305                                                         update_fr_bank( R_ECX );
  3306                                                         sh4_x86.tstate = TSTATE_NONE;
  3308                                                         break;
  3309                                                     case 0x3:
  3310                                                         { /* UNDEF */
  3311                                                         if( sh4_x86.in_delay_slot ) {
  3312                                                     	SLOTILLEGAL();
  3313                                                         } else {
  3314                                                     	JMP_exc(EXC_ILLEGAL);
  3315                                                     	return 2;
  3318                                                         break;
  3319                                                     default:
  3320                                                         UNDEF();
  3321                                                         break;
  3323                                                 break;
  3325                                         break;
  3327                                 break;
  3328                             default:
  3329                                 UNDEF();
  3330                                 break;
  3332                         break;
  3333                     case 0xE:
  3334                         { /* FMAC FR0, FRm, FRn */
  3335                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3336                         check_fpuen();
  3337                         load_spreg( R_ECX, R_FPSCR );
  3338                         load_spreg( R_EDX, REG_OFFSET(fr_bank));
  3339                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3340                         JNE_rel8(18, doubleprec);
  3341                         push_fr( R_EDX, 0 );
  3342                         push_fr( R_EDX, FRm );
  3343                         FMULP_st(1);
  3344                         push_fr( R_EDX, FRn );
  3345                         FADDP_st(1);
  3346                         pop_fr( R_EDX, FRn );
  3347                         JMP_rel8(16, end);
  3348                         JMP_TARGET(doubleprec);
  3349                         push_dr( R_EDX, 0 );
  3350                         push_dr( R_EDX, FRm );
  3351                         FMULP_st(1);
  3352                         push_dr( R_EDX, FRn );
  3353                         FADDP_st(1);
  3354                         pop_dr( R_EDX, FRn );
  3355                         JMP_TARGET(end);
  3356                         sh4_x86.tstate = TSTATE_NONE;
  3358                         break;
  3359                     default:
  3360                         UNDEF();
  3361                         break;
  3363                 break;
  3366     sh4_x86.in_delay_slot = FALSE;
  3367     return 0;
.