lxdream.org :: lxdream/src/pvr2/pvr2.c r304:2855cf8709a5

tree revision 319:5392aed6a982

filename	src/pvr2/pvr2.c
changeset	304:2855cf8709a5
prev	295:6637664291a8
next	335:fb890e1814c0
author	nkeynes
date	Wed Jan 24 08:11:14 2007 +0000 (17 years ago)
permissions	-rw-r--r--
last change	Add support for quads (auto-calculated 4th vertex)

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     1 /**

     2  * $Id: pvr2.c,v 1.41 2007-01-18 11:13:12 nkeynes Exp $

     3  *

     4  * PVR2 (Video) Core module implementation and MMIO registers.

     5  *

     6  * Copyright (c) 2005 Nathan Keynes.

     7  *

     8  * This program is free software; you can redistribute it and/or modify

     9  * it under the terms of the GNU General Public License as published by

    10  * the Free Software Foundation; either version 2 of the License, or

    11  * (at your option) any later version.

    12  *

    13  * This program is distributed in the hope that it will be useful,

    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    16  * GNU General Public License for more details.

    17  */

    18 #define MODULE pvr2_module

    20 #include "dream.h"

    21 #include "eventq.h"

    22 #include "display.h"

    23 #include "mem.h"

    24 #include "asic.h"

    25 #include "clock.h"

    26 #include "pvr2/pvr2.h"

    27 #include "sh4/sh4core.h"

    28 #define MMIO_IMPL

    29 #include "pvr2/pvr2mmio.h"

    31 char *video_base;

    33 #define HPOS_PER_FRAME 0

    34 #define HPOS_PER_LINECOUNT 1

    36 static void pvr2_init( void );

    37 static void pvr2_reset( void );

    38 static uint32_t pvr2_run_slice( uint32_t );

    39 static void pvr2_save_state( FILE *f );

    40 static int pvr2_load_state( FILE *f );

    41 static void pvr2_update_raster_posn( uint32_t nanosecs );

    42 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );

    43 uint32_t pvr2_get_sync_status();

    45 void pvr2_display_frame( void );

    47 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };

    49 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,

    50 					pvr2_run_slice, NULL,

    51 					pvr2_save_state, pvr2_load_state };

    54 display_driver_t display_driver = NULL;

    56 struct video_timing {

    57     int fields_per_second;

    58     int total_lines;

    59     int retrace_lines;

    60     int line_time_ns;

    61 };

    63 struct video_timing pal_timing = { 50, 625, 65, 31945 };

    64 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };

    66 struct pvr2_state {

    67     uint32_t frame_count;

    68     uint32_t line_count;

    69     uint32_t line_remainder;

    70     uint32_t cycles_run; /* Cycles already executed prior to main time slice */

    71     uint32_t irq_hpos_line;

    72     uint32_t irq_hpos_line_count;

    73     uint32_t irq_hpos_mode;

    74     uint32_t irq_hpos_time_ns; /* Time within the line */

    75     uint32_t irq_vpos1;

    76     uint32_t irq_vpos2;

    77     uint32_t odd_even_field; /* 1 = odd, 0 = even */

    78     gchar *save_next_render_filename;

    79     /* timing */

    80     uint32_t dot_clock;

    81     uint32_t total_lines;

    82     uint32_t line_size;

    83     uint32_t line_time_ns;

    84     uint32_t vsync_lines;

    85     uint32_t hsync_width_ns;

    86     uint32_t front_porch_ns;

    87     uint32_t back_porch_ns;

    88     uint32_t retrace_start_line;

    89     uint32_t retrace_end_line;

    90     gboolean interlaced;

    91     struct video_timing timing;

    92 } pvr2_state;

    94 struct video_buffer video_buffer[2];

    95 int video_buffer_idx = 0;

    97 /**

    98  * Event handler for the hpos callback

    99  */

   100 static void pvr2_hpos_callback( int eventid ) {

   101     asic_event( eventid );

   102     pvr2_update_raster_posn(sh4r.slice_cycle);

   103     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {

   104 	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;

   105 	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   106 	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   107 	}

   108     }

   109     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,

   110 				  pvr2_state.irq_hpos_time_ns );

   111 }

   113 /**

   114  * Event handler for the scanline callbacks. Fires the corresponding

   115  * ASIC event, and resets the timer for the next field.

   116  */

   117 static void pvr2_scanline_callback( int eventid ) {

   118     asic_event( eventid );

   119     pvr2_update_raster_posn(sh4r.slice_cycle);

   120     if( eventid == EVENT_SCANLINE1 ) {

   121 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );

   122     } else {

   123 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );

   124     }

   125 }

   127 static void pvr2_init( void )

   128 {

   129     register_io_region( &mmio_region_PVR2 );

   130     register_io_region( &mmio_region_PVR2PAL );

   131     register_io_region( &mmio_region_PVR2TA );

   132     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );

   133     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );

   134     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );

   135     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );

   136     texcache_init();

   137     pvr2_reset();

   138     pvr2_ta_reset();

   139     pvr2_state.save_next_render_filename = NULL;

   140 }

   142 static void pvr2_reset( void )

   143 {

   144     pvr2_state.line_count = 0;

   145     pvr2_state.line_remainder = 0;

   146     pvr2_state.cycles_run = 0;

   147     pvr2_state.irq_vpos1 = 0;

   148     pvr2_state.irq_vpos2 = 0;

   149     pvr2_state.timing = ntsc_timing;

   150     pvr2_state.dot_clock = PVR2_DOT_CLOCK;

   151     pvr2_state.back_porch_ns = 4000;

   152     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );

   153     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );

   154     mmio_region_PVR2_write( YUV_ADDR, 0 );

   155     mmio_region_PVR2_write( YUV_CFG, 0 );

   156     video_buffer_idx = 0;

   158     pvr2_ta_init();

   159     pvr2_render_init();

   160     texcache_flush();

   161 }

   163 static void pvr2_save_state( FILE *f )

   164 {

   165     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );

   166     pvr2_ta_save_state( f );

   167     pvr2_yuv_save_state( f );

   168 }

   170 static int pvr2_load_state( FILE *f )

   171 {

   172     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )

   173 	return 1;

   174     if( pvr2_ta_load_state(f) ) {

   175 	return 1;

   176     }

   177     return pvr2_yuv_load_state(f);

   178 }

   180 /**

   181  * Update the current raster position to the given number of nanoseconds,

   182  * relative to the last time slice. (ie the raster will be adjusted forward

   183  * by nanosecs - nanosecs_already_run_this_timeslice)

   184  */

   185 static void pvr2_update_raster_posn( uint32_t nanosecs )

   186 {

   187     uint32_t old_line_count = pvr2_state.line_count;

   188     if( pvr2_state.line_time_ns == 0 ) {

   189 	return; /* do nothing */

   190     }

   191     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);

   192     pvr2_state.cycles_run = nanosecs;

   193     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {

   194 	pvr2_state.line_count ++;

   195 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;

   196     }

   198     if( pvr2_state.line_count >= pvr2_state.total_lines ) {

   199 	pvr2_state.line_count -= pvr2_state.total_lines;

   200 	if( pvr2_state.interlaced ) {

   201 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;

   202 	}

   203     }

   204     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&

   205 	(old_line_count < pvr2_state.retrace_end_line ||

   206 	 old_line_count > pvr2_state.line_count) ) {

   207 	pvr2_display_frame();

   208     }

   209 }

   211 static uint32_t pvr2_run_slice( uint32_t nanosecs )

   212 {

   213     pvr2_update_raster_posn( nanosecs );

   214     pvr2_state.cycles_run = 0;

   215     return nanosecs;

   216 }

   218 int pvr2_get_frame_count()

   219 {

   220     return pvr2_state.frame_count;

   221 }

   223 gboolean pvr2_save_next_scene( const gchar *filename )

   224 {

   225     if( pvr2_state.save_next_render_filename != NULL ) {

   226 	g_free( pvr2_state.save_next_render_filename );

   227     }

   228     pvr2_state.save_next_render_filename = g_strdup(filename);

   229     return TRUE;

   230 }

   234 /**

   235  * Display the next frame, copying the current contents of video ram to

   236  * the window. If the video configuration has changed, first recompute the

   237  * new frame size/depth.

   238  */

   239 void pvr2_display_frame( void )

   240 {

   241     uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );

   243     int dispsize = MMIO_READ( PVR2, DISP_SIZE );

   244     int dispmode = MMIO_READ( PVR2, DISP_MODE );

   245     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );

   246     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;

   247     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;

   248     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;

   249     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;

   250     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);

   251     video_buffer_t buffer = &video_buffer[video_buffer_idx];

   252     video_buffer_idx = !video_buffer_idx;

   253     video_buffer_t last = &video_buffer[video_buffer_idx];

   254     buffer->rowstride = (vid_ppl + vid_stride) << 2;

   255     buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );

   256     buffer->vres = vid_lpf;

   257     if( interlaced ) buffer->vres <<= 1;

   258     switch( (dispmode & DISPMODE_COL) >> 2 ) {

   259     case 0:

   260 	buffer->colour_format = COLFMT_ARGB1555;

   261 	buffer->hres = vid_ppl << 1;

   262 	break;

   263     case 1:

   264 	buffer->colour_format = COLFMT_RGB565;

   265 	buffer->hres = vid_ppl << 1;

   266 	break;

   267     case 2:

   268 	buffer->colour_format = COLFMT_RGB888;

   269 	buffer->hres = (vid_ppl << 2) / 3;

   270 	break;

   271     case 3:

   272 	buffer->colour_format = COLFMT_ARGB8888;

   273 	buffer->hres = vid_ppl;

   274 	break;

   275     }

   277     if( buffer->hres <=8 )

   278 	buffer->hres = 640;

   279     if( buffer->vres <=8 )

   280 	buffer->vres = 480;

   281     if( display_driver != NULL ) {

   282 	if( buffer->hres != last->hres ||

   283 	    buffer->vres != last->vres ||

   284 	    buffer->colour_format != last->colour_format) {

   285 	    display_driver->set_display_format( buffer->hres, buffer->vres,

   286 						buffer->colour_format );

   287 	}

   288 	if( !bEnabled ) {

   289 	    display_driver->display_blank_frame( 0 );

   290 	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */

   291 	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );

   292 	    display_driver->display_blank_frame( colour );

   293 	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {

   294 	    display_driver->display_frame( buffer );

   295 	}

   296     }

   297     pvr2_state.frame_count++;

   298 }

   300 /**

   301  * This has to handle every single register individually as they all get masked

   302  * off differently (and its easier to do it at write time)

   303  */

   304 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )

   305 {

   306     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */

   307         MMIO_WRITE( PVR2, reg, val );

   308         return;

   309     }

   311     switch(reg) {

   312     case PVRID:

   313     case PVRVER:

   314     case GUNPOS: /* Read only registers */

   315 	break;

   316     case PVRRESET:

   317 	val &= 0x00000007; /* Do stuff? */

   318 	MMIO_WRITE( PVR2, reg, val );

   319 	break;

   320     case RENDER_START: /* Don't really care what value */

   321 	if( pvr2_state.save_next_render_filename != NULL ) {

   322 	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {

   323 		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);

   324 	    }

   325 	    g_free( pvr2_state.save_next_render_filename );

   326 	    pvr2_state.save_next_render_filename = NULL;

   327 	}

   328 	pvr2_render_scene();

   329 	break;

   330     case RENDER_POLYBASE:

   331     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );

   332     	break;

   333     case RENDER_TSPCFG:

   334     	MMIO_WRITE( PVR2, reg, val&0x00010101 );

   335     	break;

   336     case DISP_BORDER:

   337     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );

   338     	break;

   339     case DISP_MODE:

   340     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );

   341     	break;

   342     case RENDER_MODE:

   343     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );

   344     	break;

   345     case RENDER_SIZE:

   346     	MMIO_WRITE( PVR2, reg, val&0x000001FF );

   347     	break;

   348     case DISP_ADDR1:

   349 	val &= 0x00FFFFFC;

   350 	MMIO_WRITE( PVR2, reg, val );

   351 	pvr2_update_raster_posn(sh4r.slice_cycle);

   352 	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||

   353 	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {

   354 	    pvr2_display_frame();

   355 	}

   356 	break;

   357     case DISP_ADDR2:

   358     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   359     	break;

   360     case DISP_SIZE:

   361     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );

   362     	break;

   363     case RENDER_ADDR1:

   364     case RENDER_ADDR2:

   365     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );

   366     	break;

   367     case RENDER_HCLIP:

   368 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );

   369 	break;

   370     case RENDER_VCLIP:

   371 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   372 	break;

   373     case DISP_HPOSIRQ:

   374 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );

   375 	pvr2_state.irq_hpos_line = val & 0x03FF;

   376 	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;

   377 	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;

   378 	switch( pvr2_state.irq_hpos_mode ) {

   379 	case 3: /* Reserved - treat as 0 */

   380 	case 0: /* Once per frame at specified line */

   381 	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;

   382 	    break;

   383 	case 2: /* Once per line - as per-line-count */

   384 	    pvr2_state.irq_hpos_line = 1;

   385 	    pvr2_state.irq_hpos_mode = 1;

   386 	case 1: /* Once per N lines */

   387 	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;

   388 	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +

   389 		pvr2_state.irq_hpos_line_count;

   390 	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   391 		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   392 	    }

   393 	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;

   394 	}

   395 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   396 					  pvr2_state.irq_hpos_time_ns );

   397 	break;

   398     case DISP_VPOSIRQ:

   399 	val = val & 0x03FF03FF;

   400 	pvr2_state.irq_vpos1 = (val >> 16);

   401 	pvr2_state.irq_vpos2 = val & 0x03FF;

   402 	pvr2_update_raster_posn(sh4r.slice_cycle);

   403 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   404 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   405 	MMIO_WRITE( PVR2, reg, val );

   406 	break;

   407     case RENDER_NEARCLIP:

   408 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );

   409 	break;

   410     case RENDER_SHADOW:

   411 	MMIO_WRITE( PVR2, reg, val&0x000001FF );

   412 	break;

   413     case RENDER_OBJCFG:

   414     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   415     	break;

   416     case RENDER_TSPCLIP:

   417     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );

   418     	break;

   419     case RENDER_FARCLIP:

   420 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );

   421 	break;

   422     case RENDER_BGPLANE:

   423     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   424     	break;

   425     case RENDER_ISPCFG:

   426     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );

   427     	break;

   428     case VRAM_CFG1:

   429 	MMIO_WRITE( PVR2, reg, val&0x000000FF );

   430 	break;

   431     case VRAM_CFG2:

   432 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   433 	break;

   434     case VRAM_CFG3:

   435 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   436 	break;

   437     case RENDER_FOGTBLCOL:

   438     case RENDER_FOGVRTCOL:

   439 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );

   440 	break;

   441     case RENDER_FOGCOEFF:

   442 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   443 	break;

   444     case RENDER_CLAMPHI:

   445     case RENDER_CLAMPLO:

   446 	MMIO_WRITE( PVR2, reg, val );

   447 	break;

   448     case RENDER_TEXSIZE:

   449 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );

   450 	break;

   451     case RENDER_PALETTE:

   452 	MMIO_WRITE( PVR2, reg, val&0x00000003 );

   453 	break;

   455 	/********** CRTC registers *************/

   456     case DISP_HBORDER:

   457     case DISP_VBORDER:

   458 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   459 	break;

   460     case DISP_TOTAL:

   461 	val = val & 0x03FF03FF;

   462 	MMIO_WRITE( PVR2, reg, val );

   463 	pvr2_update_raster_posn(sh4r.slice_cycle);

   464 	pvr2_state.total_lines = (val >> 16) + 1;

   465 	pvr2_state.line_size = (val & 0x03FF) + 1;

   466 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;

   467 	pvr2_state.retrace_end_line = 0x2A;

   468 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;

   469 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   470 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   471 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   472 					  pvr2_state.irq_hpos_time_ns );

   473 	break;

   474     case DISP_SYNCCFG:

   475 	MMIO_WRITE( PVR2, reg, val&0x000003FF );

   476 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;

   477 	break;

   478     case DISP_SYNCTIME:

   479 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;

   480 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;

   481 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );

   482 	break;

   483     case DISP_CFG2:

   484 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );

   485 	break;

   486     case DISP_HPOS:

   487 	val = val & 0x03FF;

   488 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;

   489 	MMIO_WRITE( PVR2, reg, val );

   490 	break;

   491     case DISP_VPOS:

   492 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   493 	break;

   495 	/*********** Tile accelerator registers ***********/

   496     case TA_POLYPOS:

   497     case TA_LISTPOS:

   498 	/* Readonly registers */

   499 	break;

   500     case TA_TILEBASE:

   501     case TA_LISTEND:

   502     case TA_LISTBASE:

   503 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );

   504 	break;

   505     case RENDER_TILEBASE:

   506     case TA_POLYBASE:

   507     case TA_POLYEND:

   508 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   509 	break;

   510     case TA_TILESIZE:

   511 	MMIO_WRITE( PVR2, reg, val&0x000F003F );

   512 	break;

   513     case TA_TILECFG:

   514 	MMIO_WRITE( PVR2, reg, val&0x00133333 );

   515 	break;

   516     case TA_INIT:

   517 	if( val & 0x80000000 )

   518 	    pvr2_ta_init();

   519 	break;

   520     case TA_REINIT:

   521 	break;

   522 	/**************** Scaler registers? ****************/

   523     case SCALERCFG:

   524 	/* KOS suggests bits as follows:

   525 	 *   0: enable vertical scaling

   526 	 *  10: ???

   527 	 *  16: enable FSAA

   528 	 */

   529 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );

   530 	break;

   532     case YUV_ADDR:

   533 	val = val & 0x00FFFFF8;

   534 	MMIO_WRITE( PVR2, reg, val );

   535 	pvr2_yuv_init( val );

   536 	break;

   537     case YUV_CFG:

   538 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );

   539 	pvr2_yuv_set_config(val);

   540 	break;

   542 	/**************** Unknowns ***************/

   543     case PVRUNK1:

   544     	MMIO_WRITE( PVR2, reg, val&0x000007FF );

   545     	break;

   546     case PVRUNK2:

   547 	MMIO_WRITE( PVR2, reg, val&0x00000007 );

   548 	break;

   549     case PVRUNK3:

   550 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );

   551 	break;

   552     case PVRUNK5:

   553 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   554 	break;

   555     case PVRUNK6:

   556 	MMIO_WRITE( PVR2, reg, val&0x000000FF );

   557 	break;

   558     case PVRUNK7:

   559 	MMIO_WRITE( PVR2, reg, val&0x00000001 );

   560 	break;

   561     }

   562 }

   564 /**

   565  * Calculate the current read value of the syncstat register, using

   566  * the current SH4 clock time as an offset from the last timeslice.

   567  * The register reads (LSB to MSB) as:

   568  *     0..9  Current scan line

   569  *     10    Odd/even field (1 = odd, 0 = even)

   570  *     11    Display active (including border and overscan)

   571  *     12    Horizontal sync off

   572  *     13    Vertical sync off

   573  * Note this method is probably incorrect for anything other than straight

   574  * interlaced PAL/NTSC, and needs further testing.

   575  */

   576 uint32_t pvr2_get_sync_status()

   577 {

   578     pvr2_update_raster_posn(sh4r.slice_cycle);

   579     uint32_t result = pvr2_state.line_count;

   581     if( pvr2_state.odd_even_field ) {

   582 	result |= 0x0400;

   583     }

   584     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {

   585 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {

   586 	    result |= 0x1000; /* !HSYNC */

   587 	}

   588 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   589 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {

   590 		result |= 0x2800; /* Display active */

   591 	    } else {

   592 		result |= 0x2000; /* Front porch */

   593 	    }

   594 	}

   595     } else {

   596 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   597 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {

   598 		result |= 0x3800; /* Display active */

   599 	    } else {

   600 		result |= 0x3000;

   601 	    }

   602 	} else {

   603 	    result |= 0x1000; /* Back porch */

   604 	}

   605     }

   606     return result;

   607 }

   609 /**

   610  * Schedule a "scanline" event. This actually goes off at

   611  * 2 * line in even fields and 2 * line + 1 in odd fields.

   612  * Otherwise this behaves as per pvr2_schedule_line_event().

   613  * The raster position should be updated before calling this

   614  * method.

   615  * @param eventid Event to fire at the specified time

   616  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced

   617  *  displays).

   618  * @param hpos_ns Nanoseconds into the line at which to fire.

   619  */

   620 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )

   621 {

   622     uint32_t field = pvr2_state.odd_even_field;

   623     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {

   624 	field = !field;

   625     }

   626     if( hpos_ns > pvr2_state.line_time_ns ) {

   627 	hpos_ns = pvr2_state.line_time_ns;

   628     }

   630     line <<= 1;

   631     if( field ) {

   632 	line += 1;

   633     }

   635     if( line < pvr2_state.total_lines ) {

   636 	uint32_t lines;

   637 	uint32_t time;

   638 	if( line <= pvr2_state.line_count ) {

   639 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);

   640 	} else {

   641 	    lines = (line - pvr2_state.line_count);

   642 	}

   643 	if( lines <= minimum_lines ) {

   644 	    lines += pvr2_state.total_lines;

   645 	}

   646 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;

   647 	event_schedule( eventid, time );

   648     } else {

   649 	event_cancel( eventid );

   650     }

   651 }

   653 MMIO_REGION_READ_FN( PVR2, reg )

   654 {

   655     switch( reg ) {

   656         case DISP_SYNCSTAT:

   657             return pvr2_get_sync_status();

   658         default:

   659             return MMIO_READ( PVR2, reg );

   660     }

   661 }

   663 MMIO_REGION_DEFFNS( PVR2PAL )

   665 void pvr2_set_base_address( uint32_t base )

   666 {

   667     mmio_region_PVR2_write( DISP_ADDR1, base );

   668 }

   673 int32_t mmio_region_PVR2TA_read( uint32_t reg )

   674 {

   675     return 0xFFFFFFFF;

   676 }

   678 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )

   679 {

   680     pvr2_ta_write( (char *)&val, sizeof(uint32_t) );

   681 }