filename | src/sh4/sh4stat.c |
changeset | 387:38e9fddbf0e3 |
next | 500:848e66eee418 |
author | nkeynes |
date | Sat Sep 29 05:33:02 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Modify termination again to allow early exit (eg on end-of-page), as well as allowing follow through on conditional branches if desired. |
view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4stat.c,v 1.1 2007-09-18 08:58:23 nkeynes Exp $
3 *
4 * Support module for collecting instruction stats
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #include "dream.h"
20 #include "sh4stat.h"
21 #include "sh4core.h"
23 static uint64_t sh4_stats[SH4_INSTRUCTION_COUNT+1];
24 static uint64_t sh4_stats_total;
25 static const char *sh4_stats_names[] = {
26 "???",
27 "ADD Rm, Rn",
28 "ADD #imm, Rn",
29 "ADDC Rm, Rn",
30 "ADDV Rm, Rn",
31 "AND Rm, Rn",
32 "AND #imm, R0",
33 "AND.B #imm, @(R0, GBR)",
34 "BF disp",
35 "BF/S disp",
36 "BRA disp",
37 "BRAF Rn",
38 "BSR disp",
39 "BSRF Rn",
40 "BT disp",
41 "BT/S disp",
42 "CLRMAC",
43 "CLRS",
44 "CLRT",
45 "CMP/EQ Rm, Rn",
46 "CMP/EQ #imm, R0",
47 "CMP/GE Rm, Rn",
48 "CMP/GT Rm, Rn",
49 "CMP/HI Rm, Rn",
50 "CMP/HS Rm, Rn",
51 "CMP/PL Rn",
52 "CMP/PZ Rn",
53 "CMP/STR Rm, Rn",
54 "DIV0S Rm, Rn",
55 "DIV0U",
56 "DIV1 Rm, Rn",
57 "DMULS.L Rm, Rn",
58 "DMULU.L Rm, Rn",
59 "DT Rn",
60 "EXTS.B Rm, Rn",
61 "EXTS.W Rm, Rn",
62 "EXTU.B Rm, Rn",
63 "EXTU.W Rm, Rn",
64 "FABS FRn",
65 "FADD FRm, FRn",
66 "FCMP/EQ FRm, FRn",
67 "FCMP/GT FRm, FRn",
68 "FCNVDS FRm, FPUL",
69 "FCNVSD FPUL, FRn",
70 "FDIV FRm, FRn",
71 "FIPR FVm, FVn",
72 "FLDS FRm, FPUL",
73 "FLDI0 FRn",
74 "FLDI1 FRn",
75 "FLOAT FPUL, FRn",
76 "FMAC FR0, FRm, FRn",
77 "FMOV FRm, FRn",
78 "FMOV FRm, @Rn",
79 "FMOV FRm, @-Rn",
80 "FMOV FRm, @(R0, Rn)",
81 "FMOV @Rm, FRn",
82 "FMOV @Rm+, FRn",
83 "FMOV @(R0, Rm), FRn",
84 "FMUL FRm, FRn",
85 "FNEG FRn",
86 "FRCHG",
87 "FSCA FPUL, FRn",
88 "FSCHG",
89 "FSQRT FRn",
90 "FSRRA FRn",
91 "FSTS FPUL, FRn",
92 "FSUB FRm, FRn",
93 "FTRC FRm, FPUL",
94 "FTRV XMTRX, FVn",
95 "JMP @Rn",
96 "JSR @Rn",
97 "LDC Rm, SR",
98 "LDC Rm, *",
99 "LDC.L @Rm+, SR",
100 "LDC.L @Rm+, *",
101 "LDS Rm, *",
102 "LDS.L @Rm+, *",
103 "LDTLB",
104 "MAC.L @Rm+, @Rn+",
105 "MAC.W @Rm+, @Rn+",
106 "MOV Rm, Rn",
107 "MOV #imm, Rn",
108 "MOV.B ...",
109 "MOV.L ...",
110 "MOV.L @(disp, PC)",
111 "MOV.W ...",
112 "MOVA @(disp, PC), R0",
113 "MOVCA.L R0, @Rn",
114 "MOVT Rn",
115 "MUL.L Rm, Rn",
116 "MULS.W Rm, Rn",
117 "MULU.W Rm, Rn",
118 "NEG Rm, Rn",
119 "NEGC Rm, Rn",
120 "NOP",
121 "NOT Rm, Rn",
122 "OCBI @Rn",
123 "OCBP @Rn",
124 "OCBWB @Rn",
125 "OR Rm, Rn",
126 "OR #imm, R0",
127 "OR.B #imm, @(R0, GBR)",
128 "PREF @Rn",
129 "ROTCL Rn",
130 "ROTCR Rn",
131 "ROTL Rn",
132 "ROTR Rn",
133 "RTE",
134 "RTS",
135 "SETS",
136 "SETT",
137 "SHAD Rm, Rn",
138 "SHAL Rn",
139 "SHAR Rn",
140 "SHLD Rm, Rn",
141 "SHLL* Rn",
142 "SHLR* Rn",
143 "SLEEP",
144 "STC SR, Rn",
145 "STC *, Rn",
146 "STC.L SR, @-Rn",
147 "STC.L *, @-Rn",
148 "STS *, Rn",
149 "STS.L *, @-Rn",
150 "SUB Rm, Rn",
151 "SUBC Rm, Rn",
152 "SUBV Rm, Rn",
153 "SWAP.B Rm, Rn",
154 "SWAP.W Rm, Rn",
155 "TAS.B @Rn",
156 "TRAPA #imm",
157 "TST Rm, Rn",
158 "TST #imm, R0",
159 "TST.B #imm, @(R0, GBR)",
160 "XOR Rm, Rn",
161 "XOR #imm, R0",
162 "XOR.B #imm, @(R0, GBR)",
163 "XTRCT Rm, Rn",
164 "UNDEF"
165 };
167 void sh4_stats_reset( void )
168 {
169 int i;
170 for( i=0; i<= I_UNDEF; i++ ) {
171 sh4_stats[i] = 0;
172 }
173 sh4_stats_total = 0;
174 }
176 void sh4_stats_print( FILE *out )
177 {
178 int i;
179 for( i=0; i<= I_UNDEF; i++ ) {
180 fprintf( out, "%-20s\t%d\t%.2f%\n", sh4_stats_names[i], (uint32_t)sh4_stats[i], ((double)sh4_stats[i])*100.0/(double)sh4_stats_total );
181 }
182 fprintf( out, "Total: %d\n", sh4_stats_total );
183 }
185 void sh4_stats_add( uint32_t pc )
186 {
187 uint16_t ir = sh4_read_word(pc);
188 #define UNDEF() sh4_stats[0]++
189 switch( (ir&0xF000) >> 12 ) {
190 case 0x0:
191 switch( ir&0xF ) {
192 case 0x2:
193 switch( (ir&0x80) >> 7 ) {
194 case 0x0:
195 switch( (ir&0x70) >> 4 ) {
196 case 0x0:
197 { /* STC SR, Rn */
198 uint32_t Rn = ((ir>>8)&0xF);
199 sh4_stats[I_STCSR]++;
200 }
201 break;
202 case 0x1:
203 { /* STC GBR, Rn */
204 uint32_t Rn = ((ir>>8)&0xF);
205 sh4_stats[I_STC]++;
206 }
207 break;
208 case 0x2:
209 { /* STC VBR, Rn */
210 uint32_t Rn = ((ir>>8)&0xF);
211 sh4_stats[I_STC]++;
212 }
213 break;
214 case 0x3:
215 { /* STC SSR, Rn */
216 uint32_t Rn = ((ir>>8)&0xF);
217 sh4_stats[I_STC]++;
218 }
219 break;
220 case 0x4:
221 { /* STC SPC, Rn */
222 uint32_t Rn = ((ir>>8)&0xF);
223 sh4_stats[I_STC]++;
224 }
225 break;
226 default:
227 UNDEF();
228 break;
229 }
230 break;
231 case 0x1:
232 { /* STC Rm_BANK, Rn */
233 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
234 sh4_stats[I_STC]++;
235 }
236 break;
237 }
238 break;
239 case 0x3:
240 switch( (ir&0xF0) >> 4 ) {
241 case 0x0:
242 { /* BSRF Rn */
243 uint32_t Rn = ((ir>>8)&0xF);
244 sh4_stats[I_BSRF]++;
245 }
246 break;
247 case 0x2:
248 { /* BRAF Rn */
249 uint32_t Rn = ((ir>>8)&0xF);
250 sh4_stats[I_BRAF]++;
251 }
252 break;
253 case 0x8:
254 { /* PREF @Rn */
255 uint32_t Rn = ((ir>>8)&0xF);
256 sh4_stats[I_PREF]++;
257 }
258 break;
259 case 0x9:
260 { /* OCBI @Rn */
261 uint32_t Rn = ((ir>>8)&0xF);
262 sh4_stats[I_OCBI]++;
263 }
264 break;
265 case 0xA:
266 { /* OCBP @Rn */
267 uint32_t Rn = ((ir>>8)&0xF);
268 sh4_stats[I_OCBP]++;
269 }
270 break;
271 case 0xB:
272 { /* OCBWB @Rn */
273 uint32_t Rn = ((ir>>8)&0xF);
274 sh4_stats[I_OCBWB]++;
275 }
276 break;
277 case 0xC:
278 { /* MOVCA.L R0, @Rn */
279 uint32_t Rn = ((ir>>8)&0xF);
280 sh4_stats[I_MOVCA]++;
281 }
282 break;
283 default:
284 UNDEF();
285 break;
286 }
287 break;
288 case 0x4:
289 { /* MOV.B Rm, @(R0, Rn) */
290 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
291 sh4_stats[I_MOVB]++;
292 }
293 break;
294 case 0x5:
295 { /* MOV.W Rm, @(R0, Rn) */
296 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
297 sh4_stats[I_MOVW]++;
298 }
299 break;
300 case 0x6:
301 { /* MOV.L Rm, @(R0, Rn) */
302 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
303 sh4_stats[I_MOVL]++;
304 }
305 break;
306 case 0x7:
307 { /* MUL.L Rm, Rn */
308 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
309 sh4_stats[I_MULL]++;
310 }
311 break;
312 case 0x8:
313 switch( (ir&0xFF0) >> 4 ) {
314 case 0x0:
315 { /* CLRT */
316 sh4_stats[I_CLRT]++;
317 }
318 break;
319 case 0x1:
320 { /* SETT */
321 sh4_stats[I_SETT]++;
322 }
323 break;
324 case 0x2:
325 { /* CLRMAC */
326 sh4_stats[I_CLRMAC]++;
327 }
328 break;
329 case 0x3:
330 { /* LDTLB */
331 sh4_stats[I_LDTLB]++;
332 }
333 break;
334 case 0x4:
335 { /* CLRS */
336 sh4_stats[I_CLRS]++;
337 }
338 break;
339 case 0x5:
340 { /* SETS */
341 sh4_stats[I_SETS]++;
342 }
343 break;
344 default:
345 UNDEF();
346 break;
347 }
348 break;
349 case 0x9:
350 switch( (ir&0xF0) >> 4 ) {
351 case 0x0:
352 { /* NOP */
353 sh4_stats[I_NOP]++;
354 }
355 break;
356 case 0x1:
357 { /* DIV0U */
358 sh4_stats[I_DIV0U]++;
359 }
360 break;
361 case 0x2:
362 { /* MOVT Rn */
363 uint32_t Rn = ((ir>>8)&0xF);
364 sh4_stats[I_MOVT]++;
365 }
366 break;
367 default:
368 UNDEF();
369 break;
370 }
371 break;
372 case 0xA:
373 switch( (ir&0xF0) >> 4 ) {
374 case 0x0:
375 { /* STS MACH, Rn */
376 uint32_t Rn = ((ir>>8)&0xF);
377 sh4_stats[I_STS]++;
378 }
379 break;
380 case 0x1:
381 { /* STS MACL, Rn */
382 uint32_t Rn = ((ir>>8)&0xF);
383 sh4_stats[I_STS]++;
384 }
385 break;
386 case 0x2:
387 { /* STS PR, Rn */
388 uint32_t Rn = ((ir>>8)&0xF);
389 sh4_stats[I_STS]++;
390 }
391 break;
392 case 0x3:
393 { /* STC SGR, Rn */
394 uint32_t Rn = ((ir>>8)&0xF);
395 sh4_stats[I_STC]++;
396 }
397 break;
398 case 0x5:
399 { /* STS FPUL, Rn */
400 uint32_t Rn = ((ir>>8)&0xF);
401 sh4_stats[I_STS]++;
402 }
403 break;
404 case 0x6:
405 { /* STS FPSCR, Rn */
406 uint32_t Rn = ((ir>>8)&0xF);
407 sh4_stats[I_STS]++;
408 }
409 break;
410 case 0xF:
411 { /* STC DBR, Rn */
412 uint32_t Rn = ((ir>>8)&0xF);
413 sh4_stats[I_STC]++;
414 }
415 break;
416 default:
417 UNDEF();
418 break;
419 }
420 break;
421 case 0xB:
422 switch( (ir&0xFF0) >> 4 ) {
423 case 0x0:
424 { /* RTS */
425 sh4_stats[I_RTS]++;
426 }
427 break;
428 case 0x1:
429 { /* SLEEP */
430 sh4_stats[I_SLEEP]++;
431 }
432 break;
433 case 0x2:
434 { /* RTE */
435 sh4_stats[I_RTE]++;
436 }
437 break;
438 default:
439 UNDEF();
440 break;
441 }
442 break;
443 case 0xC:
444 { /* MOV.B @(R0, Rm), Rn */
445 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
446 sh4_stats[I_MOVB]++;
447 }
448 break;
449 case 0xD:
450 { /* MOV.W @(R0, Rm), Rn */
451 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
452 sh4_stats[I_MOVW]++;
453 }
454 break;
455 case 0xE:
456 { /* MOV.L @(R0, Rm), Rn */
457 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
458 sh4_stats[I_MOVL]++;
459 }
460 break;
461 case 0xF:
462 { /* MAC.L @Rm+, @Rn+ */
463 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
464 sh4_stats[I_MACL]++;
465 }
466 break;
467 default:
468 UNDEF();
469 break;
470 }
471 break;
472 case 0x1:
473 { /* MOV.L Rm, @(disp, Rn) */
474 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
475 sh4_stats[I_MOVL]++;
476 }
477 break;
478 case 0x2:
479 switch( ir&0xF ) {
480 case 0x0:
481 { /* MOV.B Rm, @Rn */
482 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
483 sh4_stats[I_MOVB]++;
484 }
485 break;
486 case 0x1:
487 { /* MOV.W Rm, @Rn */
488 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
489 sh4_stats[I_MOVW]++;
490 }
491 break;
492 case 0x2:
493 { /* MOV.L Rm, @Rn */
494 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
495 sh4_stats[I_MOVL]++;
496 }
497 break;
498 case 0x4:
499 { /* MOV.B Rm, @-Rn */
500 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
501 sh4_stats[I_MOVB]++;
502 }
503 break;
504 case 0x5:
505 { /* MOV.W Rm, @-Rn */
506 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
507 sh4_stats[I_MOVW]++;
508 }
509 break;
510 case 0x6:
511 { /* MOV.L Rm, @-Rn */
512 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
513 sh4_stats[I_MOVL]++;
514 }
515 break;
516 case 0x7:
517 { /* DIV0S Rm, Rn */
518 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
519 sh4_stats[I_DIV0S]++;
520 }
521 break;
522 case 0x8:
523 { /* TST Rm, Rn */
524 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
525 sh4_stats[I_TST]++;
526 }
527 break;
528 case 0x9:
529 { /* AND Rm, Rn */
530 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
531 sh4_stats[I_AND]++;
532 }
533 break;
534 case 0xA:
535 { /* XOR Rm, Rn */
536 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
537 sh4_stats[I_XOR]++;
538 }
539 break;
540 case 0xB:
541 { /* OR Rm, Rn */
542 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
543 sh4_stats[I_OR]++;
544 }
545 break;
546 case 0xC:
547 { /* CMP/STR Rm, Rn */
548 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
549 sh4_stats[I_CMPSTR]++;
550 }
551 break;
552 case 0xD:
553 { /* XTRCT Rm, Rn */
554 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
555 sh4_stats[I_XTRCT]++;
556 }
557 break;
558 case 0xE:
559 { /* MULU.W Rm, Rn */
560 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
561 sh4_stats[I_MULUW]++;
562 }
563 break;
564 case 0xF:
565 { /* MULS.W Rm, Rn */
566 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
567 sh4_stats[I_MULSW]++;
568 }
569 break;
570 default:
571 UNDEF();
572 break;
573 }
574 break;
575 case 0x3:
576 switch( ir&0xF ) {
577 case 0x0:
578 { /* CMP/EQ Rm, Rn */
579 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
580 sh4_stats[I_CMPEQ]++;
581 }
582 break;
583 case 0x2:
584 { /* CMP/HS Rm, Rn */
585 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
586 sh4_stats[I_CMPHS]++;
587 }
588 break;
589 case 0x3:
590 { /* CMP/GE Rm, Rn */
591 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
592 sh4_stats[I_CMPGE]++;
593 }
594 break;
595 case 0x4:
596 { /* DIV1 Rm, Rn */
597 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
598 sh4_stats[I_DIV1]++;
599 }
600 break;
601 case 0x5:
602 { /* DMULU.L Rm, Rn */
603 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
604 sh4_stats[I_DMULU]++;
605 }
606 break;
607 case 0x6:
608 { /* CMP/HI Rm, Rn */
609 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
610 sh4_stats[I_CMPHI]++;
611 }
612 break;
613 case 0x7:
614 { /* CMP/GT Rm, Rn */
615 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
616 sh4_stats[I_CMPGT]++;
617 }
618 break;
619 case 0x8:
620 { /* SUB Rm, Rn */
621 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
622 sh4_stats[I_SUB]++;
623 }
624 break;
625 case 0xA:
626 { /* SUBC Rm, Rn */
627 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
628 sh4_stats[I_SUBC]++;
629 }
630 break;
631 case 0xB:
632 { /* SUBV Rm, Rn */
633 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
634 sh4_stats[I_SUBV]++;
635 }
636 break;
637 case 0xC:
638 { /* ADD Rm, Rn */
639 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
640 sh4_stats[I_ADD]++;
641 }
642 break;
643 case 0xD:
644 { /* DMULS.L Rm, Rn */
645 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
646 sh4_stats[I_DMULS]++;
647 }
648 break;
649 case 0xE:
650 { /* ADDC Rm, Rn */
651 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
652 sh4_stats[I_ADDC]++;
653 }
654 break;
655 case 0xF:
656 { /* ADDV Rm, Rn */
657 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
658 sh4_stats[I_ADDV]++;
659 }
660 break;
661 default:
662 UNDEF();
663 break;
664 }
665 break;
666 case 0x4:
667 switch( ir&0xF ) {
668 case 0x0:
669 switch( (ir&0xF0) >> 4 ) {
670 case 0x0:
671 { /* SHLL Rn */
672 uint32_t Rn = ((ir>>8)&0xF);
673 sh4_stats[I_SHLL]++;
674 }
675 break;
676 case 0x1:
677 { /* DT Rn */
678 uint32_t Rn = ((ir>>8)&0xF);
679 sh4_stats[I_DT]++;
680 }
681 break;
682 case 0x2:
683 { /* SHAL Rn */
684 uint32_t Rn = ((ir>>8)&0xF);
685 sh4_stats[I_SHAL]++;
686 }
687 break;
688 default:
689 UNDEF();
690 break;
691 }
692 break;
693 case 0x1:
694 switch( (ir&0xF0) >> 4 ) {
695 case 0x0:
696 { /* SHLR Rn */
697 uint32_t Rn = ((ir>>8)&0xF);
698 sh4_stats[I_SHLR]++;
699 }
700 break;
701 case 0x1:
702 { /* CMP/PZ Rn */
703 uint32_t Rn = ((ir>>8)&0xF);
704 sh4_stats[I_CMPPZ]++;
705 }
706 break;
707 case 0x2:
708 { /* SHAR Rn */
709 uint32_t Rn = ((ir>>8)&0xF);
710 sh4_stats[I_SHAR]++;
711 }
712 break;
713 default:
714 UNDEF();
715 break;
716 }
717 break;
718 case 0x2:
719 switch( (ir&0xF0) >> 4 ) {
720 case 0x0:
721 { /* STS.L MACH, @-Rn */
722 uint32_t Rn = ((ir>>8)&0xF);
723 sh4_stats[I_STSM]++;
724 }
725 break;
726 case 0x1:
727 { /* STS.L MACL, @-Rn */
728 uint32_t Rn = ((ir>>8)&0xF);
729 sh4_stats[I_STSM]++;
730 }
731 break;
732 case 0x2:
733 { /* STS.L PR, @-Rn */
734 uint32_t Rn = ((ir>>8)&0xF);
735 sh4_stats[I_STSM]++;
736 }
737 break;
738 case 0x3:
739 { /* STC.L SGR, @-Rn */
740 uint32_t Rn = ((ir>>8)&0xF);
741 sh4_stats[I_STCM]++;
742 }
743 break;
744 case 0x5:
745 { /* STS.L FPUL, @-Rn */
746 uint32_t Rn = ((ir>>8)&0xF);
747 sh4_stats[I_STSM]++;
748 }
749 break;
750 case 0x6:
751 { /* STS.L FPSCR, @-Rn */
752 uint32_t Rn = ((ir>>8)&0xF);
753 sh4_stats[I_STSM]++;
754 }
755 break;
756 case 0xF:
757 { /* STC.L DBR, @-Rn */
758 uint32_t Rn = ((ir>>8)&0xF);
759 sh4_stats[I_STCM]++;
760 }
761 break;
762 default:
763 UNDEF();
764 break;
765 }
766 break;
767 case 0x3:
768 switch( (ir&0x80) >> 7 ) {
769 case 0x0:
770 switch( (ir&0x70) >> 4 ) {
771 case 0x0:
772 { /* STC.L SR, @-Rn */
773 uint32_t Rn = ((ir>>8)&0xF);
774 sh4_stats[I_STCSRM]++;
775 }
776 break;
777 case 0x1:
778 { /* STC.L GBR, @-Rn */
779 uint32_t Rn = ((ir>>8)&0xF);
780 sh4_stats[I_STCM]++;
781 }
782 break;
783 case 0x2:
784 { /* STC.L VBR, @-Rn */
785 uint32_t Rn = ((ir>>8)&0xF);
786 sh4_stats[I_STCM]++;
787 }
788 break;
789 case 0x3:
790 { /* STC.L SSR, @-Rn */
791 uint32_t Rn = ((ir>>8)&0xF);
792 sh4_stats[I_STCM]++;
793 }
794 break;
795 case 0x4:
796 { /* STC.L SPC, @-Rn */
797 uint32_t Rn = ((ir>>8)&0xF);
798 sh4_stats[I_STCM]++;
799 }
800 break;
801 default:
802 UNDEF();
803 break;
804 }
805 break;
806 case 0x1:
807 { /* STC.L Rm_BANK, @-Rn */
808 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
809 sh4_stats[I_STCM]++;
810 }
811 break;
812 }
813 break;
814 case 0x4:
815 switch( (ir&0xF0) >> 4 ) {
816 case 0x0:
817 { /* ROTL Rn */
818 uint32_t Rn = ((ir>>8)&0xF);
819 sh4_stats[I_ROTL]++;
820 }
821 break;
822 case 0x2:
823 { /* ROTCL Rn */
824 uint32_t Rn = ((ir>>8)&0xF);
825 sh4_stats[I_ROTCL]++;
826 }
827 break;
828 default:
829 UNDEF();
830 break;
831 }
832 break;
833 case 0x5:
834 switch( (ir&0xF0) >> 4 ) {
835 case 0x0:
836 { /* ROTR Rn */
837 uint32_t Rn = ((ir>>8)&0xF);
838 sh4_stats[I_ROTR]++;
839 }
840 break;
841 case 0x1:
842 { /* CMP/PL Rn */
843 uint32_t Rn = ((ir>>8)&0xF);
844 sh4_stats[I_CMPPL]++;
845 }
846 break;
847 case 0x2:
848 { /* ROTCR Rn */
849 uint32_t Rn = ((ir>>8)&0xF);
850 sh4_stats[I_ROTCR]++;
851 }
852 break;
853 default:
854 UNDEF();
855 break;
856 }
857 break;
858 case 0x6:
859 switch( (ir&0xF0) >> 4 ) {
860 case 0x0:
861 { /* LDS.L @Rm+, MACH */
862 uint32_t Rm = ((ir>>8)&0xF);
863 sh4_stats[I_LDSM]++;
864 }
865 break;
866 case 0x1:
867 { /* LDS.L @Rm+, MACL */
868 uint32_t Rm = ((ir>>8)&0xF);
869 sh4_stats[I_LDSM]++;
870 }
871 break;
872 case 0x2:
873 { /* LDS.L @Rm+, PR */
874 uint32_t Rm = ((ir>>8)&0xF);
875 sh4_stats[I_LDSM]++;
876 }
877 break;
878 case 0x3:
879 { /* LDC.L @Rm+, SGR */
880 uint32_t Rm = ((ir>>8)&0xF);
881 sh4_stats[I_LDCM]++;
882 }
883 break;
884 case 0x5:
885 { /* LDS.L @Rm+, FPUL */
886 uint32_t Rm = ((ir>>8)&0xF);
887 sh4_stats[I_LDSM]++;
888 }
889 break;
890 case 0x6:
891 { /* LDS.L @Rm+, FPSCR */
892 uint32_t Rm = ((ir>>8)&0xF);
893 sh4_stats[I_LDSM]++;
894 }
895 break;
896 case 0xF:
897 { /* LDC.L @Rm+, DBR */
898 uint32_t Rm = ((ir>>8)&0xF);
899 sh4_stats[I_LDCM]++;
900 }
901 break;
902 default:
903 UNDEF();
904 break;
905 }
906 break;
907 case 0x7:
908 switch( (ir&0x80) >> 7 ) {
909 case 0x0:
910 switch( (ir&0x70) >> 4 ) {
911 case 0x0:
912 { /* LDC.L @Rm+, SR */
913 uint32_t Rm = ((ir>>8)&0xF);
914 sh4_stats[I_LDCSRM]++;
915 }
916 break;
917 case 0x1:
918 { /* LDC.L @Rm+, GBR */
919 uint32_t Rm = ((ir>>8)&0xF);
920 sh4_stats[I_LDCM]++;
921 }
922 break;
923 case 0x2:
924 { /* LDC.L @Rm+, VBR */
925 uint32_t Rm = ((ir>>8)&0xF);
926 sh4_stats[I_LDCM]++;
927 }
928 break;
929 case 0x3:
930 { /* LDC.L @Rm+, SSR */
931 uint32_t Rm = ((ir>>8)&0xF);
932 sh4_stats[I_LDCM]++;
933 }
934 break;
935 case 0x4:
936 { /* LDC.L @Rm+, SPC */
937 uint32_t Rm = ((ir>>8)&0xF);
938 sh4_stats[I_LDCM]++;
939 }
940 break;
941 default:
942 UNDEF();
943 break;
944 }
945 break;
946 case 0x1:
947 { /* LDC.L @Rm+, Rn_BANK */
948 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
949 sh4_stats[I_LDCM]++;
950 }
951 break;
952 }
953 break;
954 case 0x8:
955 switch( (ir&0xF0) >> 4 ) {
956 case 0x0:
957 { /* SHLL2 Rn */
958 uint32_t Rn = ((ir>>8)&0xF);
959 sh4_stats[I_SHLL]++;
960 }
961 break;
962 case 0x1:
963 { /* SHLL8 Rn */
964 uint32_t Rn = ((ir>>8)&0xF);
965 sh4_stats[I_SHLL]++;
966 }
967 break;
968 case 0x2:
969 { /* SHLL16 Rn */
970 uint32_t Rn = ((ir>>8)&0xF);
971 sh4_stats[I_SHLL]++;
972 }
973 break;
974 default:
975 UNDEF();
976 break;
977 }
978 break;
979 case 0x9:
980 switch( (ir&0xF0) >> 4 ) {
981 case 0x0:
982 { /* SHLR2 Rn */
983 uint32_t Rn = ((ir>>8)&0xF);
984 sh4_stats[I_SHLR]++;
985 }
986 break;
987 case 0x1:
988 { /* SHLR8 Rn */
989 uint32_t Rn = ((ir>>8)&0xF);
990 sh4_stats[I_SHLR]++;
991 }
992 break;
993 case 0x2:
994 { /* SHLR16 Rn */
995 uint32_t Rn = ((ir>>8)&0xF);
996 sh4_stats[I_SHLR]++;
997 }
998 break;
999 default:
1000 UNDEF();
1001 break;
1002 }
1003 break;
1004 case 0xA:
1005 switch( (ir&0xF0) >> 4 ) {
1006 case 0x0:
1007 { /* LDS Rm, MACH */
1008 uint32_t Rm = ((ir>>8)&0xF);
1009 sh4_stats[I_LDS]++;
1010 }
1011 break;
1012 case 0x1:
1013 { /* LDS Rm, MACL */
1014 uint32_t Rm = ((ir>>8)&0xF);
1015 sh4_stats[I_LDS]++;
1016 }
1017 break;
1018 case 0x2:
1019 { /* LDS Rm, PR */
1020 uint32_t Rm = ((ir>>8)&0xF);
1021 sh4_stats[I_LDS]++;
1022 }
1023 break;
1024 case 0x3:
1025 { /* LDC Rm, SGR */
1026 uint32_t Rm = ((ir>>8)&0xF);
1027 sh4_stats[I_LDC]++;
1028 }
1029 break;
1030 case 0x5:
1031 { /* LDS Rm, FPUL */
1032 uint32_t Rm = ((ir>>8)&0xF);
1033 sh4_stats[I_LDS]++;
1034 }
1035 break;
1036 case 0x6:
1037 { /* LDS Rm, FPSCR */
1038 uint32_t Rm = ((ir>>8)&0xF);
1039 sh4_stats[I_LDS]++;
1040 }
1041 break;
1042 case 0xF:
1043 { /* LDC Rm, DBR */
1044 uint32_t Rm = ((ir>>8)&0xF);
1045 sh4_stats[I_LDC]++;
1046 }
1047 break;
1048 default:
1049 UNDEF();
1050 break;
1051 }
1052 break;
1053 case 0xB:
1054 switch( (ir&0xF0) >> 4 ) {
1055 case 0x0:
1056 { /* JSR @Rn */
1057 uint32_t Rn = ((ir>>8)&0xF);
1058 sh4_stats[I_JSR]++;
1059 }
1060 break;
1061 case 0x1:
1062 { /* TAS.B @Rn */
1063 uint32_t Rn = ((ir>>8)&0xF);
1064 sh4_stats[I_TASB]++;
1065 }
1066 break;
1067 case 0x2:
1068 { /* JMP @Rn */
1069 uint32_t Rn = ((ir>>8)&0xF);
1070 sh4_stats[I_JMP]++;
1071 }
1072 break;
1073 default:
1074 UNDEF();
1075 break;
1076 }
1077 break;
1078 case 0xC:
1079 { /* SHAD Rm, Rn */
1080 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1081 sh4_stats[I_SHAD]++;
1082 }
1083 break;
1084 case 0xD:
1085 { /* SHLD Rm, Rn */
1086 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1087 sh4_stats[I_SHLD]++;
1088 }
1089 break;
1090 case 0xE:
1091 switch( (ir&0x80) >> 7 ) {
1092 case 0x0:
1093 switch( (ir&0x70) >> 4 ) {
1094 case 0x0:
1095 { /* LDC Rm, SR */
1096 uint32_t Rm = ((ir>>8)&0xF);
1097 sh4_stats[I_LDCSR]++;
1098 }
1099 break;
1100 case 0x1:
1101 { /* LDC Rm, GBR */
1102 uint32_t Rm = ((ir>>8)&0xF);
1103 sh4_stats[I_LDC]++;
1104 }
1105 break;
1106 case 0x2:
1107 { /* LDC Rm, VBR */
1108 uint32_t Rm = ((ir>>8)&0xF);
1109 sh4_stats[I_LDC]++;
1110 }
1111 break;
1112 case 0x3:
1113 { /* LDC Rm, SSR */
1114 uint32_t Rm = ((ir>>8)&0xF);
1115 sh4_stats[I_LDC]++;
1116 }
1117 break;
1118 case 0x4:
1119 { /* LDC Rm, SPC */
1120 uint32_t Rm = ((ir>>8)&0xF);
1121 sh4_stats[I_LDC]++;
1122 }
1123 break;
1124 default:
1125 UNDEF();
1126 break;
1127 }
1128 break;
1129 case 0x1:
1130 { /* LDC Rm, Rn_BANK */
1131 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1132 sh4_stats[I_LDC]++;
1133 }
1134 break;
1135 }
1136 break;
1137 case 0xF:
1138 { /* MAC.W @Rm+, @Rn+ */
1139 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1140 sh4_stats[I_MACW]++;
1141 }
1142 break;
1143 }
1144 break;
1145 case 0x5:
1146 { /* MOV.L @(disp, Rm), Rn */
1147 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1148 sh4_stats[I_MOVL]++;
1149 }
1150 break;
1151 case 0x6:
1152 switch( ir&0xF ) {
1153 case 0x0:
1154 { /* MOV.B @Rm, Rn */
1155 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1156 sh4_stats[I_MOVB]++;
1157 }
1158 break;
1159 case 0x1:
1160 { /* MOV.W @Rm, Rn */
1161 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1162 sh4_stats[I_MOVW]++;
1163 }
1164 break;
1165 case 0x2:
1166 { /* MOV.L @Rm, Rn */
1167 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1168 sh4_stats[I_MOVL]++;
1169 }
1170 break;
1171 case 0x3:
1172 { /* MOV Rm, Rn */
1173 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1174 sh4_stats[I_MOV]++;
1175 }
1176 break;
1177 case 0x4:
1178 { /* MOV.B @Rm+, Rn */
1179 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1180 sh4_stats[I_MOVB]++;
1181 }
1182 break;
1183 case 0x5:
1184 { /* MOV.W @Rm+, Rn */
1185 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1186 sh4_stats[I_MOVW]++;
1187 }
1188 break;
1189 case 0x6:
1190 { /* MOV.L @Rm+, Rn */
1191 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1192 sh4_stats[I_MOVL]++;
1193 }
1194 break;
1195 case 0x7:
1196 { /* NOT Rm, Rn */
1197 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1198 sh4_stats[I_NOT]++;
1199 }
1200 break;
1201 case 0x8:
1202 { /* SWAP.B Rm, Rn */
1203 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1204 sh4_stats[I_SWAPB]++;
1205 }
1206 break;
1207 case 0x9:
1208 { /* SWAP.W Rm, Rn */
1209 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1210 sh4_stats[I_SWAPW]++;
1211 }
1212 break;
1213 case 0xA:
1214 { /* NEGC Rm, Rn */
1215 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1216 sh4_stats[I_NEGC]++;
1217 }
1218 break;
1219 case 0xB:
1220 { /* NEG Rm, Rn */
1221 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1222 sh4_stats[I_NEG]++;
1223 }
1224 break;
1225 case 0xC:
1226 { /* EXTU.B Rm, Rn */
1227 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1228 sh4_stats[I_EXTUB]++;
1229 }
1230 break;
1231 case 0xD:
1232 { /* EXTU.W Rm, Rn */
1233 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1234 sh4_stats[I_EXTUW]++;
1235 }
1236 break;
1237 case 0xE:
1238 { /* EXTS.B Rm, Rn */
1239 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1240 sh4_stats[I_EXTSB]++;
1241 }
1242 break;
1243 case 0xF:
1244 { /* EXTS.W Rm, Rn */
1245 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1246 sh4_stats[I_EXTSW]++;
1247 }
1248 break;
1249 }
1250 break;
1251 case 0x7:
1252 { /* ADD #imm, Rn */
1253 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1254 sh4_stats[I_ADDI]++;
1255 }
1256 break;
1257 case 0x8:
1258 switch( (ir&0xF00) >> 8 ) {
1259 case 0x0:
1260 { /* MOV.B R0, @(disp, Rn) */
1261 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1262 sh4_stats[I_MOVB]++;
1263 }
1264 break;
1265 case 0x1:
1266 { /* MOV.W R0, @(disp, Rn) */
1267 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1268 sh4_stats[I_MOVW]++;
1269 }
1270 break;
1271 case 0x4:
1272 { /* MOV.B @(disp, Rm), R0 */
1273 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1274 sh4_stats[I_MOVB]++;
1275 }
1276 break;
1277 case 0x5:
1278 { /* MOV.W @(disp, Rm), R0 */
1279 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1280 sh4_stats[I_MOVW]++;
1281 }
1282 break;
1283 case 0x8:
1284 { /* CMP/EQ #imm, R0 */
1285 int32_t imm = SIGNEXT8(ir&0xFF);
1286 sh4_stats[I_CMPEQI]++;
1287 }
1288 break;
1289 case 0x9:
1290 { /* BT disp */
1291 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1292 sh4_stats[I_BT]++;
1293 }
1294 break;
1295 case 0xB:
1296 { /* BF disp */
1297 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1298 sh4_stats[I_BF]++;
1299 }
1300 break;
1301 case 0xD:
1302 { /* BT/S disp */
1303 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1304 sh4_stats[I_BTS]++;
1305 }
1306 break;
1307 case 0xF:
1308 { /* BF/S disp */
1309 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1310 sh4_stats[I_BFS]++;
1311 }
1312 break;
1313 default:
1314 UNDEF();
1315 break;
1316 }
1317 break;
1318 case 0x9:
1319 { /* MOV.W @(disp, PC), Rn */
1320 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1321 sh4_stats[I_MOVW]++;
1322 }
1323 break;
1324 case 0xA:
1325 { /* BRA disp */
1326 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1327 sh4_stats[I_BRA]++;
1328 }
1329 break;
1330 case 0xB:
1331 { /* BSR disp */
1332 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1333 sh4_stats[I_BSR]++;
1334 }
1335 break;
1336 case 0xC:
1337 switch( (ir&0xF00) >> 8 ) {
1338 case 0x0:
1339 { /* MOV.B R0, @(disp, GBR) */
1340 uint32_t disp = (ir&0xFF);
1341 sh4_stats[I_MOVB]++;
1342 }
1343 break;
1344 case 0x1:
1345 { /* MOV.W R0, @(disp, GBR) */
1346 uint32_t disp = (ir&0xFF)<<1;
1347 sh4_stats[I_MOVW]++;
1348 }
1349 break;
1350 case 0x2:
1351 { /* MOV.L R0, @(disp, GBR) */
1352 uint32_t disp = (ir&0xFF)<<2;
1353 sh4_stats[I_MOVL]++;
1354 }
1355 break;
1356 case 0x3:
1357 { /* TRAPA #imm */
1358 uint32_t imm = (ir&0xFF);
1359 sh4_stats[I_TRAPA]++;
1360 }
1361 break;
1362 case 0x4:
1363 { /* MOV.B @(disp, GBR), R0 */
1364 uint32_t disp = (ir&0xFF);
1365 sh4_stats[I_MOVB]++;
1366 }
1367 break;
1368 case 0x5:
1369 { /* MOV.W @(disp, GBR), R0 */
1370 uint32_t disp = (ir&0xFF)<<1;
1371 sh4_stats[I_MOVW]++;
1372 }
1373 break;
1374 case 0x6:
1375 { /* MOV.L @(disp, GBR), R0 */
1376 uint32_t disp = (ir&0xFF)<<2;
1377 sh4_stats[I_MOVL]++;
1378 }
1379 break;
1380 case 0x7:
1381 { /* MOVA @(disp, PC), R0 */
1382 uint32_t disp = (ir&0xFF)<<2;
1383 sh4_stats[I_MOVA]++;
1384 }
1385 break;
1386 case 0x8:
1387 { /* TST #imm, R0 */
1388 uint32_t imm = (ir&0xFF);
1389 sh4_stats[I_TSTI]++;
1390 }
1391 break;
1392 case 0x9:
1393 { /* AND #imm, R0 */
1394 uint32_t imm = (ir&0xFF);
1395 sh4_stats[I_ANDI]++;
1396 }
1397 break;
1398 case 0xA:
1399 { /* XOR #imm, R0 */
1400 uint32_t imm = (ir&0xFF);
1401 sh4_stats[I_XORI]++;
1402 }
1403 break;
1404 case 0xB:
1405 { /* OR #imm, R0 */
1406 uint32_t imm = (ir&0xFF);
1407 sh4_stats[I_ORI]++;
1408 }
1409 break;
1410 case 0xC:
1411 { /* TST.B #imm, @(R0, GBR) */
1412 uint32_t imm = (ir&0xFF);
1413 sh4_stats[I_TSTB]++;
1414 }
1415 break;
1416 case 0xD:
1417 { /* AND.B #imm, @(R0, GBR) */
1418 uint32_t imm = (ir&0xFF);
1419 sh4_stats[I_ANDB]++;
1420 }
1421 break;
1422 case 0xE:
1423 { /* XOR.B #imm, @(R0, GBR) */
1424 uint32_t imm = (ir&0xFF);
1425 sh4_stats[I_XORB]++;
1426 }
1427 break;
1428 case 0xF:
1429 { /* OR.B #imm, @(R0, GBR) */
1430 uint32_t imm = (ir&0xFF);
1431 sh4_stats[I_ORB]++;
1432 }
1433 break;
1434 }
1435 break;
1436 case 0xD:
1437 { /* MOV.L @(disp, PC), Rn */
1438 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1439 sh4_stats[I_MOVLPC]++;
1440 }
1441 break;
1442 case 0xE:
1443 { /* MOV #imm, Rn */
1444 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1445 sh4_stats[I_MOVI]++;
1446 }
1447 break;
1448 case 0xF:
1449 switch( ir&0xF ) {
1450 case 0x0:
1451 { /* FADD FRm, FRn */
1452 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1453 sh4_stats[I_FADD]++;
1454 }
1455 break;
1456 case 0x1:
1457 { /* FSUB FRm, FRn */
1458 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1459 sh4_stats[I_FSUB]++;
1460 }
1461 break;
1462 case 0x2:
1463 { /* FMUL FRm, FRn */
1464 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1465 sh4_stats[I_FMUL]++;
1466 }
1467 break;
1468 case 0x3:
1469 { /* FDIV FRm, FRn */
1470 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1471 sh4_stats[I_FDIV]++;
1472 }
1473 break;
1474 case 0x4:
1475 { /* FCMP/EQ FRm, FRn */
1476 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1477 sh4_stats[I_FCMPEQ]++;
1478 }
1479 break;
1480 case 0x5:
1481 { /* FCMP/GT FRm, FRn */
1482 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1483 sh4_stats[I_FCMPGT]++;
1484 }
1485 break;
1486 case 0x6:
1487 { /* FMOV @(R0, Rm), FRn */
1488 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1489 sh4_stats[I_FMOV7]++;
1490 }
1491 break;
1492 case 0x7:
1493 { /* FMOV FRm, @(R0, Rn) */
1494 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1495 sh4_stats[I_FMOV4]++;
1496 }
1497 break;
1498 case 0x8:
1499 { /* FMOV @Rm, FRn */
1500 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1501 sh4_stats[I_FMOV5]++;
1502 }
1503 break;
1504 case 0x9:
1505 { /* FMOV @Rm+, FRn */
1506 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1507 sh4_stats[I_FMOV6]++;
1508 }
1509 break;
1510 case 0xA:
1511 { /* FMOV FRm, @Rn */
1512 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1513 sh4_stats[I_FMOV2]++;
1514 }
1515 break;
1516 case 0xB:
1517 { /* FMOV FRm, @-Rn */
1518 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1519 sh4_stats[I_FMOV3]++;
1520 }
1521 break;
1522 case 0xC:
1523 { /* FMOV FRm, FRn */
1524 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1525 sh4_stats[I_FMOV1]++;
1526 }
1527 break;
1528 case 0xD:
1529 switch( (ir&0xF0) >> 4 ) {
1530 case 0x0:
1531 { /* FSTS FPUL, FRn */
1532 uint32_t FRn = ((ir>>8)&0xF);
1533 sh4_stats[I_FSTS]++;
1534 }
1535 break;
1536 case 0x1:
1537 { /* FLDS FRm, FPUL */
1538 uint32_t FRm = ((ir>>8)&0xF);
1539 sh4_stats[I_FLDS]++;
1540 }
1541 break;
1542 case 0x2:
1543 { /* FLOAT FPUL, FRn */
1544 uint32_t FRn = ((ir>>8)&0xF);
1545 sh4_stats[I_FLOAT]++;
1546 }
1547 break;
1548 case 0x3:
1549 { /* FTRC FRm, FPUL */
1550 uint32_t FRm = ((ir>>8)&0xF);
1551 sh4_stats[I_FTRC]++;
1552 }
1553 break;
1554 case 0x4:
1555 { /* FNEG FRn */
1556 uint32_t FRn = ((ir>>8)&0xF);
1557 sh4_stats[I_FNEG]++;
1558 }
1559 break;
1560 case 0x5:
1561 { /* FABS FRn */
1562 uint32_t FRn = ((ir>>8)&0xF);
1563 sh4_stats[I_FABS]++;
1564 }
1565 break;
1566 case 0x6:
1567 { /* FSQRT FRn */
1568 uint32_t FRn = ((ir>>8)&0xF);
1569 sh4_stats[I_FSQRT]++;
1570 }
1571 break;
1572 case 0x7:
1573 { /* FSRRA FRn */
1574 uint32_t FRn = ((ir>>8)&0xF);
1575 sh4_stats[I_FSRRA]++;
1576 }
1577 break;
1578 case 0x8:
1579 { /* FLDI0 FRn */
1580 uint32_t FRn = ((ir>>8)&0xF);
1581 sh4_stats[I_FLDI0]++;
1582 }
1583 break;
1584 case 0x9:
1585 { /* FLDI1 FRn */
1586 uint32_t FRn = ((ir>>8)&0xF);
1587 sh4_stats[I_FLDI1]++;
1588 }
1589 break;
1590 case 0xA:
1591 { /* FCNVSD FPUL, FRn */
1592 uint32_t FRn = ((ir>>8)&0xF);
1593 sh4_stats[I_FCNVSD]++;
1594 }
1595 break;
1596 case 0xB:
1597 { /* FCNVDS FRm, FPUL */
1598 uint32_t FRm = ((ir>>8)&0xF);
1599 sh4_stats[I_FCNVDS]++;
1600 }
1601 break;
1602 case 0xE:
1603 { /* FIPR FVm, FVn */
1604 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
1605 sh4_stats[I_FIPR]++;
1606 }
1607 break;
1608 case 0xF:
1609 switch( (ir&0x100) >> 8 ) {
1610 case 0x0:
1611 { /* FSCA FPUL, FRn */
1612 uint32_t FRn = ((ir>>9)&0x7)<<1;
1613 sh4_stats[I_FSCA]++;
1614 }
1615 break;
1616 case 0x1:
1617 switch( (ir&0x200) >> 9 ) {
1618 case 0x0:
1619 { /* FTRV XMTRX, FVn */
1620 uint32_t FVn = ((ir>>10)&0x3);
1621 sh4_stats[I_FTRV]++;
1622 }
1623 break;
1624 case 0x1:
1625 switch( (ir&0xC00) >> 10 ) {
1626 case 0x0:
1627 { /* FSCHG */
1628 sh4_stats[I_FSCHG]++;
1629 }
1630 break;
1631 case 0x2:
1632 { /* FRCHG */
1633 sh4_stats[I_FRCHG]++;
1634 }
1635 break;
1636 case 0x3:
1637 { /* UNDEF */
1638 sh4_stats[I_UNDEF]++;
1639 }
1640 break;
1641 default:
1642 UNDEF();
1643 break;
1644 }
1645 break;
1646 }
1647 break;
1648 }
1649 break;
1650 default:
1651 UNDEF();
1652 break;
1653 }
1654 break;
1655 case 0xE:
1656 { /* FMAC FR0, FRm, FRn */
1657 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1658 sh4_stats[I_FMAC]++;
1659 }
1660 break;
1661 default:
1662 UNDEF();
1663 break;
1664 }
1665 break;
1666 }
1669 sh4_stats_total++;
1670 }
.