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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 566:59be465e5f01
prev561:533f6b478071
next569:a1c49e1e8776
author nkeynes
date Tue Jan 01 08:57:33 2008 +0000 (13 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Add breakpoint_type_t enum (general cleanup)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4mmio.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/xltcache.h"
    28 #include "sh4/sh4stat.h"
    29 #include "mem.h"
    30 #include "clock.h"
    31 #include "syscall.h"
    33 void sh4_init( void );
    34 void sh4_xlat_init( void );
    35 void sh4_reset( void );
    36 void sh4_start( void );
    37 void sh4_stop( void );
    38 void sh4_save_state( FILE *f );
    39 int sh4_load_state( FILE *f );
    41 uint32_t sh4_run_slice( uint32_t );
    42 uint32_t sh4_xlat_run_slice( uint32_t );
    44 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    45 				       NULL, sh4_run_slice, sh4_stop,
    46 				       sh4_save_state, sh4_load_state };
    48 struct sh4_registers sh4r;
    49 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    50 int sh4_breakpoint_count = 0;
    51 extern sh4ptr_t sh4_main_ram;
    52 static gboolean sh4_use_translator = FALSE;
    54 struct sh4_icache_info {
    55     char *page;
    56     uint32_t page_start;
    57     uint32_t page_size;
    58 };
    60 extern struct sh4_icache_info sh4_icache;
    62 // struct sh4_icache_info sh4_icache = { NULL, -1, -1 };
    64 void sh4_set_use_xlat( gboolean use )
    65 {
    66 // No-op if the translator was not built
    67 #ifdef SH4_TRANSLATOR
    68     if( use ) {
    69 	xlat_cache_init();
    70 	sh4_x86_init();
    71 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    72     } else {
    73 	sh4_module.run_time_slice = sh4_run_slice;
    74     }
    75     sh4_use_translator = use;
    76 #endif
    77 }
    79 void sh4_init(void)
    80 {
    81     register_io_regions( mmio_list_sh4mmio );
    82     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    83     MMU_init();
    84     sh4_reset();
    85 }
    87 void sh4_reset(void)
    88 {
    89     if(	sh4_use_translator ) {
    90 	xlat_flush_cache();
    91     }
    93     /* zero everything out, for the sake of having a consistent state. */
    94     memset( &sh4r, 0, sizeof(sh4r) );
    96     /* Resume running if we were halted */
    97     sh4r.sh4_state = SH4_STATE_RUNNING;
    99     sh4r.pc    = 0xA0000000;
   100     sh4r.new_pc= 0xA0000002;
   101     sh4r.vbr   = 0x00000000;
   102     sh4r.fpscr = 0x00040001;
   103     sh4r.sr    = 0x700000F0;
   104     sh4r.fr_bank = &sh4r.fr[0][0];
   106     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   107     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   109     /* Peripheral modules */
   110     CPG_reset();
   111     INTC_reset();
   112     MMU_reset();
   113     TMU_reset();
   114     SCIF_reset();
   115     sh4_stats_reset();
   116 }
   118 void sh4_stop(void)
   119 {
   120     if(	sh4_use_translator ) {
   121 	/* If we were running with the translator, update new_pc and in_delay_slot */
   122 	sh4r.new_pc = sh4r.pc+2;
   123 	sh4r.in_delay_slot = FALSE;
   124     }
   126 }
   128 void sh4_save_state( FILE *f )
   129 {
   130     if(	sh4_use_translator ) {
   131 	/* If we were running with the translator, update new_pc and in_delay_slot */
   132 	sh4r.new_pc = sh4r.pc+2;
   133 	sh4r.in_delay_slot = FALSE;
   134     }
   136     fwrite( &sh4r, sizeof(sh4r), 1, f );
   137     MMU_save_state( f );
   138     INTC_save_state( f );
   139     TMU_save_state( f );
   140     SCIF_save_state( f );
   141 }
   143 int sh4_load_state( FILE * f )
   144 {
   145     if(	sh4_use_translator ) {
   146 	xlat_flush_cache();
   147     }
   148     fread( &sh4r, sizeof(sh4r), 1, f );
   149     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   150     MMU_load_state( f );
   151     INTC_load_state( f );
   152     TMU_load_state( f );
   153     return SCIF_load_state( f );
   154 }
   157 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   158 {
   159     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   160     sh4_breakpoints[sh4_breakpoint_count].type = type;
   161     sh4_breakpoint_count++;
   162 }
   164 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   165 {
   166     int i;
   168     for( i=0; i<sh4_breakpoint_count; i++ ) {
   169 	if( sh4_breakpoints[i].address == pc && 
   170 	    sh4_breakpoints[i].type == type ) {
   171 	    while( ++i < sh4_breakpoint_count ) {
   172 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   173 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   174 	    }
   175 	    sh4_breakpoint_count--;
   176 	    return TRUE;
   177 	}
   178     }
   179     return FALSE;
   180 }
   182 int sh4_get_breakpoint( uint32_t pc )
   183 {
   184     int i;
   185     for( i=0; i<sh4_breakpoint_count; i++ ) {
   186 	if( sh4_breakpoints[i].address == pc )
   187 	    return sh4_breakpoints[i].type;
   188     }
   189     return 0;
   190 }
   192 void sh4_set_pc( int pc )
   193 {
   194     sh4r.pc = pc;
   195     sh4r.new_pc = pc+2;
   196 }
   199 /******************************* Support methods ***************************/
   201 static void sh4_switch_banks( )
   202 {
   203     uint32_t tmp[8];
   205     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   206     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   207     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   208 }
   210 void sh4_write_sr( uint32_t newval )
   211 {
   212     if( (newval ^ sh4r.sr) & SR_RB )
   213         sh4_switch_banks();
   214     sh4r.sr = newval;
   215     sh4r.t = (newval&SR_T) ? 1 : 0;
   216     sh4r.s = (newval&SR_S) ? 1 : 0;
   217     sh4r.m = (newval&SR_M) ? 1 : 0;
   218     sh4r.q = (newval&SR_Q) ? 1 : 0;
   219     intc_mask_changed();
   220 }
   222 uint32_t sh4_read_sr( void )
   223 {
   224     /* synchronize sh4r.sr with the various bitflags */
   225     sh4r.sr &= SR_MQSTMASK;
   226     if( sh4r.t ) sh4r.sr |= SR_T;
   227     if( sh4r.s ) sh4r.sr |= SR_S;
   228     if( sh4r.m ) sh4r.sr |= SR_M;
   229     if( sh4r.q ) sh4r.sr |= SR_Q;
   230     return sh4r.sr;
   231 }
   235 #define RAISE( x, v ) do{			\
   236     if( sh4r.vbr == 0 ) { \
   237         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   238         dreamcast_stop(); return FALSE;	\
   239     } else { \
   240         sh4r.spc = sh4r.pc;	\
   241         sh4r.ssr = sh4_read_sr(); \
   242         sh4r.sgr = sh4r.r[15]; \
   243         MMIO_WRITE(MMU,EXPEVT,x); \
   244         sh4r.pc = sh4r.vbr + v; \
   245         sh4r.new_pc = sh4r.pc + 2; \
   246         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   247 	if( sh4r.in_delay_slot ) { \
   248 	    sh4r.in_delay_slot = 0; \
   249 	    sh4r.spc -= 2; \
   250 	} \
   251     } \
   252     return TRUE; } while(0)
   254 /**
   255  * Raise a general CPU exception for the specified exception code.
   256  * (NOT for TRAPA or TLB exceptions)
   257  */
   258 gboolean sh4_raise_exception( int code )
   259 {
   260     RAISE( code, EXV_EXCEPTION );
   261 }
   263 /**
   264  * Raise a CPU reset exception with the specified exception code.
   265  */
   266 gboolean sh4_raise_reset( int code )
   267 {
   268     // FIXME: reset modules as per "manual reset"
   269     sh4_reset();
   270     MMIO_WRITE(MMU,EXPEVT,code);
   271     sh4r.vbr = 0;
   272     sh4r.pc = 0xA0000000;
   273     sh4r.new_pc = sh4r.pc + 2;
   274     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   275 		  &(~SR_FD) );
   276 }
   278 gboolean sh4_raise_trap( int trap )
   279 {
   280     MMIO_WRITE( MMU, TRA, trap<<2 );
   281     return sh4_raise_exception( EXC_TRAP );
   282 }
   284 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   285     if( sh4r.in_delay_slot ) {
   286 	return sh4_raise_exception(slot_code);
   287     } else {
   288 	return sh4_raise_exception(normal_code);
   289     }
   290 }
   292 gboolean sh4_raise_tlb_exception( int code )
   293 {
   294     RAISE( code, EXV_TLBMISS );
   295 }
   297 void sh4_accept_interrupt( void )
   298 {
   299     uint32_t code = intc_accept_interrupt();
   300     sh4r.ssr = sh4_read_sr();
   301     sh4r.spc = sh4r.pc;
   302     sh4r.sgr = sh4r.r[15];
   303     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   304     MMIO_WRITE( MMU, INTEVT, code );
   305     sh4r.pc = sh4r.vbr + 0x600;
   306     sh4r.new_pc = sh4r.pc + 2;
   307     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   308 }
   310 void signsat48( void )
   311 {
   312     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   313 	sh4r.mac = 0xFFFF800000000000LL;
   314     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   315 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   316 }
   318 void sh4_fsca( uint32_t anglei, float *fr )
   319 {
   320     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   321     *fr++ = cosf(angle);
   322     *fr = sinf(angle);
   323 }
   325 void sh4_sleep(void)
   326 {
   327     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   328 	sh4r.sh4_state = SH4_STATE_STANDBY;
   329     } else {
   330 	sh4r.sh4_state = SH4_STATE_SLEEP;
   331     }
   332 }
   334 /**
   335  * Compute the matrix tranform of fv given the matrix xf.
   336  * Both fv and xf are word-swapped as per the sh4r.fr banks
   337  */
   338 void sh4_ftrv( float *target, float *xf )
   339 {
   340     float fv[4] = { target[1], target[0], target[3], target[2] };
   341     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   342 	xf[9]*fv[2] + xf[13]*fv[3];
   343     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   344 	xf[8]*fv[2] + xf[12]*fv[3];
   345     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   346 	xf[11]*fv[2] + xf[15]*fv[3];
   347     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   348 	xf[10]*fv[2] + xf[14]*fv[3];
   349 }
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