4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "dreamcast.h"
28 #include "sh4/sh4core.h"
29 #include "sh4/sh4mmio.h"
32 #define SH4_CALLTRACE 1
34 #define MAX_INT 0x7FFFFFFF
35 #define MIN_INT 0x80000000
36 #define MAX_INTF 2147483647.0
37 #define MIN_INTF -2147483648.0
39 /********************** SH4 Module Definition ****************************/
41 uint16_t *sh4_icache = NULL;
42 uint32_t sh4_icache_addr = 0;
44 uint32_t sh4_run_slice( uint32_t nanosecs )
49 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
50 if( sh4r.event_pending < nanosecs ) {
51 sh4r.sh4_state = SH4_STATE_RUNNING;
52 sh4r.slice_cycle = sh4r.event_pending;
56 if( sh4_breakpoint_count == 0 ) {
57 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
58 if( SH4_EVENT_PENDING() ) {
59 if( sh4r.event_types & PENDING_EVENT ) {
62 /* Eventq execute may (quite likely) deliver an immediate IRQ */
63 if( sh4r.event_types & PENDING_IRQ ) {
64 sh4_accept_interrupt();
67 if( !sh4_execute_instruction() ) {
72 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
73 if( SH4_EVENT_PENDING() ) {
74 if( sh4r.event_types & PENDING_EVENT ) {
77 /* Eventq execute may (quite likely) deliver an immediate IRQ */
78 if( sh4r.event_types & PENDING_IRQ ) {
79 sh4_accept_interrupt();
83 if( !sh4_execute_instruction() )
85 #ifdef ENABLE_DEBUG_MODE
86 for( i=0; i<sh4_breakpoint_count; i++ ) {
87 if( sh4_breakpoints[i].address == sh4r.pc ) {
91 if( i != sh4_breakpoint_count ) {
93 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
94 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
101 /* If we aborted early, but the cpu is still technically running,
102 * we're doing a hard abort - cut the timeslice back to what we
105 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
106 nanosecs = sh4r.slice_cycle;
108 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
109 TMU_run_slice( nanosecs );
110 SCIF_run_slice( nanosecs );
115 /********************** SH4 emulation core ****************************/
117 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
118 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
120 #if(SH4_CALLTRACE == 1)
121 #define MAX_CALLSTACK 32
122 static struct call_stack {
124 sh4addr_t target_addr;
125 sh4addr_t stack_pointer;
126 } call_stack[MAX_CALLSTACK];
128 static int call_stack_depth = 0;
129 int sh4_call_trace_on = 0;
131 static inline void trace_call( sh4addr_t source, sh4addr_t dest )
133 if( call_stack_depth < MAX_CALLSTACK ) {
134 call_stack[call_stack_depth].call_addr = source;
135 call_stack[call_stack_depth].target_addr = dest;
136 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
141 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
143 if( call_stack_depth > 0 ) {
148 void fprint_stack_trace( FILE *f )
150 int i = call_stack_depth -1;
151 if( i >= MAX_CALLSTACK )
152 i = MAX_CALLSTACK - 1;
153 for( ; i >= 0; i-- ) {
154 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
155 (call_stack_depth - i), call_stack[i].call_addr,
156 call_stack[i].target_addr, call_stack[i].stack_pointer );
160 #define TRACE_CALL( source, dest ) trace_call(source, dest)
161 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
163 #define TRACE_CALL( dest, rts )
164 #define TRACE_RETURN( source, dest )
167 #define MEM_READ_BYTE( addr, val ) memtmp = sh4_read_byte(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }
168 #define MEM_READ_WORD( addr, val ) memtmp = sh4_read_word(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }
169 #define MEM_READ_LONG( addr, val ) memtmp = sh4_read_long(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }
170 #define MEM_WRITE_BYTE( addr, val ) if( sh4_write_byte(addr, val) ) { return TRUE; }
171 #define MEM_WRITE_WORD( addr, val ) if( sh4_write_word(addr, val) ) { return TRUE; }
172 #define MEM_WRITE_LONG( addr, val ) if( sh4_write_long(addr, val) ) { return TRUE; }
174 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
176 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
177 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
179 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
180 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
181 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
182 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
183 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
185 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
186 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
187 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
189 static void sh4_write_float( uint32_t addr, int reg )
191 if( IS_FPU_DOUBLESIZE() ) {
193 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
194 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
196 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
197 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
200 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
204 static void sh4_read_float( uint32_t addr, int reg )
206 if( IS_FPU_DOUBLESIZE() ) {
208 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
209 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
211 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
212 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
215 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
219 gboolean sh4_execute_instruction( void )
226 int64_t memtmp; // temporary holder for memory reads
230 if( pc > 0xFFFFFF00 ) {
232 syscall_invoke( pc );
233 sh4r.in_delay_slot = 0;
234 pc = sh4r.pc = sh4r.pr;
235 sh4r.new_pc = sh4r.pc + 2;
239 /* Read instruction */
240 uint32_t pageaddr = pc >> 12;
241 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
242 ir = sh4_icache[(pc&0xFFF)>>1];
244 sh4_icache = (uint16_t *)mem_get_page(pc);
245 if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {
246 /* If someone's actually been so daft as to try to execute out of an IO
247 * region, fallback on the full-blown memory read
250 MEM_READ_WORD(pc, ir);
252 sh4_icache_addr = pageaddr;
253 ir = sh4_icache[(pc&0xFFF)>>1];
256 switch( (ir&0xF000) >> 12 ) {
260 switch( (ir&0x80) >> 7 ) {
262 switch( (ir&0x70) >> 4 ) {
265 uint32_t Rn = ((ir>>8)&0xF);
267 sh4r.r[Rn] = sh4_read_sr();
272 uint32_t Rn = ((ir>>8)&0xF);
274 sh4r.r[Rn] = sh4r.gbr;
279 uint32_t Rn = ((ir>>8)&0xF);
281 sh4r.r[Rn] = sh4r.vbr;
286 uint32_t Rn = ((ir>>8)&0xF);
288 sh4r.r[Rn] = sh4r.ssr;
293 uint32_t Rn = ((ir>>8)&0xF);
295 sh4r.r[Rn] = sh4r.spc;
304 { /* STC Rm_BANK, Rn */
305 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
307 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
313 switch( (ir&0xF0) >> 4 ) {
316 uint32_t Rn = ((ir>>8)&0xF);
318 CHECKDEST( pc + 4 + sh4r.r[Rn] );
319 sh4r.in_delay_slot = 1;
320 sh4r.pr = sh4r.pc + 4;
321 sh4r.pc = sh4r.new_pc;
322 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
323 TRACE_CALL( pc, sh4r.new_pc );
329 uint32_t Rn = ((ir>>8)&0xF);
331 CHECKDEST( pc + 4 + sh4r.r[Rn] );
332 sh4r.in_delay_slot = 1;
333 sh4r.pc = sh4r.new_pc;
334 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
340 uint32_t Rn = ((ir>>8)&0xF);
342 if( (tmp & 0xFC000000) == 0xE0000000 ) {
343 sh4_flush_store_queue(tmp);
349 uint32_t Rn = ((ir>>8)&0xF);
354 uint32_t Rn = ((ir>>8)&0xF);
359 uint32_t Rn = ((ir>>8)&0xF);
363 { /* MOVCA.L R0, @Rn */
364 uint32_t Rn = ((ir>>8)&0xF);
367 MEM_WRITE_LONG( tmp, R0 );
376 { /* MOV.B Rm, @(R0, Rn) */
377 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
378 MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
382 { /* MOV.W Rm, @(R0, Rn) */
383 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
384 CHECKWALIGN16( R0 + sh4r.r[Rn] );
385 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
389 { /* MOV.L Rm, @(R0, Rn) */
390 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
391 CHECKWALIGN32( R0 + sh4r.r[Rn] );
392 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
397 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
398 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
399 (sh4r.r[Rm] * sh4r.r[Rn]);
403 switch( (ir&0xFF0) >> 4 ) {
440 switch( (ir&0xF0) >> 4 ) {
448 sh4r.m = sh4r.q = sh4r.t = 0;
453 uint32_t Rn = ((ir>>8)&0xF);
463 switch( (ir&0xF0) >> 4 ) {
466 uint32_t Rn = ((ir>>8)&0xF);
467 sh4r.r[Rn] = (sh4r.mac>>32);
472 uint32_t Rn = ((ir>>8)&0xF);
473 sh4r.r[Rn] = (uint32_t)sh4r.mac;
478 uint32_t Rn = ((ir>>8)&0xF);
479 sh4r.r[Rn] = sh4r.pr;
484 uint32_t Rn = ((ir>>8)&0xF);
486 sh4r.r[Rn] = sh4r.sgr;
491 uint32_t Rn = ((ir>>8)&0xF);
492 sh4r.r[Rn] = sh4r.fpul;
496 { /* STS FPSCR, Rn */
497 uint32_t Rn = ((ir>>8)&0xF);
498 sh4r.r[Rn] = sh4r.fpscr;
503 uint32_t Rn = ((ir>>8)&0xF);
504 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
513 switch( (ir&0xFF0) >> 4 ) {
517 CHECKDEST( sh4r.pr );
518 sh4r.in_delay_slot = 1;
519 sh4r.pc = sh4r.new_pc;
520 sh4r.new_pc = sh4r.pr;
521 TRACE_RETURN( pc, sh4r.new_pc );
527 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
528 sh4r.sh4_state = SH4_STATE_STANDBY;
530 sh4r.sh4_state = SH4_STATE_SLEEP;
532 return FALSE; /* Halt CPU */
538 CHECKDEST( sh4r.spc );
540 sh4r.in_delay_slot = 1;
541 sh4r.pc = sh4r.new_pc;
542 sh4r.new_pc = sh4r.spc;
543 sh4_write_sr( sh4r.ssr );
553 { /* MOV.B @(R0, Rm), Rn */
554 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
555 MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] );
559 { /* MOV.W @(R0, Rm), Rn */
560 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
561 CHECKRALIGN16( R0 + sh4r.r[Rm] );
562 MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
566 { /* MOV.L @(R0, Rm), Rn */
567 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
568 CHECKRALIGN32( R0 + sh4r.r[Rm] );
569 MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
573 { /* MAC.L @Rm+, @Rn+ */
574 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
575 CHECKRALIGN32( sh4r.r[Rm] );
576 CHECKRALIGN32( sh4r.r[Rn] );
577 MEM_READ_LONG(sh4r.r[Rn], tmp);
578 int64_t tmpl = SIGNEXT32(tmp);
580 MEM_READ_LONG(sh4r.r[Rm], tmp);
581 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
584 /* 48-bit Saturation. Yuch */
585 if( tmpl < (int64_t)0xFFFF800000000000LL )
586 tmpl = 0xFFFF800000000000LL;
587 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
588 tmpl = 0x00007FFFFFFFFFFFLL;
599 { /* MOV.L Rm, @(disp, Rn) */
600 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
601 tmp = sh4r.r[Rn] + disp;
602 CHECKWALIGN32( tmp );
603 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
609 { /* MOV.B Rm, @Rn */
610 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
611 MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
615 { /* MOV.W Rm, @Rn */
616 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
617 CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
621 { /* MOV.L Rm, @Rn */
622 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
623 CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
627 { /* MOV.B Rm, @-Rn */
628 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
629 sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
633 { /* MOV.W Rm, @-Rn */
634 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
635 sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
639 { /* MOV.L Rm, @-Rn */
640 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
641 sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
646 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
647 sh4r.q = sh4r.r[Rn]>>31;
648 sh4r.m = sh4r.r[Rm]>>31;
649 sh4r.t = sh4r.q ^ sh4r.m;
654 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
655 sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
660 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
661 sh4r.r[Rn] &= sh4r.r[Rm];
666 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
667 sh4r.r[Rn] ^= sh4r.r[Rm];
672 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
673 sh4r.r[Rn] |= sh4r.r[Rm];
677 { /* CMP/STR Rm, Rn */
678 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
679 /* set T = 1 if any byte in RM & RN is the same */
680 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
681 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
682 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
687 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
688 sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
692 { /* MULU.W Rm, Rn */
693 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
694 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
695 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
699 { /* MULS.W Rm, Rn */
700 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
701 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
702 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
713 { /* CMP/EQ Rm, Rn */
714 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
715 sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
719 { /* CMP/HS Rm, Rn */
720 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
721 sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
725 { /* CMP/GE Rm, Rn */
726 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
727 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
732 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
733 /* This is derived from the sh4 manual with some simplifications */
734 uint32_t tmp0, tmp1, tmp2, dir;
736 dir = sh4r.q ^ sh4r.m;
737 sh4r.q = (sh4r.r[Rn] >> 31);
739 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
743 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
746 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
748 sh4r.q ^= sh4r.m ^ tmp1;
749 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
753 { /* DMULU.L Rm, Rn */
754 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
755 sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
759 { /* CMP/HI Rm, Rn */
760 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
761 sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
765 { /* CMP/GT Rm, Rn */
766 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
767 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
772 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
773 sh4r.r[Rn] -= sh4r.r[Rm];
778 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
780 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
781 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
785 UNIMP(ir); /* SUBV Rm, Rn */
789 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
790 sh4r.r[Rn] += sh4r.r[Rm];
794 { /* DMULS.L Rm, Rn */
795 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
796 sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
801 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
803 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
804 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
809 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
810 tmp = sh4r.r[Rn] + sh4r.r[Rm];
811 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
823 switch( (ir&0xF0) >> 4 ) {
826 uint32_t Rn = ((ir>>8)&0xF);
827 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
832 uint32_t Rn = ((ir>>8)&0xF);
834 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
839 uint32_t Rn = ((ir>>8)&0xF);
840 sh4r.t = sh4r.r[Rn] >> 31;
850 switch( (ir&0xF0) >> 4 ) {
853 uint32_t Rn = ((ir>>8)&0xF);
854 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
859 uint32_t Rn = ((ir>>8)&0xF);
860 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
865 uint32_t Rn = ((ir>>8)&0xF);
866 sh4r.t = sh4r.r[Rn] & 0x00000001;
867 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
876 switch( (ir&0xF0) >> 4 ) {
878 { /* STS.L MACH, @-Rn */
879 uint32_t Rn = ((ir>>8)&0xF);
881 CHECKWALIGN32( sh4r.r[Rn] );
882 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
886 { /* STS.L MACL, @-Rn */
887 uint32_t Rn = ((ir>>8)&0xF);
889 CHECKWALIGN32( sh4r.r[Rn] );
890 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
894 { /* STS.L PR, @-Rn */
895 uint32_t Rn = ((ir>>8)&0xF);
897 CHECKWALIGN32( sh4r.r[Rn] );
898 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
902 { /* STC.L SGR, @-Rn */
903 uint32_t Rn = ((ir>>8)&0xF);
906 CHECKWALIGN32( sh4r.r[Rn] );
907 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
911 { /* STS.L FPUL, @-Rn */
912 uint32_t Rn = ((ir>>8)&0xF);
914 CHECKWALIGN32( sh4r.r[Rn] );
915 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
919 { /* STS.L FPSCR, @-Rn */
920 uint32_t Rn = ((ir>>8)&0xF);
922 CHECKWALIGN32( sh4r.r[Rn] );
923 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
927 { /* STC.L DBR, @-Rn */
928 uint32_t Rn = ((ir>>8)&0xF);
931 CHECKWALIGN32( sh4r.r[Rn] );
932 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
941 switch( (ir&0x80) >> 7 ) {
943 switch( (ir&0x70) >> 4 ) {
945 { /* STC.L SR, @-Rn */
946 uint32_t Rn = ((ir>>8)&0xF);
949 CHECKWALIGN32( sh4r.r[Rn] );
950 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
954 { /* STC.L GBR, @-Rn */
955 uint32_t Rn = ((ir>>8)&0xF);
957 CHECKWALIGN32( sh4r.r[Rn] );
958 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
962 { /* STC.L VBR, @-Rn */
963 uint32_t Rn = ((ir>>8)&0xF);
966 CHECKWALIGN32( sh4r.r[Rn] );
967 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
971 { /* STC.L SSR, @-Rn */
972 uint32_t Rn = ((ir>>8)&0xF);
975 CHECKWALIGN32( sh4r.r[Rn] );
976 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
980 { /* STC.L SPC, @-Rn */
981 uint32_t Rn = ((ir>>8)&0xF);
984 CHECKWALIGN32( sh4r.r[Rn] );
985 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
994 { /* STC.L Rm_BANK, @-Rn */
995 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
998 CHECKWALIGN32( sh4r.r[Rn] );
999 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
1005 switch( (ir&0xF0) >> 4 ) {
1008 uint32_t Rn = ((ir>>8)&0xF);
1009 sh4r.t = sh4r.r[Rn] >> 31;
1011 sh4r.r[Rn] |= sh4r.t;
1016 uint32_t Rn = ((ir>>8)&0xF);
1017 tmp = sh4r.r[Rn] >> 31;
1019 sh4r.r[Rn] |= sh4r.t;
1029 switch( (ir&0xF0) >> 4 ) {
1032 uint32_t Rn = ((ir>>8)&0xF);
1033 sh4r.t = sh4r.r[Rn] & 0x00000001;
1035 sh4r.r[Rn] |= (sh4r.t << 31);
1040 uint32_t Rn = ((ir>>8)&0xF);
1041 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
1046 uint32_t Rn = ((ir>>8)&0xF);
1047 tmp = sh4r.r[Rn] & 0x00000001;
1049 sh4r.r[Rn] |= (sh4r.t << 31 );
1059 switch( (ir&0xF0) >> 4 ) {
1061 { /* LDS.L @Rm+, MACH */
1062 uint32_t Rm = ((ir>>8)&0xF);
1063 CHECKRALIGN32( sh4r.r[Rm] );
1064 MEM_READ_LONG(sh4r.r[Rm], tmp);
1065 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1066 (((uint64_t)tmp)<<32);
1071 { /* LDS.L @Rm+, MACL */
1072 uint32_t Rm = ((ir>>8)&0xF);
1073 CHECKRALIGN32( sh4r.r[Rm] );
1074 MEM_READ_LONG(sh4r.r[Rm], tmp);
1075 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1076 (uint64_t)((uint32_t)tmp);
1081 { /* LDS.L @Rm+, PR */
1082 uint32_t Rm = ((ir>>8)&0xF);
1083 CHECKRALIGN32( sh4r.r[Rm] );
1084 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
1089 { /* LDC.L @Rm+, SGR */
1090 uint32_t Rm = ((ir>>8)&0xF);
1092 CHECKRALIGN32( sh4r.r[Rm] );
1093 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
1098 { /* LDS.L @Rm+, FPUL */
1099 uint32_t Rm = ((ir>>8)&0xF);
1100 CHECKRALIGN32( sh4r.r[Rm] );
1101 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
1106 { /* LDS.L @Rm+, FPSCR */
1107 uint32_t Rm = ((ir>>8)&0xF);
1108 CHECKRALIGN32( sh4r.r[Rm] );
1109 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
1111 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1115 { /* LDC.L @Rm+, DBR */
1116 uint32_t Rm = ((ir>>8)&0xF);
1118 CHECKRALIGN32( sh4r.r[Rm] );
1119 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
1129 switch( (ir&0x80) >> 7 ) {
1131 switch( (ir&0x70) >> 4 ) {
1133 { /* LDC.L @Rm+, SR */
1134 uint32_t Rm = ((ir>>8)&0xF);
1137 CHECKWALIGN32( sh4r.r[Rm] );
1138 MEM_READ_LONG(sh4r.r[Rm], tmp);
1139 sh4_write_sr( tmp );
1144 { /* LDC.L @Rm+, GBR */
1145 uint32_t Rm = ((ir>>8)&0xF);
1146 CHECKRALIGN32( sh4r.r[Rm] );
1147 MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
1152 { /* LDC.L @Rm+, VBR */
1153 uint32_t Rm = ((ir>>8)&0xF);
1155 CHECKRALIGN32( sh4r.r[Rm] );
1156 MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
1161 { /* LDC.L @Rm+, SSR */
1162 uint32_t Rm = ((ir>>8)&0xF);
1164 CHECKRALIGN32( sh4r.r[Rm] );
1165 MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
1170 { /* LDC.L @Rm+, SPC */
1171 uint32_t Rm = ((ir>>8)&0xF);
1173 CHECKRALIGN32( sh4r.r[Rm] );
1174 MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
1184 { /* LDC.L @Rm+, Rn_BANK */
1185 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1187 CHECKRALIGN32( sh4r.r[Rm] );
1188 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
1195 switch( (ir&0xF0) >> 4 ) {
1198 uint32_t Rn = ((ir>>8)&0xF);
1204 uint32_t Rn = ((ir>>8)&0xF);
1210 uint32_t Rn = ((ir>>8)&0xF);
1220 switch( (ir&0xF0) >> 4 ) {
1223 uint32_t Rn = ((ir>>8)&0xF);
1229 uint32_t Rn = ((ir>>8)&0xF);
1235 uint32_t Rn = ((ir>>8)&0xF);
1245 switch( (ir&0xF0) >> 4 ) {
1247 { /* LDS Rm, MACH */
1248 uint32_t Rm = ((ir>>8)&0xF);
1249 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1250 (((uint64_t)sh4r.r[Rm])<<32);
1254 { /* LDS Rm, MACL */
1255 uint32_t Rm = ((ir>>8)&0xF);
1256 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1257 (uint64_t)((uint32_t)(sh4r.r[Rm]));
1262 uint32_t Rm = ((ir>>8)&0xF);
1263 sh4r.pr = sh4r.r[Rm];
1268 uint32_t Rm = ((ir>>8)&0xF);
1270 sh4r.sgr = sh4r.r[Rm];
1274 { /* LDS Rm, FPUL */
1275 uint32_t Rm = ((ir>>8)&0xF);
1276 sh4r.fpul = sh4r.r[Rm];
1280 { /* LDS Rm, FPSCR */
1281 uint32_t Rm = ((ir>>8)&0xF);
1282 sh4r.fpscr = sh4r.r[Rm];
1283 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1288 uint32_t Rm = ((ir>>8)&0xF);
1290 sh4r.dbr = sh4r.r[Rm];
1299 switch( (ir&0xF0) >> 4 ) {
1302 uint32_t Rn = ((ir>>8)&0xF);
1303 CHECKDEST( sh4r.r[Rn] );
1305 sh4r.in_delay_slot = 1;
1306 sh4r.pc = sh4r.new_pc;
1307 sh4r.new_pc = sh4r.r[Rn];
1309 TRACE_CALL( pc, sh4r.new_pc );
1315 uint32_t Rn = ((ir>>8)&0xF);
1316 MEM_READ_BYTE( sh4r.r[Rn], tmp );
1317 sh4r.t = ( tmp == 0 ? 1 : 0 );
1318 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
1323 uint32_t Rn = ((ir>>8)&0xF);
1324 CHECKDEST( sh4r.r[Rn] );
1326 sh4r.in_delay_slot = 1;
1327 sh4r.pc = sh4r.new_pc;
1328 sh4r.new_pc = sh4r.r[Rn];
1339 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1341 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1342 else if( (tmp & 0x1F) == 0 )
1343 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
1345 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
1350 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1352 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1353 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
1354 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
1358 switch( (ir&0x80) >> 7 ) {
1360 switch( (ir&0x70) >> 4 ) {
1363 uint32_t Rm = ((ir>>8)&0xF);
1366 sh4_write_sr( sh4r.r[Rm] );
1371 uint32_t Rm = ((ir>>8)&0xF);
1372 sh4r.gbr = sh4r.r[Rm];
1377 uint32_t Rm = ((ir>>8)&0xF);
1379 sh4r.vbr = sh4r.r[Rm];
1384 uint32_t Rm = ((ir>>8)&0xF);
1386 sh4r.ssr = sh4r.r[Rm];
1391 uint32_t Rm = ((ir>>8)&0xF);
1393 sh4r.spc = sh4r.r[Rm];
1402 { /* LDC Rm, Rn_BANK */
1403 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1405 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
1411 { /* MAC.W @Rm+, @Rn+ */
1412 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1413 CHECKRALIGN16( sh4r.r[Rn] );
1414 CHECKRALIGN16( sh4r.r[Rm] );
1415 MEM_READ_WORD(sh4r.r[Rn], tmp);
1416 int32_t stmp = SIGNEXT16(tmp);
1418 MEM_READ_WORD(sh4r.r[Rm], tmp);
1419 stmp = stmp * SIGNEXT16(tmp);
1422 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
1423 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
1424 sh4r.mac = 0x000000017FFFFFFFLL;
1425 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
1426 sh4r.mac = 0x0000000180000000LL;
1428 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1429 ((uint32_t)(sh4r.mac + stmp));
1432 sh4r.mac += SIGNEXT32(stmp);
1439 { /* MOV.L @(disp, Rm), Rn */
1440 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1441 tmp = sh4r.r[Rm] + disp;
1442 CHECKRALIGN32( tmp );
1443 MEM_READ_LONG( tmp, sh4r.r[Rn] );
1449 { /* MOV.B @Rm, Rn */
1450 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1451 MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] );
1455 { /* MOV.W @Rm, Rn */
1456 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1457 CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] );
1461 { /* MOV.L @Rm, Rn */
1462 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1463 CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] );
1468 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1469 sh4r.r[Rn] = sh4r.r[Rm];
1473 { /* MOV.B @Rm+, Rn */
1474 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1475 MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++;
1479 { /* MOV.W @Rm+, Rn */
1480 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1481 CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2;
1485 { /* MOV.L @Rm+, Rn */
1486 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1487 CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4;
1492 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1493 sh4r.r[Rn] = ~sh4r.r[Rm];
1497 { /* SWAP.B Rm, Rn */
1498 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1499 sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
1503 { /* SWAP.W Rm, Rn */
1504 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1505 sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
1510 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1511 tmp = 0 - sh4r.r[Rm];
1512 sh4r.r[Rn] = tmp - sh4r.t;
1513 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
1518 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1519 sh4r.r[Rn] = 0 - sh4r.r[Rm];
1523 { /* EXTU.B Rm, Rn */
1524 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1525 sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
1529 { /* EXTU.W Rm, Rn */
1530 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1531 sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
1535 { /* EXTS.B Rm, Rn */
1536 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1537 sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
1541 { /* EXTS.W Rm, Rn */
1542 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1543 sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
1549 { /* ADD #imm, Rn */
1550 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1555 switch( (ir&0xF00) >> 8 ) {
1557 { /* MOV.B R0, @(disp, Rn) */
1558 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1559 MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
1563 { /* MOV.W R0, @(disp, Rn) */
1564 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1565 tmp = sh4r.r[Rn] + disp;
1566 CHECKWALIGN16( tmp );
1567 MEM_WRITE_WORD( tmp, R0 );
1571 { /* MOV.B @(disp, Rm), R0 */
1572 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1573 MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 );
1577 { /* MOV.W @(disp, Rm), R0 */
1578 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1579 tmp = sh4r.r[Rm] + disp;
1580 CHECKRALIGN16( tmp );
1581 MEM_READ_WORD( tmp, R0 );
1585 { /* CMP/EQ #imm, R0 */
1586 int32_t imm = SIGNEXT8(ir&0xFF);
1587 sh4r.t = ( R0 == imm ? 1 : 0 );
1592 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1595 CHECKDEST( sh4r.pc + disp + 4 )
1596 sh4r.pc += disp + 4;
1597 sh4r.new_pc = sh4r.pc + 2;
1604 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1607 CHECKDEST( sh4r.pc + disp + 4 )
1608 sh4r.pc += disp + 4;
1609 sh4r.new_pc = sh4r.pc + 2;
1616 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1619 CHECKDEST( sh4r.pc + disp + 4 )
1620 sh4r.in_delay_slot = 1;
1621 sh4r.pc = sh4r.new_pc;
1622 sh4r.new_pc = pc + disp + 4;
1623 sh4r.in_delay_slot = 1;
1630 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1633 CHECKDEST( sh4r.pc + disp + 4 )
1634 sh4r.in_delay_slot = 1;
1635 sh4r.pc = sh4r.new_pc;
1636 sh4r.new_pc = pc + disp + 4;
1647 { /* MOV.W @(disp, PC), Rn */
1648 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1650 tmp = pc + 4 + disp;
1651 MEM_READ_WORD( tmp, sh4r.r[Rn] );
1656 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1658 CHECKDEST( sh4r.pc + disp + 4 );
1659 sh4r.in_delay_slot = 1;
1660 sh4r.pc = sh4r.new_pc;
1661 sh4r.new_pc = pc + 4 + disp;
1667 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1668 CHECKDEST( sh4r.pc + disp + 4 );
1670 sh4r.in_delay_slot = 1;
1672 sh4r.pc = sh4r.new_pc;
1673 sh4r.new_pc = pc + 4 + disp;
1674 TRACE_CALL( pc, sh4r.new_pc );
1679 switch( (ir&0xF00) >> 8 ) {
1681 { /* MOV.B R0, @(disp, GBR) */
1682 uint32_t disp = (ir&0xFF);
1683 MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
1687 { /* MOV.W R0, @(disp, GBR) */
1688 uint32_t disp = (ir&0xFF)<<1;
1689 tmp = sh4r.gbr + disp;
1690 CHECKWALIGN16( tmp );
1691 MEM_WRITE_WORD( tmp, R0 );
1695 { /* MOV.L R0, @(disp, GBR) */
1696 uint32_t disp = (ir&0xFF)<<2;
1697 tmp = sh4r.gbr + disp;
1698 CHECKWALIGN32( tmp );
1699 MEM_WRITE_LONG( tmp, R0 );
1704 uint32_t imm = (ir&0xFF);
1706 MMIO_WRITE( MMU, TRA, imm<<2 );
1708 sh4_raise_exception( EXC_TRAP );
1712 { /* MOV.B @(disp, GBR), R0 */
1713 uint32_t disp = (ir&0xFF);
1714 MEM_READ_BYTE( sh4r.gbr + disp, R0 );
1718 { /* MOV.W @(disp, GBR), R0 */
1719 uint32_t disp = (ir&0xFF)<<1;
1720 tmp = sh4r.gbr + disp;
1721 CHECKRALIGN16( tmp );
1722 MEM_READ_WORD( tmp, R0 );
1726 { /* MOV.L @(disp, GBR), R0 */
1727 uint32_t disp = (ir&0xFF)<<2;
1728 tmp = sh4r.gbr + disp;
1729 CHECKRALIGN32( tmp );
1730 MEM_READ_LONG( tmp, R0 );
1734 { /* MOVA @(disp, PC), R0 */
1735 uint32_t disp = (ir&0xFF)<<2;
1737 R0 = (pc&0xFFFFFFFC) + disp + 4;
1741 { /* TST #imm, R0 */
1742 uint32_t imm = (ir&0xFF);
1743 sh4r.t = (R0 & imm ? 0 : 1);
1747 { /* AND #imm, R0 */
1748 uint32_t imm = (ir&0xFF);
1753 { /* XOR #imm, R0 */
1754 uint32_t imm = (ir&0xFF);
1760 uint32_t imm = (ir&0xFF);
1765 { /* TST.B #imm, @(R0, GBR) */
1766 uint32_t imm = (ir&0xFF);
1767 MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 );
1771 { /* AND.B #imm, @(R0, GBR) */
1772 uint32_t imm = (ir&0xFF);
1773 MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp );
1777 { /* XOR.B #imm, @(R0, GBR) */
1778 uint32_t imm = (ir&0xFF);
1779 MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp );
1783 { /* OR.B #imm, @(R0, GBR) */
1784 uint32_t imm = (ir&0xFF);
1785 MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp );
1791 { /* MOV.L @(disp, PC), Rn */
1792 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1794 tmp = (pc&0xFFFFFFFC) + disp + 4;
1795 MEM_READ_LONG( tmp, sh4r.r[Rn] );
1799 { /* MOV #imm, Rn */
1800 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1807 { /* FADD FRm, FRn */
1808 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1810 if( IS_FPU_DOUBLEPREC() ) {
1818 { /* FSUB FRm, FRn */
1819 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1821 if( IS_FPU_DOUBLEPREC() ) {
1829 { /* FMUL FRm, FRn */
1830 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1832 if( IS_FPU_DOUBLEPREC() ) {
1840 { /* FDIV FRm, FRn */
1841 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1843 if( IS_FPU_DOUBLEPREC() ) {
1851 { /* FCMP/EQ FRm, FRn */
1852 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1854 if( IS_FPU_DOUBLEPREC() ) {
1855 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
1857 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1862 { /* FCMP/GT FRm, FRn */
1863 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1865 if( IS_FPU_DOUBLEPREC() ) {
1866 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1868 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1873 { /* FMOV @(R0, Rm), FRn */
1874 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1875 MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
1879 { /* FMOV FRm, @(R0, Rn) */
1880 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1881 MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
1885 { /* FMOV @Rm, FRn */
1886 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1887 MEM_FP_READ( sh4r.r[Rm], FRn );
1891 { /* FMOV @Rm+, FRn */
1892 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1893 MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
1897 { /* FMOV FRm, @Rn */
1898 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1899 MEM_FP_WRITE( sh4r.r[Rn], FRm );
1903 { /* FMOV FRm, @-Rn */
1904 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1905 sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
1909 { /* FMOV FRm, FRn */
1910 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1911 if( IS_FPU_DOUBLESIZE() )
1918 switch( (ir&0xF0) >> 4 ) {
1920 { /* FSTS FPUL, FRn */
1921 uint32_t FRn = ((ir>>8)&0xF);
1922 CHECKFPUEN(); FR(FRn) = FPULf;
1926 { /* FLDS FRm, FPUL */
1927 uint32_t FRm = ((ir>>8)&0xF);
1928 CHECKFPUEN(); FPULf = FR(FRm);
1932 { /* FLOAT FPUL, FRn */
1933 uint32_t FRn = ((ir>>8)&0xF);
1935 if( IS_FPU_DOUBLEPREC() ) {
1936 if( FRn&1 ) { // No, really...
1937 dtmp = (double)FPULi;
1938 FR(FRn) = *(((float *)&dtmp)+1);
1940 DRF(FRn>>1) = (double)FPULi;
1943 FR(FRn) = (float)FPULi;
1948 { /* FTRC FRm, FPUL */
1949 uint32_t FRm = ((ir>>8)&0xF);
1951 if( IS_FPU_DOUBLEPREC() ) {
1954 *(((float *)&dtmp)+1) = FR(FRm);
1958 if( dtmp >= MAX_INTF )
1960 else if( dtmp <= MIN_INTF )
1963 FPULi = (int32_t)dtmp;
1966 if( ftmp >= MAX_INTF )
1968 else if( ftmp <= MIN_INTF )
1971 FPULi = (int32_t)ftmp;
1977 uint32_t FRn = ((ir>>8)&0xF);
1979 if( IS_FPU_DOUBLEPREC() ) {
1988 uint32_t FRn = ((ir>>8)&0xF);
1990 if( IS_FPU_DOUBLEPREC() ) {
1991 DR(FRn) = fabs(DR(FRn));
1993 FR(FRn) = fabsf(FR(FRn));
1999 uint32_t FRn = ((ir>>8)&0xF);
2001 if( IS_FPU_DOUBLEPREC() ) {
2002 DR(FRn) = sqrt(DR(FRn));
2004 FR(FRn) = sqrtf(FR(FRn));
2010 uint32_t FRn = ((ir>>8)&0xF);
2012 if( !IS_FPU_DOUBLEPREC() ) {
2013 FR(FRn) = 1.0/sqrtf(FR(FRn));
2019 uint32_t FRn = ((ir>>8)&0xF);
2021 if( IS_FPU_DOUBLEPREC() ) {
2030 uint32_t FRn = ((ir>>8)&0xF);
2032 if( IS_FPU_DOUBLEPREC() ) {
2040 { /* FCNVSD FPUL, FRn */
2041 uint32_t FRn = ((ir>>8)&0xF);
2043 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2044 DR(FRn) = (double)FPULf;
2049 { /* FCNVDS FRm, FPUL */
2050 uint32_t FRm = ((ir>>8)&0xF);
2052 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2053 FPULf = (float)DR(FRm);
2058 { /* FIPR FVm, FVn */
2059 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
2061 if( !IS_FPU_DOUBLEPREC() ) {
2064 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
2065 FR(tmp+1)*FR(tmp2+1) +
2066 FR(tmp+2)*FR(tmp2+2) +
2067 FR(tmp+3)*FR(tmp2+3);
2072 switch( (ir&0x100) >> 8 ) {
2074 { /* FSCA FPUL, FRn */
2075 uint32_t FRn = ((ir>>9)&0x7)<<1;
2077 if( !IS_FPU_DOUBLEPREC() ) {
2078 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
2080 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
2081 FR(FRn) = sinf(angle);
2082 FR((FRn)+1) = cosf(angle);
2088 switch( (ir&0x200) >> 9 ) {
2090 { /* FTRV XMTRX, FVn */
2091 uint32_t FVn = ((ir>>10)&0x3);
2093 if( !IS_FPU_DOUBLEPREC() ) {
2094 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
2097 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
2098 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
2099 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
2100 xf[9]*fv[2] + xf[13]*fv[3];
2101 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
2102 xf[8]*fv[2] + xf[12]*fv[3];
2103 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
2104 xf[11]*fv[2] + xf[15]*fv[3];
2105 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
2106 xf[10]*fv[2] + xf[14]*fv[3];
2112 switch( (ir&0xC00) >> 10 ) {
2115 CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
2121 sh4r.fpscr ^= FPSCR_FR;
2122 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
2145 { /* FMAC FR0, FRm, FRn */
2146 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2148 if( IS_FPU_DOUBLEPREC() ) {
2149 DR(FRn) += DR(FRm)*DR(0);
2151 FR(FRn) += FR(FRm)*FR(0);
2162 sh4r.pc = sh4r.new_pc;
2164 sh4r.in_delay_slot = 0;
.