lxdream 0.9.1| filename | src/sh4/sh4mmio.h |
| changeset | 30:89b30313d757 |
| prev | 19:9da7a8e38f9d |
| next | 550:a27e31340147 |
| author | nkeynes |
| date | Sat Jan 06 04:06:36 2007 +0000 (17 years ago) |
| permissions | -rw-r--r-- |
| last change | Implement event queue. Fix pvr2 timing (yes, again). |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4mmio.h,v 1.4 2005-12-25 05:57:00 nkeynes Exp $
3 *
4 * MMIO region and supporting function declarations. Private to the sh4
5 * module.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #include "mmio.h"
22 #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
23 (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE))
25 #ifdef MMIO_IMPL
26 #define SH4MMIO_IMPL
27 #else
28 #define SH4MMIO_IFACE
29 #endif
30 /* SH7750 onchip mmio devices */
32 MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
33 LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" )
34 LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" )
35 LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" )
36 LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" )
37 LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
38 BYTE_PORT( 0x14, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
39 BYTE_PORT( 0x18, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
40 LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" )
41 LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" )
42 LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
43 LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
44 LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
45 LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
46 LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )
47 MMIO_REGION_END
49 /* User Break Controller (Page 717 [757] of sh7750h manual) */
50 MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" )
51 LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" )
52 BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" )
53 WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" )
54 LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" )
55 BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" )
56 WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" )
57 LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" )
58 LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" )
59 WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" )
60 MMIO_REGION_END
61 /* Bus State Controller (Page 293 [333] of sh7750h manual)
62 * I/O Ports */
63 MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" )
64 LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" )
65 WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" )
66 LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" )
67 LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" )
68 LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" )
69 LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" )
70 WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" )
71 WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" )
72 WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" )
73 WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" )
74 WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" )
75 LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" )
76 WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" )
77 LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" )
78 WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" )
79 WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
80 MMIO_REGION_END
82 /* DMA Controller (Page 457 [497] of sh7750h manual) */
83 MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" )
84 LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" )
85 LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" )
86 LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" )
87 LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" )
88 LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" )
89 LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" )
90 LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" )
91 LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" )
92 LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" )
93 LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" )
94 LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" )
95 LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" )
96 LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" )
97 LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" )
98 LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" )
99 LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" )
100 LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" )
101 MMIO_REGION_END
103 /* Clock Pulse Generator (page 233 [273] of sh7750h manual) */
104 MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" )
105 WORD_PORT( 0x000, FRQCR, PORT_MRW, UNDEFINED, "Frequency control" )
106 BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" )
107 BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" )
108 BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" )
109 BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" )
110 MMIO_REGION_END
112 /* Real time clock (Page 253 [293] of sh7750h manual) */
113 MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" )
114 BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" )
115 BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" )
116 /* ... */
117 MMIO_REGION_END
119 /* Interrupt controller (Page 699 [739] of sh7750h manual) */
120 MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" )
121 WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" )
122 WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" )
123 WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" )
124 WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" )
125 WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" )
126 MMIO_REGION_END
128 /* Timer unit (Page 277 [317] of sh7750h manual) */
129 MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" )
130 BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" )
131 BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" )
132 LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" )
133 LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" )
134 WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" )
135 LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" )
136 LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" )
137 WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" )
138 LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" )
139 LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" )
140 WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" )
141 LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" )
142 MMIO_REGION_END
144 /* Serial channel (page 541 [581] of sh7750h manual) */
145 MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" )
146 BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" )
147 BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" )
148 BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" )
149 BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" )
150 BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" )
151 BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" )
152 BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" )
153 MMIO_REGION_END
155 MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )
156 WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )
157 BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )
158 WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )
159 BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )
160 WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)")
161 BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )
162 WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )
163 WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )
164 WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" )
165 WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" )
166 MMIO_REGION_END
168 MMIO_REGION_LIST_BEGIN( sh4mmio )
169 MMIO_REGION( MMU )
170 MMIO_REGION( UBC )
171 MMIO_REGION( BSC )
172 MMIO_REGION( DMAC )
173 MMIO_REGION( CPG )
174 MMIO_REGION( RTC )
175 MMIO_REGION( INTC )
176 MMIO_REGION( TMU )
177 MMIO_REGION( SCI )
178 MMIO_REGION( SCIF )
179 MMIO_REGION_LIST_END
181 /* mmucr register bits */
182 #define MMUCR_AT 0x00000001 /* Address Translation enabled */
183 #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */
184 #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
185 #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
186 #define MMUCR_URC 0x0000FC00 /* UTLB access counter */
187 #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */
188 #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
189 #define MMUCR_MASK 0xFCFCFF05
190 #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
192 #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
194 /* ccr register bits */
195 #define CCR_IIX 0x00008000 /* IC index enable */
196 #define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */
197 #define CCR_ICE 0x00000100 /* IC enable */
198 #define CCR_OIX 0x00000080 /* OC index enable */
199 #define CCR_ORA 0x00000020 /* OC RAM enable */
200 #define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */
201 #define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */
202 #define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */
203 #define CCR_OCE 0x00000001 /* OC enable */
204 #define CCR_MASK 0x000089AF
205 #define CCR_RMASK 0x000081A7 /* Read mask */
207 #define MEM_OC_DISABLED 0
208 #define MEM_OC_INDEX0 CCR_ORA
209 #define MEM_OC_INDEX1 CCR_ORA|CCR_OIX
211 void mmu_init(void);
212 void mmu_set_cache_mode( int );
214 #endif
.