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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 422:61a0598e07ff
prev418:b9b14afa0959
next472:8a3ae91eb215
author nkeynes
date Sat Oct 06 09:03:24 2007 +0000 (14 years ago)
permissions -rw-r--r--
last change Fix compilation warnings
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     1 /**
     2  * $Id: sh4.c,v 1.5 2007-10-06 09:03:24 nkeynes Exp $
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "dreamcast.h"
    24 #include "sh4/sh4core.h"
    25 #include "sh4/sh4mmio.h"
    26 #include "sh4/intc.h"
    27 #include "sh4/xltcache.h"
    28 #include "sh4/sh4stat.h"
    29 #include "mem.h"
    30 #include "clock.h"
    31 #include "syscall.h"
    33 #define EXV_EXCEPTION    0x100  /* General exception vector */
    34 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    35 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    37 void sh4_init( void );
    38 void sh4_x86_init( void );
    39 void sh4_reset( void );
    40 void sh4_start( void );
    41 void sh4_stop( void );
    42 void sh4_save_state( FILE *f );
    43 int sh4_load_state( FILE *f );
    45 uint32_t sh4_run_slice( uint32_t );
    46 uint32_t sh4_xlat_run_slice( uint32_t );
    48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    49 				       NULL, sh4_run_slice, sh4_stop,
    50 				       sh4_save_state, sh4_load_state };
    52 struct sh4_registers sh4r;
    53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    54 int sh4_breakpoint_count = 0;
    55 extern char *sh4_main_ram;
    57 void sh4_set_use_xlat( gboolean use )
    58 {
    59     if( use ) {
    60 	xlat_cache_init();
    61 	sh4_x86_init();
    62 	sh4_module.run_time_slice = sh4_xlat_run_slice;
    63     } else {
    64 	sh4_module.run_time_slice = sh4_run_slice;
    65     }
    66 }
    68 void sh4_init(void)
    69 {
    70     register_io_regions( mmio_list_sh4mmio );
    71     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    72     MMU_init();
    73     sh4_reset();
    74 }
    76 void sh4_reset(void)
    77 {
    78     /* zero everything out, for the sake of having a consistent state. */
    79     memset( &sh4r, 0, sizeof(sh4r) );
    81     /* Resume running if we were halted */
    82     sh4r.sh4_state = SH4_STATE_RUNNING;
    84     sh4r.pc    = 0xA0000000;
    85     sh4r.new_pc= 0xA0000002;
    86     sh4r.vbr   = 0x00000000;
    87     sh4r.fpscr = 0x00040001;
    88     sh4r.sr    = 0x700000F0;
    89     sh4r.fr_bank = &sh4r.fr[0][0];
    91     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
    92     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
    94     /* Peripheral modules */
    95     CPG_reset();
    96     INTC_reset();
    97     MMU_reset();
    98     TMU_reset();
    99     SCIF_reset();
   100     sh4_stats_reset();
   101 }
   103 void sh4_stop(void)
   104 {
   106 }
   108 void sh4_save_state( FILE *f )
   109 {
   110     if(	sh4_module.run_time_slice == sh4_xlat_run_slice ) {
   111 	/* If we were running with the translator, update new_pc and in_delay_slot */
   112 	sh4r.new_pc = sh4r.pc+2;
   113 	sh4r.in_delay_slot = FALSE;
   114     }
   116     fwrite( &sh4r, sizeof(sh4r), 1, f );
   117     MMU_save_state( f );
   118     INTC_save_state( f );
   119     TMU_save_state( f );
   120     SCIF_save_state( f );
   121 }
   123 int sh4_load_state( FILE * f )
   124 {
   125     fread( &sh4r, sizeof(sh4r), 1, f );
   126     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
   127     MMU_load_state( f );
   128     INTC_load_state( f );
   129     TMU_load_state( f );
   130     return SCIF_load_state( f );
   131 }
   134 void sh4_set_breakpoint( uint32_t pc, int type )
   135 {
   136     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   137     sh4_breakpoints[sh4_breakpoint_count].type = type;
   138     sh4_breakpoint_count++;
   139 }
   141 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
   142 {
   143     int i;
   145     for( i=0; i<sh4_breakpoint_count; i++ ) {
   146 	if( sh4_breakpoints[i].address == pc && 
   147 	    sh4_breakpoints[i].type == type ) {
   148 	    while( ++i < sh4_breakpoint_count ) {
   149 		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   150 		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   151 	    }
   152 	    sh4_breakpoint_count--;
   153 	    return TRUE;
   154 	}
   155     }
   156     return FALSE;
   157 }
   159 int sh4_get_breakpoint( uint32_t pc )
   160 {
   161     int i;
   162     for( i=0; i<sh4_breakpoint_count; i++ ) {
   163 	if( sh4_breakpoints[i].address == pc )
   164 	    return sh4_breakpoints[i].type;
   165     }
   166     return 0;
   167 }
   169 void sh4_set_pc( int pc )
   170 {
   171     sh4r.pc = pc;
   172     sh4r.new_pc = pc+2;
   173 }
   176 /******************************* Support methods ***************************/
   178 static void sh4_switch_banks( )
   179 {
   180     uint32_t tmp[8];
   182     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   183     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   184     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   185 }
   187 void sh4_write_sr( uint32_t newval )
   188 {
   189     if( (newval ^ sh4r.sr) & SR_RB )
   190         sh4_switch_banks();
   191     sh4r.sr = newval;
   192     sh4r.t = (newval&SR_T) ? 1 : 0;
   193     sh4r.s = (newval&SR_S) ? 1 : 0;
   194     sh4r.m = (newval&SR_M) ? 1 : 0;
   195     sh4r.q = (newval&SR_Q) ? 1 : 0;
   196     intc_mask_changed();
   197 }
   199 uint32_t sh4_read_sr( void )
   200 {
   201     /* synchronize sh4r.sr with the various bitflags */
   202     sh4r.sr &= SR_MQSTMASK;
   203     if( sh4r.t ) sh4r.sr |= SR_T;
   204     if( sh4r.s ) sh4r.sr |= SR_S;
   205     if( sh4r.m ) sh4r.sr |= SR_M;
   206     if( sh4r.q ) sh4r.sr |= SR_Q;
   207     return sh4r.sr;
   208 }
   212 #define RAISE( x, v ) do{			\
   213     if( sh4r.vbr == 0 ) { \
   214         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   215         dreamcast_stop(); return FALSE;	\
   216     } else { \
   217         sh4r.spc = sh4r.pc;	\
   218         sh4r.ssr = sh4_read_sr(); \
   219         sh4r.sgr = sh4r.r[15]; \
   220         MMIO_WRITE(MMU,EXPEVT,x); \
   221         sh4r.pc = sh4r.vbr + v; \
   222         sh4r.new_pc = sh4r.pc + 2; \
   223         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   224 	if( sh4r.in_delay_slot ) { \
   225 	    sh4r.in_delay_slot = 0; \
   226 	    sh4r.spc -= 2; \
   227 	} \
   228     } \
   229     return TRUE; } while(0)
   231 /**
   232  * Raise a general CPU exception for the specified exception code.
   233  * (NOT for TRAPA or TLB exceptions)
   234  */
   235 gboolean sh4_raise_exception( int code )
   236 {
   237     RAISE( code, EXV_EXCEPTION );
   238 }
   240 gboolean sh4_raise_trap( int trap )
   241 {
   242     MMIO_WRITE( MMU, TRA, trap<<2 );
   243     return sh4_raise_exception( EXC_TRAP );
   244 }
   246 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   247     if( sh4r.in_delay_slot ) {
   248 	return sh4_raise_exception(slot_code);
   249     } else {
   250 	return sh4_raise_exception(normal_code);
   251     }
   252 }
   254 gboolean sh4_raise_tlb_exception( int code )
   255 {
   256     RAISE( code, EXV_TLBMISS );
   257 }
   259 void sh4_accept_interrupt( void )
   260 {
   261     uint32_t code = intc_accept_interrupt();
   262     sh4r.ssr = sh4_read_sr();
   263     sh4r.spc = sh4r.pc;
   264     sh4r.sgr = sh4r.r[15];
   265     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   266     MMIO_WRITE( MMU, INTEVT, code );
   267     sh4r.pc = sh4r.vbr + 0x600;
   268     sh4r.new_pc = sh4r.pc + 2;
   269     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   270 }
   272 void signsat48( void )
   273 {
   274     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   275 	sh4r.mac = 0xFFFF800000000000LL;
   276     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   277 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
   278 }
   280 void sh4_fsca( uint32_t anglei, float *fr )
   281 {
   282     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   283     *fr++ = cosf(angle);
   284     *fr = sinf(angle);
   285 }
   287 void sh4_sleep(void)
   288 {
   289     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   290 	sh4r.sh4_state = SH4_STATE_STANDBY;
   291     } else {
   292 	sh4r.sh4_state = SH4_STATE_SLEEP;
   293     }
   294 }
   296 /**
   297  * Compute the matrix tranform of fv given the matrix xf.
   298  * Both fv and xf are word-swapped as per the sh4r.fr banks
   299  */
   300 void sh4_ftrv( float *target, float *xf )
   301 {
   302     float fv[4] = { target[1], target[0], target[3], target[2] };
   303     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
   304 	xf[9]*fv[2] + xf[13]*fv[3];
   305     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   306 	xf[8]*fv[2] + xf[12]*fv[3];
   307     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   308 	xf[11]*fv[2] + xf[15]*fv[3];
   309     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   310 	xf[10]*fv[2] + xf[14]*fv[3];
   311 }
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