4 * This file defines the internal functions exported/used by the SH4 core,
5 * except for disassembly functions defined in sh4dasm.h
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
23 #include <glib/gtypes.h>
33 /* Breakpoint data structure */
34 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
35 extern int sh4_breakpoint_count;
36 extern sh4ptr_t sh4_main_ram;
37 extern gboolean sh4_starting;
40 * Cached direct pointer to the current instruction page. If AT is on, this
41 * is derived from the ITLB, otherwise this will be the entire memory region.
42 * This is actually a fairly useful optimization, as we can make a lot of
43 * assumptions about the "current page" that we can't make in general for
44 * arbitrary virtual addresses.
46 struct sh4_icache_struct {
47 sh4ptr_t page; // Page pointer (NULL if no page)
48 sh4vma_t page_vma; // virtual address of the page.
49 sh4addr_t page_ppa; // physical address of the page
50 uint32_t mask; // page mask
52 extern struct sh4_icache_struct sh4_icache;
55 * Test if a given address is contained in the current icache entry
57 #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask))
59 * Return a pointer for the given vma, under the assumption that it is
60 * actually contained in the current icache entry.
62 #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma))
64 * Return the physical (external) address for the given vma, assuming that it is
65 * actually contained in the current icache entry.
67 #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma))
70 * Return the virtual (vma) address for the first address past the end of the
71 * cache entry. Assumes that there is in fact a current icache entry.
73 #define GET_ICACHE_END() (sh4_icache.page_vma + (~sh4_icache.mask) + 1)
75 /* SH4 module functions */
76 void sh4_init( void );
77 void sh4_reset( void );
79 void sh4_stop( void );
80 uint32_t sh4_run_slice( uint32_t nanos ); // Run single timeslice using emulator
81 uint32_t sh4_xlat_run_slice( uint32_t nanos ); // Run single timeslice using translator
82 uint32_t sh4_sleep_run_slice( uint32_t nanos ); // Run single timeslice while the CPU is asleep
84 /* SH4 peripheral module functions */
85 void CPG_reset( void );
86 void DMAC_reset( void );
87 void DMAC_run_slice( uint32_t );
88 void DMAC_save_state( FILE * );
89 int DMAC_load_state( FILE * );
90 void INTC_reset( void );
91 void INTC_save_state( FILE *f );
92 int INTC_load_state( FILE *f );
93 void MMU_init( void );
94 void MMU_reset( void );
95 void MMU_save_state( FILE *f );
96 int MMU_load_state( FILE *f );
98 void SCIF_reset( void );
99 void SCIF_run_slice( uint32_t );
100 void SCIF_save_state( FILE *f );
101 int SCIF_load_state( FILE *f );
102 void SCIF_update_line_speed(void);
103 void TMU_init( void );
104 void TMU_reset( void );
105 void TMU_run_slice( uint32_t );
106 void TMU_save_state( FILE * );
107 int TMU_load_state( FILE * );
108 void TMU_update_clocks( void );
110 /* SH4 instruction support methods */
111 void sh4_sleep( void );
112 void sh4_fsca( uint32_t angle, float *fr );
113 void sh4_ftrv( float *fv );
114 uint32_t sh4_read_sr(void);
115 void sh4_write_sr(uint32_t val);
116 void sh4_write_fpscr(uint32_t val);
117 void sh4_switch_fr_banks(void);
118 void signsat48(void);
119 gboolean sh4_has_page( sh4vma_t vma );
122 #define MMU_VMA_ERROR 0x80000000
124 * Update the sh4_icache structure to contain the specified vma. If the vma
125 * cannot be resolved, an MMU exception is raised and the function returns
126 * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly.
127 * Note: If the vma resolves to a non-memory area, sh4_icache will be
128 * invalidated, but the function will still return TRUE.
129 * @return FALSE if an MMU exception was raised, otherwise TRUE.
131 gboolean mmu_update_icache( sh4vma_t addr );
134 * Resolve a virtual address through the TLB for a read operation, returning
135 * the resultant P4 or external address. If the resolution fails, the
136 * appropriate MMU exception is raised and the value MMU_VMA_ERROR is returned.
137 * @return An external address (0x00000000-0x1FFFFFFF), a P4 address
138 * (0xE0000000 - 0xFFFFFFFF), or MMU_VMA_ERROR.
140 sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr );
141 sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr );
142 sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t addr );
144 int64_t sh4_read_quad( sh4addr_t addr );
145 int32_t sh4_read_long( sh4addr_t addr );
146 int32_t sh4_read_word( sh4addr_t addr );
147 int32_t sh4_read_byte( sh4addr_t addr );
148 void sh4_write_quad( sh4addr_t addr, uint64_t val );
149 void sh4_write_long( sh4addr_t addr, uint32_t val );
150 void sh4_write_word( sh4addr_t addr, uint32_t val );
151 void sh4_write_byte( sh4addr_t addr, uint32_t val );
152 int32_t sh4_read_phys_word( sh4addr_t addr );
153 gboolean sh4_flush_store_queue( sh4addr_t addr );
156 #define EXC_POWER_RESET 0x000 /* reset vector */
157 #define EXC_MANUAL_RESET 0x020 /* reset vector */
158 #define EXC_TLB_MISS_READ 0x040 /* TLB vector */
159 #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */
160 #define EXC_INIT_PAGE_WRITE 0x080
161 #define EXC_TLB_PROT_READ 0x0A0
162 #define EXC_TLB_PROT_WRITE 0x0C0
163 #define EXC_DATA_ADDR_READ 0x0E0
164 #define EXC_DATA_ADDR_WRITE 0x100
165 #define EXC_TLB_MULTI_HIT 0x140
166 #define EXC_SLOT_ILLEGAL 0x1A0
167 #define EXC_ILLEGAL 0x180
168 #define EXC_TRAP 0x160
169 #define EXC_FPU_DISABLED 0x800
170 #define EXC_SLOT_FPU_DISABLED 0x820
172 #define EXV_EXCEPTION 0x100 /* General exception vector */
173 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
174 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
176 gboolean sh4_raise_exception( int );
177 gboolean sh4_raise_reset( int );
178 gboolean sh4_raise_trap( int );
179 gboolean sh4_raise_slot_exception( int, int );
180 gboolean sh4_raise_tlb_exception( int );
181 void sh4_accept_interrupt( void );
183 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
184 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
185 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
186 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
187 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
188 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
189 #define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n))))
191 /* Status Register (SR) bits */
192 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
193 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
194 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
195 #define SR_FD 0x00008000 /* FPU disable */
196 #define SR_M 0x00000200
197 #define SR_Q 0x00000100
198 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
199 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
200 #define SR_T 0x00000001 /* True/false or carry/borrow */
201 #define SR_MASK 0x700083F3
202 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
203 #define SR_MDRB 0x60000000 /* MD+RB mask for convenience */
205 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
206 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
207 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
209 #define FPSCR_FR 0x00200000 /* FPU register bank */
210 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
211 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
212 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
213 #define FPSCR_CAUSE 0x0003F000
214 #define FPSCR_ENABLE 0x00000F80
215 #define FPSCR_FLAG 0x0000007C
216 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
218 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
219 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
220 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
222 #define FR(x) sh4r.fr[0][(x)^1]
223 #define DRF(x) *((double *)&sh4r.fr[0][(x)<<1])
224 #define XF(x) sh4r.fr[1][(x)^1]
225 #define XDR(x) *((double *)&sh4r.fr[1][(x)<<1])
226 #define DRb(x,b) *((double *)&sh4r.fr[b][(x)<<1])
227 #define DR(x) *((double *)&sh4r.fr[x&1][x&0x0E])
228 #define FPULf (sh4r.fpul.f)
229 #define FPULi (sh4r.fpul.i)
231 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
.