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lxdream.org :: lxdream/src/sh4/sh4core.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 951:63483914846f
prev948:545c85cc56f1
next1067:d3c00ffccfcd
author nkeynes
date Wed Jan 07 05:45:15 2009 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Tidy up exceptions+resets
Implement manual reset on general exception when SR.BL == 1
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <assert.h>
    22 #include <math.h>
    23 #include "dream.h"
    24 #include "dreamcast.h"
    25 #include "eventq.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/sh4stat.h"
    32 #include "sh4/mmu.h"
    34 #define SH4_CALLTRACE 1
    36 #define MAX_INT 0x7FFFFFFF
    37 #define MIN_INT 0x80000000
    38 #define MAX_INTF 2147483647.0
    39 #define MIN_INTF -2147483648.0
    41 /********************** SH4 Module Definition ****************************/
    43 uint32_t sh4_emulate_run_slice( uint32_t nanosecs ) 
    44 {
    45     int i;
    47     if( sh4_breakpoint_count == 0 ) {
    48 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    49 	    if( SH4_EVENT_PENDING() ) {
    50 		if( sh4r.event_types & PENDING_EVENT ) {
    51 		    event_execute();
    52 		}
    53 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    54 		if( sh4r.event_types & PENDING_IRQ ) {
    55 		    sh4_accept_interrupt();
    56 		}
    57 	    }
    58 	    if( !sh4_execute_instruction() ) {
    59 		break;
    60 	    }
    61 	}
    62     } else {
    63 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    64 	    if( SH4_EVENT_PENDING() ) {
    65 		if( sh4r.event_types & PENDING_EVENT ) {
    66 		    event_execute();
    67 		}
    68 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    69 		if( sh4r.event_types & PENDING_IRQ ) {
    70 		    sh4_accept_interrupt();
    71 		}
    72 	    }
    74 	    if( !sh4_execute_instruction() )
    75 		break;
    76 #ifdef ENABLE_DEBUG_MODE
    77 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    78 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    79 		    break;
    80 		}
    81 	    }
    82 	    if( i != sh4_breakpoint_count ) {
    83 	    	sh4_core_exit( CORE_EXIT_BREAKPOINT );
    84 	    }
    85 #endif	
    86 	}
    87     }
    89     /* If we aborted early, but the cpu is still technically running,
    90      * we're doing a hard abort - cut the timeslice back to what we
    91      * actually executed
    92      */
    93     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
    94 	nanosecs = sh4r.slice_cycle;
    95     }
    96     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
    97 	TMU_run_slice( nanosecs );
    98 	SCIF_run_slice( nanosecs );
    99     }
   100     return nanosecs;
   101 }
   103 /********************** SH4 emulation core  ****************************/
   105 #if(SH4_CALLTRACE == 1)
   106 #define MAX_CALLSTACK 32
   107 static struct call_stack {
   108     sh4addr_t call_addr;
   109     sh4addr_t target_addr;
   110     sh4addr_t stack_pointer;
   111 } call_stack[MAX_CALLSTACK];
   113 static int call_stack_depth = 0;
   114 int sh4_call_trace_on = 0;
   116 static inline void trace_call( sh4addr_t source, sh4addr_t dest ) 
   117 {
   118     if( call_stack_depth < MAX_CALLSTACK ) {
   119 	call_stack[call_stack_depth].call_addr = source;
   120 	call_stack[call_stack_depth].target_addr = dest;
   121 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   122     }
   123     call_stack_depth++;
   124 }
   126 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
   127 {
   128     if( call_stack_depth > 0 ) {
   129 	call_stack_depth--;
   130     }
   131 }
   133 void fprint_stack_trace( FILE *f )
   134 {
   135     int i = call_stack_depth -1;
   136     if( i >= MAX_CALLSTACK )
   137 	i = MAX_CALLSTACK - 1;
   138     for( ; i >= 0; i-- ) {
   139 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   140 		 (call_stack_depth - i), call_stack[i].call_addr,
   141 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   142     }
   143 }
   145 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   146 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   147 #else
   148 #define TRACE_CALL( dest, rts ) 
   149 #define TRACE_RETURN( source, dest )
   150 #endif
   152 static gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
   153     if( sh4r.in_delay_slot ) {
   154         sh4_raise_exception(slot_code);
   155     } else {
   156         sh4_raise_exception(normal_code);
   157     }
   158     return TRUE;
   159 }
   162 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) { return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL ); }
   163 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   164 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   165 #define CHECKRALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_READ ); return TRUE; }
   166 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   167 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   168 #define CHECKWALIGN64(addr) if( (addr)&0x07 ) { sh4_raise_exception( EXC_DATA_ADDR_WRITE ); return TRUE; }
   170 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   171 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }
   172 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { sh4_raise_exception(EXC_SLOT_ILLEGAL); return TRUE; }
   174 #define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)
   175 #define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)
   177 #ifdef HAVE_FRAME_ADDRESS
   178 static FASTCALL __attribute__((noinline)) void *__first_arg(void *a, void *b) { return a; }
   179 #define INIT_EXCEPTIONS(label) goto *__first_arg(&&fnstart,&&label); fnstart:
   180 #define MEM_READ_BYTE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte)((addr), &&except)
   181 #define MEM_READ_WORD( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_word)((addr), &&except)
   182 #define MEM_READ_LONG( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_long)((addr), &&except)
   183 #define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)
   184 #define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)
   185 #define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)
   186 #define MEM_PREFETCH( addr ) ((mem_prefetch_exc_fn_t)ADDRSPACE[(addr)>>12]->prefetch)((addr), &&except)
   187 #else
   188 #define INIT_EXCEPTIONS(label)
   189 #define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)
   190 #define MEM_READ_WORD( addr, val ) val = ADDRSPACE[(addr)>>12]->read_word(addr)
   191 #define MEM_READ_LONG( addr, val ) val = ADDRSPACE[(addr)>>12]->read_long(addr)
   192 #define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)
   193 #define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)
   194 #define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)
   195 #define MEM_PREFETCH( addr ) ADDRSPACE[(addr)>>12]->prefetch(addr)
   196 #endif
   198 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   200 #define MEM_FP_READ( addr, reg ) \
   201     if( IS_FPU_DOUBLESIZE() ) { \
   202 	CHECKRALIGN64(addr); \
   203         if( reg & 1 ) { \
   204             MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \
   205             MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
   206         } else { \
   207             MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   208             MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   209 	} \
   210     } else { \
   211         CHECKRALIGN32(addr); \
   212         MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   213     }
   214 #define MEM_FP_WRITE( addr, reg ) \
   215     if( IS_FPU_DOUBLESIZE() ) { \
   216         CHECKWALIGN64(addr); \
   217         if( reg & 1 ) { \
   218 	    MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \
   219 	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
   220         } else { \
   221 	    MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \
   222 	    MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
   223 	} \
   224     } else { \
   225     	CHECKWALIGN32(addr); \
   226         MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \
   227     }
   229 #define UNDEF(ir)
   230 #define UNIMP(ir)
   232 /**
   233  * Perform instruction-completion following core exit of a partially completed
   234  * instruction. NOTE: This is only allowed on memory writes, operation is not
   235  * guaranteed in any other case.
   236  */
   237 void sh4_finalize_instruction( void )
   238 {
   239     unsigned short ir;
   240     uint32_t tmp;
   242     assert( IS_IN_ICACHE(sh4r.pc) );
   243     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   245     /**
   246      * Note - we can't take an exit on a control transfer instruction itself,
   247      * which means the exit must have happened in the delay slot. So for these
   248      * cases, finalize the delay slot instruction, and re-execute the control transfer.
   249      *
   250      * For delay slots which modify the argument used in the branch instruction,
   251      * we pretty much just assume that that can't have already happened in an exit case.
   252      */
   254 %%
   255 BRA disp {: 
   256     sh4r.pc += 2; 
   257     sh4_finalize_instruction(); 
   258     sh4r.pc += disp;
   259     sh4r.slice_cycle += sh4_cpu_period;
   260 :}
   261 BRAF Rn {: 
   262     sh4r.pc += 2; 
   263     tmp = sh4r.r[Rn];
   264     sh4_finalize_instruction(); 
   265     sh4r.pc += tmp;
   266     sh4r.slice_cycle += sh4_cpu_period;
   267 :}
   268 BSR disp {: 
   269     /* Note: PR is already set */ 
   270     sh4r.pc += 2;
   271     sh4_finalize_instruction();
   272     sh4r.pc += disp;
   273     sh4r.slice_cycle += sh4_cpu_period;
   274 :}
   275 BSRF Rn {:
   276     /* Note: PR is already set */ 
   277     sh4r.pc += 2;
   278     tmp = sh4r.r[Rn];
   279     sh4_finalize_instruction();
   280     sh4r.pc += tmp;
   281     sh4r.slice_cycle += sh4_cpu_period;
   282 :}
   283 BF/S disp {: 
   284     sh4r.pc += 2;
   285     sh4_finalize_instruction();
   286     if( !sh4r.t ) {
   287         sh4r.pc += disp;
   288     }
   289     sh4r.slice_cycle += sh4_cpu_period;
   290 :}
   291 BT/S disp {: 
   292     sh4r.pc += 2;
   293     sh4_finalize_instruction();
   294     if( sh4r.t ) {
   295         sh4r.pc += disp;
   296     }
   297     sh4r.slice_cycle += sh4_cpu_period;
   298 :}
   299 JMP @Rn {:
   300     sh4r.pc += 2;
   301     tmp = sh4r.r[Rn];
   302     sh4_finalize_instruction();
   303     sh4r.pc = tmp;
   304     sh4r.new_pc = tmp + 2;
   305     sh4r.slice_cycle += 2*sh4_cpu_period;
   306     return;
   307 :}
   308 JSR @Rn {: 
   309     /* Note: PR is already set */ 
   310     sh4r.pc += 2;
   311     tmp = sh4r.r[Rn];
   312     sh4_finalize_instruction();
   313     sh4r.pc = tmp;
   314     sh4r.new_pc = tmp + 2;
   315     sh4r.slice_cycle += 2*sh4_cpu_period;
   316     return;
   317 :}
   318 RTS {: 
   319     sh4r.pc += 2;
   320     sh4_finalize_instruction();
   321     sh4r.pc = sh4r.pr;
   322     sh4r.new_pc = sh4r.pr + 2;
   323     sh4r.slice_cycle += 2*sh4_cpu_period;
   324     return;
   325 :}
   326 RTE {: 
   327     /* SR is already set */
   328     sh4r.pc += 2;
   329     sh4_finalize_instruction();
   330     sh4r.pc = sh4r.spc;
   331     sh4r.new_pc = sh4r.pr + 2;
   332     sh4r.slice_cycle += 2*sh4_cpu_period;
   333     return;
   334 :}
   335 MOV.B Rm, @-Rn {: sh4r.r[Rn]--; :}
   336 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; :}
   337 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; :}
   338 MOV.B @Rm+, Rn {: sh4r.r[Rm] ++; :}
   339 MOV.W @Rm+, Rn {: sh4r.r[Rm] += 2; :}
   340 MOV.L @Rm+, Rn {: sh4r.r[Rm] += 4; :}
   341 %%
   342     sh4r.pc += 2;
   343     sh4r.new_pc = sh4r.pc+2;
   344     sh4r.slice_cycle += sh4_cpu_period;
   345 }
   347 #undef UNDEF(ir)
   348 #undef UNIMP(ir)
   350 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   351 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)
   354 gboolean sh4_execute_instruction( void )
   355 {
   356     uint32_t pc;
   357     unsigned short ir;
   358     uint32_t tmp;
   359     float ftmp;
   360     double dtmp;
   361     int64_t memtmp; // temporary holder for memory reads
   363     INIT_EXCEPTIONS(except)
   365 #define R0 sh4r.r[0]
   366     pc = sh4r.pc;
   367     if( pc > 0xFFFFFF00 ) {
   368 	/* SYSCALL Magic */
   369 	syscall_invoke( pc );
   370 	sh4r.in_delay_slot = 0;
   371 	pc = sh4r.pc = sh4r.pr;
   372 	sh4r.new_pc = sh4r.pc + 2;
   373         return TRUE;
   374     }
   375     CHECKRALIGN16(pc);
   377 #ifdef ENABLE_SH4STATS
   378     sh4_stats_add_by_pc(sh4r.pc);
   379 #endif
   381     /* Read instruction */
   382     if( !IS_IN_ICACHE(pc) ) {
   383 	if( !mmu_update_icache(pc) ) {
   384 	    // Fault - look for the fault handler
   385 	    if( !mmu_update_icache(sh4r.pc) ) {
   386 		// double fault - halt
   387 		ERROR( "Double fault - halting" );
   388 		sh4_core_exit(CORE_EXIT_HALT);
   389 		return FALSE;
   390 	    }
   391 	}
   392 	pc = sh4r.pc;
   393     }
   394     assert( IS_IN_ICACHE(pc) );
   395     ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
   397     /* FIXME: This is a bit of a hack, but the PC of the delay slot should not
   398      * be visible until after the instruction has executed (for exception 
   399      * correctness)
   400      */
   401     if( sh4r.in_delay_slot ) {
   402     	sh4r.pc -= 2;
   403     }
   404 %%
   405 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
   406 AND #imm, R0 {: R0 &= imm; :}
   407  AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
   408 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
   409 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
   410 OR #imm, R0  {: R0 |= imm; :}
   411  OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
   412 TAS.B @Rn {:
   413     MEM_READ_BYTE( sh4r.r[Rn], tmp );
   414     sh4r.t = ( tmp == 0 ? 1 : 0 );
   415     MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
   416 :}
   417 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
   418 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
   419  TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
   420 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
   421 XOR #imm, R0 {: R0 ^= imm; :}
   422  XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
   423 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
   425 ROTL Rn {:
   426     sh4r.t = sh4r.r[Rn] >> 31;
   427     sh4r.r[Rn] <<= 1;
   428     sh4r.r[Rn] |= sh4r.t;
   429 :}
   430 ROTR Rn {:
   431     sh4r.t = sh4r.r[Rn] & 0x00000001;
   432     sh4r.r[Rn] >>= 1;
   433     sh4r.r[Rn] |= (sh4r.t << 31);
   434 :}
   435 ROTCL Rn {:
   436     tmp = sh4r.r[Rn] >> 31;
   437     sh4r.r[Rn] <<= 1;
   438     sh4r.r[Rn] |= sh4r.t;
   439     sh4r.t = tmp;
   440 :}
   441 ROTCR Rn {:
   442     tmp = sh4r.r[Rn] & 0x00000001;
   443     sh4r.r[Rn] >>= 1;
   444     sh4r.r[Rn] |= (sh4r.t << 31 );
   445     sh4r.t = tmp;
   446 :}
   447 SHAD Rm, Rn {:
   448     tmp = sh4r.r[Rm];
   449     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   450     else if( (tmp & 0x1F) == 0 )  
   451         sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
   452     else 
   453 	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
   454 :}
   455 SHLD Rm, Rn {:
   456     tmp = sh4r.r[Rm];
   457     if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
   458     else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
   459     else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
   460 :}
   461 SHAL Rn {:
   462     sh4r.t = sh4r.r[Rn] >> 31;
   463     sh4r.r[Rn] <<= 1;
   464 :}
   465 SHAR Rn {:
   466     sh4r.t = sh4r.r[Rn] & 0x00000001;
   467     sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   468 :}
   469 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
   470 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
   471 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
   472 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
   473 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
   474 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
   475 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
   476 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
   478 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
   479 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
   480 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
   481 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
   482 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
   483 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
   485 CLRT {: sh4r.t = 0; :}
   486 SETT {: sh4r.t = 1; :}
   487 CLRMAC {: sh4r.mac = 0; :}
   488 LDTLB {: MMU_ldtlb(); :}
   489 CLRS {: sh4r.s = 0; :}
   490 SETS {: sh4r.s = 1; :}
   491 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
   492 NOP {: /* NOP */ :}
   494 PREF @Rn {:
   495     MEM_PREFETCH(sh4r.r[Rn]);
   496 :}
   497 OCBI @Rn {: :}
   498 OCBP @Rn {: :}
   499 OCBWB @Rn {: :}
   500 MOVCA.L R0, @Rn {:
   501     tmp = sh4r.r[Rn];
   502     CHECKWALIGN32(tmp);
   503     MEM_WRITE_LONG( tmp, R0 );
   504 :}
   505 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
   506 MOV.W Rm, @(R0, Rn) {: 
   507     CHECKWALIGN16( R0 + sh4r.r[Rn] );
   508     MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   509 :}
   510 MOV.L Rm, @(R0, Rn) {:
   511     CHECKWALIGN32( R0 + sh4r.r[Rn] );
   512     MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   513 :}
   514 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
   515 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
   516     MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   517 :}
   518 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
   519     MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
   520 :}
   521 MOV.L Rm, @(disp, Rn) {:
   522     tmp = sh4r.r[Rn] + disp;
   523     CHECKWALIGN32( tmp );
   524     MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   525 :}
   526 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
   527 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
   528 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
   529  MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
   530  MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
   531  MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
   532 MOV.L @(disp, Rm), Rn {:
   533     tmp = sh4r.r[Rm] + disp;
   534     CHECKRALIGN32( tmp );
   535     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   536 :}
   537 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
   538  MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
   539  MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
   540 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
   541  MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
   542  MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
   543  MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
   544 MOV.L @(disp, PC), Rn {:
   545     CHECKSLOTILLEGAL();
   546     tmp = (pc&0xFFFFFFFC) + disp + 4;
   547     MEM_READ_LONG( tmp, sh4r.r[Rn] );
   548 :}
   549 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
   550 MOV.W R0, @(disp, GBR) {:
   551     tmp = sh4r.gbr + disp;
   552     CHECKWALIGN16( tmp );
   553     MEM_WRITE_WORD( tmp, R0 );
   554 :}
   555 MOV.L R0, @(disp, GBR) {:
   556     tmp = sh4r.gbr + disp;
   557     CHECKWALIGN32( tmp );
   558     MEM_WRITE_LONG( tmp, R0 );
   559 :}
   560  MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
   561 MOV.W @(disp, GBR), R0 {: 
   562     tmp = sh4r.gbr + disp;
   563     CHECKRALIGN16( tmp );
   564     MEM_READ_WORD( tmp, R0 );
   565 :}
   566 MOV.L @(disp, GBR), R0 {:
   567     tmp = sh4r.gbr + disp;
   568     CHECKRALIGN32( tmp );
   569     MEM_READ_LONG( tmp, R0 );
   570 :}
   571 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
   572 MOV.W R0, @(disp, Rn) {: 
   573     tmp = sh4r.r[Rn] + disp;
   574     CHECKWALIGN16( tmp );
   575     MEM_WRITE_WORD( tmp, R0 );
   576 :}
   577  MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
   578 MOV.W @(disp, Rm), R0 {: 
   579     tmp = sh4r.r[Rm] + disp;
   580     CHECKRALIGN16( tmp );
   581     MEM_READ_WORD( tmp, R0 );
   582 :}
   583 MOV.W @(disp, PC), Rn {:
   584     CHECKSLOTILLEGAL();
   585     tmp = pc + 4 + disp;
   586     MEM_READ_WORD( tmp, sh4r.r[Rn] );
   587 :}
   588 MOVA @(disp, PC), R0 {:
   589     CHECKSLOTILLEGAL();
   590     R0 = (pc&0xFFFFFFFC) + disp + 4;
   591 :}
   592 MOV #imm, Rn {:  sh4r.r[Rn] = imm; :}
   594 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
   595 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
   596 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
   597 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
   598 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
   599  FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
   600 FMOV FRm, FRn {: 
   601     if( IS_FPU_DOUBLESIZE() )
   602 	DR(FRn) = DR(FRm);
   603     else
   604 	FR(FRn) = FR(FRm);
   605 :}
   607 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
   608 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
   609 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   610 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
   611 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
   612 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
   613 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
   614 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
   615 CMP/STR Rm, Rn {: 
   616     /* set T = 1 if any byte in RM & RN is the same */
   617     tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   618     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   619              (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   620 :}
   622 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
   623 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
   624 ADDC Rm, Rn {:
   625     tmp = sh4r.r[Rn];
   626     sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   627     sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   628 :}
   629 ADDV Rm, Rn {:
   630     tmp = sh4r.r[Rn] + sh4r.r[Rm];
   631     sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   632     sh4r.r[Rn] = tmp;
   633 :}
   634 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
   635 DIV0S Rm, Rn {: 
   636     sh4r.q = sh4r.r[Rn]>>31;
   637     sh4r.m = sh4r.r[Rm]>>31;
   638     sh4r.t = sh4r.q ^ sh4r.m;
   639 :}
   640 DIV1 Rm, Rn {:
   641     /* This is derived from the sh4 manual with some simplifications */
   642     uint32_t tmp0, tmp1, tmp2, dir;
   644     dir = sh4r.q ^ sh4r.m;
   645     sh4r.q = (sh4r.r[Rn] >> 31);
   646     tmp2 = sh4r.r[Rm];
   647     sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   648     tmp0 = sh4r.r[Rn];
   649     if( dir ) {
   650          sh4r.r[Rn] += tmp2;
   651          tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   652     } else {
   653          sh4r.r[Rn] -= tmp2;
   654          tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   655     }
   656     sh4r.q ^= sh4r.m ^ tmp1;
   657     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   658 :}
   659 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
   660 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
   661 DT Rn {:
   662     sh4r.r[Rn] --;
   663     sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   664 :}
   665 MAC.W @Rm+, @Rn+ {:
   666     int32_t stmp;
   667     if( Rm == Rn ) {
   668 	CHECKRALIGN16(sh4r.r[Rn]);
   669 	MEM_READ_WORD( sh4r.r[Rn], tmp );
   670 	stmp = SIGNEXT16(tmp);
   671 	MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
   672 	stmp *= SIGNEXT16(tmp);
   673 	sh4r.r[Rn] += 4;
   674     } else {
   675 	CHECKRALIGN16( sh4r.r[Rn] );
   676 	CHECKRALIGN16( sh4r.r[Rm] );
   677 	MEM_READ_WORD(sh4r.r[Rn], tmp);
   678 	stmp = SIGNEXT16(tmp);
   679 	MEM_READ_WORD(sh4r.r[Rm], tmp);
   680 	stmp = stmp * SIGNEXT16(tmp);
   681 	sh4r.r[Rn] += 2;
   682 	sh4r.r[Rm] += 2;
   683     }
   684     if( sh4r.s ) {
   685 	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
   686 	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
   687 	    sh4r.mac = 0x000000017FFFFFFFLL;
   688 	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
   689 	    sh4r.mac = 0x0000000180000000LL;
   690 	} else {
   691 	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   692 		((uint32_t)(sh4r.mac + stmp));
   693 	}
   694     } else {
   695 	sh4r.mac += SIGNEXT32(stmp);
   696     }
   697 :}
   698 MAC.L @Rm+, @Rn+ {:
   699     int64_t tmpl;
   700     if( Rm == Rn ) {
   701 	CHECKRALIGN32( sh4r.r[Rn] );
   702 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   703 	tmpl = SIGNEXT32(tmp);
   704 	MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
   705 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   706 	sh4r.r[Rn] += 8;
   707     } else {
   708 	CHECKRALIGN32( sh4r.r[Rm] );
   709 	CHECKRALIGN32( sh4r.r[Rn] );
   710 	MEM_READ_LONG(sh4r.r[Rn], tmp);
   711 	tmpl = SIGNEXT32(tmp);
   712 	MEM_READ_LONG(sh4r.r[Rm], tmp);
   713 	tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
   714 	sh4r.r[Rn] += 4;
   715 	sh4r.r[Rm] += 4;
   716     }
   717     if( sh4r.s ) {
   718         /* 48-bit Saturation. Yuch */
   719         if( tmpl < (int64_t)0xFFFF800000000000LL )
   720             tmpl = 0xFFFF800000000000LL;
   721         else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   722             tmpl = 0x00007FFFFFFFFFFFLL;
   723     }
   724     sh4r.mac = tmpl;
   725 :}
   726 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   727                         (sh4r.r[Rm] * sh4r.r[Rn]); :}
   728 MULU.W Rm, Rn {:
   729     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   730                (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   731 :}
   732 MULS.W Rm, Rn {:
   733     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   734                (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   735 :}
   736 NEGC Rm, Rn {:
   737     tmp = 0 - sh4r.r[Rm];
   738     sh4r.r[Rn] = tmp - sh4r.t;
   739     sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
   740 :}
   741 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
   742 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
   743 SUBC Rm, Rn {: 
   744     tmp = sh4r.r[Rn];
   745     sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   746     sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   747 :}
   749 BRAF Rn {:
   750      CHECKSLOTILLEGAL();
   751      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   752      sh4r.in_delay_slot = 1;
   753      sh4r.pc = sh4r.new_pc;
   754      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   755      return TRUE;
   756 :}
   757 BSRF Rn {:
   758      CHECKSLOTILLEGAL();
   759      CHECKDEST( pc + 4 + sh4r.r[Rn] );
   760      sh4r.in_delay_slot = 1;
   761      sh4r.pr = sh4r.pc + 4;
   762      sh4r.pc = sh4r.new_pc;
   763      sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   764      TRACE_CALL( pc, sh4r.new_pc );
   765      return TRUE;
   766 :}
   767 BT disp {:
   768     CHECKSLOTILLEGAL();
   769     if( sh4r.t ) {
   770         CHECKDEST( sh4r.pc + disp + 4 )
   771         sh4r.pc += disp + 4;
   772         sh4r.new_pc = sh4r.pc + 2;
   773         return TRUE;
   774     }
   775 :}
   776 BF disp {:
   777     CHECKSLOTILLEGAL();
   778     if( !sh4r.t ) {
   779         CHECKDEST( sh4r.pc + disp + 4 )
   780         sh4r.pc += disp + 4;
   781         sh4r.new_pc = sh4r.pc + 2;
   782         return TRUE;
   783     }
   784 :}
   785 BT/S disp {:
   786     CHECKSLOTILLEGAL();
   787     if( sh4r.t ) {
   788         CHECKDEST( sh4r.pc + disp + 4 )
   789         sh4r.in_delay_slot = 1;
   790         sh4r.pc = sh4r.new_pc;
   791         sh4r.new_pc = pc + disp + 4;
   792         sh4r.in_delay_slot = 1;
   793         return TRUE;
   794     }
   795 :}
   796 BF/S disp {:
   797     CHECKSLOTILLEGAL();
   798     if( !sh4r.t ) {
   799         CHECKDEST( sh4r.pc + disp + 4 )
   800         sh4r.in_delay_slot = 1;
   801         sh4r.pc = sh4r.new_pc;
   802         sh4r.new_pc = pc + disp + 4;
   803         return TRUE;
   804     }
   805 :}
   806 BRA disp {:
   807     CHECKSLOTILLEGAL();
   808     CHECKDEST( sh4r.pc + disp + 4 );
   809     sh4r.in_delay_slot = 1;
   810     sh4r.pc = sh4r.new_pc;
   811     sh4r.new_pc = pc + 4 + disp;
   812     return TRUE;
   813 :}
   814 BSR disp {:
   815     CHECKDEST( sh4r.pc + disp + 4 );
   816     CHECKSLOTILLEGAL();
   817     sh4r.in_delay_slot = 1;
   818     sh4r.pr = pc + 4;
   819     sh4r.pc = sh4r.new_pc;
   820     sh4r.new_pc = pc + 4 + disp;
   821     TRACE_CALL( pc, sh4r.new_pc );
   822     return TRUE;
   823 :}
   824 TRAPA #imm {:
   825     CHECKSLOTILLEGAL();
   826     sh4r.pc += 2;
   827     sh4_raise_trap( imm );
   828     return TRUE;
   829 :}
   830 RTS {: 
   831     CHECKSLOTILLEGAL();
   832     CHECKDEST( sh4r.pr );
   833     sh4r.in_delay_slot = 1;
   834     sh4r.pc = sh4r.new_pc;
   835     sh4r.new_pc = sh4r.pr;
   836     TRACE_RETURN( pc, sh4r.new_pc );
   837     return TRUE;
   838 :}
   839 SLEEP {:
   840     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   841 	sh4r.sh4_state = SH4_STATE_STANDBY;
   842     } else {
   843 	sh4r.sh4_state = SH4_STATE_SLEEP;
   844     }
   845     return FALSE; /* Halt CPU */
   846 :}
   847 RTE {:
   848     CHECKPRIV();
   849     CHECKDEST( sh4r.spc );
   850     CHECKSLOTILLEGAL();
   851     sh4r.in_delay_slot = 1;
   852     sh4r.pc = sh4r.new_pc;
   853     sh4r.new_pc = sh4r.spc;
   854     sh4_write_sr( sh4r.ssr );
   855     return TRUE;
   856 :}
   857 JMP @Rn {:
   858     CHECKDEST( sh4r.r[Rn] );
   859     CHECKSLOTILLEGAL();
   860     sh4r.in_delay_slot = 1;
   861     sh4r.pc = sh4r.new_pc;
   862     sh4r.new_pc = sh4r.r[Rn];
   863     return TRUE;
   864 :}
   865 JSR @Rn {:
   866     CHECKDEST( sh4r.r[Rn] );
   867     CHECKSLOTILLEGAL();
   868     sh4r.in_delay_slot = 1;
   869     sh4r.pc = sh4r.new_pc;
   870     sh4r.new_pc = sh4r.r[Rn];
   871     sh4r.pr = pc + 4;
   872     TRACE_CALL( pc, sh4r.new_pc );
   873     return TRUE;
   874 :}
   875 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
   876 STS.L MACH, @-Rn {:
   877     CHECKWALIGN32( sh4r.r[Rn] );
   878     MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
   879     sh4r.r[Rn] -= 4;
   880 :}
   881 STC.L SR, @-Rn {:
   882     CHECKPRIV();
   883     CHECKWALIGN32( sh4r.r[Rn] );
   884     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
   885     sh4r.r[Rn] -= 4;
   886 :}
   887 LDS.L @Rm+, MACH {:
   888     CHECKRALIGN32( sh4r.r[Rm] );
   889     MEM_READ_LONG(sh4r.r[Rm], tmp);
   890     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   891 	(((uint64_t)tmp)<<32);
   892     sh4r.r[Rm] += 4;
   893 :}
   894 LDC.L @Rm+, SR {:
   895     CHECKSLOTILLEGAL();
   896     CHECKPRIV();
   897     CHECKWALIGN32( sh4r.r[Rm] );
   898     MEM_READ_LONG(sh4r.r[Rm], tmp);
   899     sh4_write_sr( tmp );
   900     sh4r.r[Rm] +=4;
   901 :}
   902 LDS Rm, MACH {:
   903     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   904                (((uint64_t)sh4r.r[Rm])<<32);
   905 :}
   906 LDC Rm, SR {:
   907     CHECKSLOTILLEGAL();
   908     CHECKPRIV();
   909     sh4_write_sr( sh4r.r[Rm] );
   910 :}
   911 LDC Rm, SGR {:
   912     CHECKPRIV();
   913     sh4r.sgr = sh4r.r[Rm];
   914 :}
   915 LDC.L @Rm+, SGR {:
   916     CHECKPRIV();
   917     CHECKRALIGN32( sh4r.r[Rm] );
   918     MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
   919     sh4r.r[Rm] +=4;
   920 :}
   921 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
   922 STS.L MACL, @-Rn {:
   923     CHECKWALIGN32( sh4r.r[Rn] );
   924     MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
   925     sh4r.r[Rn] -= 4;
   926 :}
   927 STC.L GBR, @-Rn {:
   928     CHECKWALIGN32( sh4r.r[Rn] );
   929     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
   930     sh4r.r[Rn] -= 4;
   931 :}
   932 LDS.L @Rm+, MACL {:
   933     CHECKRALIGN32( sh4r.r[Rm] );
   934     MEM_READ_LONG(sh4r.r[Rm], tmp);
   935     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   936                (uint64_t)((uint32_t)tmp);
   937     sh4r.r[Rm] += 4;
   938 :}
   939 LDC.L @Rm+, GBR {:
   940     CHECKRALIGN32( sh4r.r[Rm] );
   941     MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
   942     sh4r.r[Rm] +=4;
   943 :}
   944 LDS Rm, MACL {:
   945     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   946                (uint64_t)((uint32_t)(sh4r.r[Rm]));
   947 :}
   948 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
   949 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
   950 STS.L PR, @-Rn {:
   951     CHECKWALIGN32( sh4r.r[Rn] );
   952     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
   953     sh4r.r[Rn] -= 4;
   954 :}
   955 STC.L VBR, @-Rn {:
   956     CHECKPRIV();
   957     CHECKWALIGN32( sh4r.r[Rn] );
   958     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
   959     sh4r.r[Rn] -= 4;
   960 :}
   961 LDS.L @Rm+, PR {:
   962     CHECKRALIGN32( sh4r.r[Rm] );
   963     MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
   964     sh4r.r[Rm] += 4;
   965 :}
   966 LDC.L @Rm+, VBR {:
   967     CHECKPRIV();
   968     CHECKRALIGN32( sh4r.r[Rm] );
   969     MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
   970     sh4r.r[Rm] +=4;
   971 :}
   972 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
   973 LDC Rm, VBR {:
   974     CHECKPRIV();
   975     sh4r.vbr = sh4r.r[Rm];
   976 :}
   977 STC SGR, Rn {:
   978     CHECKPRIV();
   979     sh4r.r[Rn] = sh4r.sgr;
   980 :}
   981 STC.L SGR, @-Rn {:
   982     CHECKPRIV();
   983     CHECKWALIGN32( sh4r.r[Rn] );
   984     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
   985     sh4r.r[Rn] -= 4;
   986 :}
   987 STC.L SSR, @-Rn {:
   988     CHECKPRIV();
   989     CHECKWALIGN32( sh4r.r[Rn] );
   990     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
   991     sh4r.r[Rn] -= 4;
   992 :}
   993 LDC.L @Rm+, SSR {:
   994     CHECKPRIV();
   995     CHECKRALIGN32( sh4r.r[Rm] );
   996     MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
   997     sh4r.r[Rm] +=4;
   998 :}
   999 LDC Rm, SSR {:
  1000     CHECKPRIV();
  1001     sh4r.ssr = sh4r.r[Rm];
  1002 :}
  1003 STC.L SPC, @-Rn {:
  1004     CHECKPRIV();
  1005     CHECKWALIGN32( sh4r.r[Rn] );
  1006     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
  1007     sh4r.r[Rn] -= 4;
  1008 :}
  1009 LDC.L @Rm+, SPC {:
  1010     CHECKPRIV();
  1011     CHECKRALIGN32( sh4r.r[Rm] );
  1012     MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
  1013     sh4r.r[Rm] +=4;
  1014 :}
  1015 LDC Rm, SPC {:
  1016     CHECKPRIV();
  1017     sh4r.spc = sh4r.r[Rm];
  1018 :}
  1019 STS FPUL, Rn {: 
  1020     CHECKFPUEN();
  1021     sh4r.r[Rn] = FPULi; 
  1022 :}
  1023 STS.L FPUL, @-Rn {:
  1024     CHECKFPUEN();
  1025     CHECKWALIGN32( sh4r.r[Rn] );
  1026     MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
  1027     sh4r.r[Rn] -= 4;
  1028 :}
  1029 LDS.L @Rm+, FPUL {:
  1030     CHECKFPUEN();
  1031     CHECKRALIGN32( sh4r.r[Rm] );
  1032     MEM_READ_LONG(sh4r.r[Rm], FPULi);
  1033     sh4r.r[Rm] +=4;
  1034 :}
  1035 LDS Rm, FPUL {:
  1036     CHECKFPUEN();
  1037     FPULi = sh4r.r[Rm]; 
  1038 :}
  1039 STS FPSCR, Rn {: 
  1040     CHECKFPUEN();
  1041     sh4r.r[Rn] = sh4r.fpscr; 
  1042 :}
  1043 STS.L FPSCR, @-Rn {:
  1044     CHECKFPUEN();
  1045     CHECKWALIGN32( sh4r.r[Rn] );
  1046     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
  1047     sh4r.r[Rn] -= 4;
  1048 :}
  1049 LDS.L @Rm+, FPSCR {:
  1050     CHECKFPUEN();
  1051     CHECKRALIGN32( sh4r.r[Rm] );
  1052     MEM_READ_LONG(sh4r.r[Rm], tmp);
  1053     sh4r.r[Rm] +=4;
  1054     sh4_write_fpscr( tmp );
  1055 :}
  1056 LDS Rm, FPSCR {: 
  1057     CHECKFPUEN();
  1058     sh4_write_fpscr( sh4r.r[Rm] );
  1059 :}
  1060 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
  1061 STC.L DBR, @-Rn {:
  1062     CHECKPRIV();
  1063     CHECKWALIGN32( sh4r.r[Rn] );
  1064     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
  1065     sh4r.r[Rn] -= 4;
  1066 :}
  1067 LDC.L @Rm+, DBR {:
  1068     CHECKPRIV();
  1069     CHECKRALIGN32( sh4r.r[Rm] );
  1070     MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
  1071     sh4r.r[Rm] +=4;
  1072 :}
  1073 LDC Rm, DBR {:
  1074     CHECKPRIV();
  1075     sh4r.dbr = sh4r.r[Rm];
  1076 :}
  1077 STC.L Rm_BANK, @-Rn {:
  1078     CHECKPRIV();
  1079     CHECKWALIGN32( sh4r.r[Rn] );
  1080     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
  1081     sh4r.r[Rn] -= 4;
  1082 :}
  1083 LDC.L @Rm+, Rn_BANK {:
  1084     CHECKPRIV();
  1085     CHECKRALIGN32( sh4r.r[Rm] );
  1086     MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
  1087     sh4r.r[Rm] += 4;
  1088 :}
  1089 LDC Rm, Rn_BANK {:
  1090     CHECKPRIV();
  1091     sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1092 :}
  1093 STC SR, Rn {: 
  1094     CHECKPRIV();
  1095     sh4r.r[Rn] = sh4_read_sr();
  1096 :}
  1097 STC GBR, Rn {:
  1098     sh4r.r[Rn] = sh4r.gbr;
  1099 :}
  1100 STC VBR, Rn {:
  1101     CHECKPRIV();
  1102     sh4r.r[Rn] = sh4r.vbr;
  1103 :}
  1104 STC SSR, Rn {:
  1105     CHECKPRIV();
  1106     sh4r.r[Rn] = sh4r.ssr;
  1107 :}
  1108 STC SPC, Rn {:
  1109     CHECKPRIV();
  1110     sh4r.r[Rn] = sh4r.spc;
  1111 :}
  1112 STC Rm_BANK, Rn {:
  1113     CHECKPRIV();
  1114     sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
  1115 :}
  1117 FADD FRm, FRn {:
  1118     CHECKFPUEN();
  1119     if( IS_FPU_DOUBLEPREC() ) {
  1120 	DR(FRn) += DR(FRm);
  1121     } else {
  1122 	FR(FRn) += FR(FRm);
  1124 :}
  1125 FSUB FRm, FRn {:
  1126     CHECKFPUEN();
  1127     if( IS_FPU_DOUBLEPREC() ) {
  1128 	DR(FRn) -= DR(FRm);
  1129     } else {
  1130 	FR(FRn) -= FR(FRm);
  1132 :}
  1134 FMUL FRm, FRn {:
  1135     CHECKFPUEN();
  1136     if( IS_FPU_DOUBLEPREC() ) {
  1137 	DR(FRn) *= DR(FRm);
  1138     } else {
  1139 	FR(FRn) *= FR(FRm);
  1141 :}
  1143 FDIV FRm, FRn {:
  1144     CHECKFPUEN();
  1145     if( IS_FPU_DOUBLEPREC() ) {
  1146 	DR(FRn) /= DR(FRm);
  1147     } else {
  1148 	FR(FRn) /= FR(FRm);
  1150 :}
  1152 FCMP/EQ FRm, FRn {:
  1153     CHECKFPUEN();
  1154     if( IS_FPU_DOUBLEPREC() ) {
  1155 	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1156     } else {
  1157 	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1159 :}
  1161 FCMP/GT FRm, FRn {:
  1162     CHECKFPUEN();
  1163     if( IS_FPU_DOUBLEPREC() ) {
  1164 	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1165     } else {
  1166 	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1168 :}
  1170 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
  1171 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
  1172 FLOAT FPUL, FRn {: 
  1173     CHECKFPUEN();
  1174     if( IS_FPU_DOUBLEPREC() ) {
  1175 	if( FRn&1 ) { // No, really...
  1176 	    dtmp = (double)FPULi;
  1177 	    FR(FRn) = *(((float *)&dtmp)+1);
  1178 	} else {
  1179 	    DRF(FRn>>1) = (double)FPULi;
  1181     } else {
  1182 	FR(FRn) = (float)FPULi;
  1184 :}
  1185 FTRC FRm, FPUL {:
  1186     CHECKFPUEN();
  1187     if( IS_FPU_DOUBLEPREC() ) {
  1188 	if( FRm&1 ) {
  1189 	    dtmp = 0;
  1190 	    *(((float *)&dtmp)+1) = FR(FRm);
  1191 	} else {
  1192 	    dtmp = DRF(FRm>>1);
  1194         if( dtmp >= MAX_INTF )
  1195             FPULi = MAX_INT;
  1196         else if( dtmp <= MIN_INTF )
  1197             FPULi = MIN_INT;
  1198         else 
  1199             FPULi = (int32_t)dtmp;
  1200     } else {
  1201 	ftmp = FR(FRm);
  1202 	if( ftmp >= MAX_INTF )
  1203 	    FPULi = MAX_INT;
  1204 	else if( ftmp <= MIN_INTF )
  1205 	    FPULi = MIN_INT;
  1206 	else
  1207 	    FPULi = (int32_t)ftmp;
  1209 :}
  1210 FNEG FRn {:
  1211     CHECKFPUEN();
  1212     if( IS_FPU_DOUBLEPREC() ) {
  1213 	DR(FRn) = -DR(FRn);
  1214     } else {
  1215         FR(FRn) = -FR(FRn);
  1217 :}
  1218 FABS FRn {:
  1219     CHECKFPUEN();
  1220     if( IS_FPU_DOUBLEPREC() ) {
  1221 	DR(FRn) = fabs(DR(FRn));
  1222     } else {
  1223         FR(FRn) = fabsf(FR(FRn));
  1225 :}
  1226 FSQRT FRn {:
  1227     CHECKFPUEN();
  1228     if( IS_FPU_DOUBLEPREC() ) {
  1229 	DR(FRn) = sqrt(DR(FRn));
  1230     } else {
  1231         FR(FRn) = sqrtf(FR(FRn));
  1233 :}
  1234 FLDI0 FRn {:
  1235     CHECKFPUEN();
  1236     if( IS_FPU_DOUBLEPREC() ) {
  1237 	DR(FRn) = 0.0;
  1238     } else {
  1239         FR(FRn) = 0.0;
  1241 :}
  1242 FLDI1 FRn {:
  1243     CHECKFPUEN();
  1244     if( IS_FPU_DOUBLEPREC() ) {
  1245 	DR(FRn) = 1.0;
  1246     } else {
  1247         FR(FRn) = 1.0;
  1249 :}
  1250 FMAC FR0, FRm, FRn {:
  1251     CHECKFPUEN();
  1252     if( IS_FPU_DOUBLEPREC() ) {
  1253         DR(FRn) += DR(FRm)*DR(0);
  1254     } else {
  1255 	FR(FRn) += FR(FRm)*FR(0);
  1257 :}
  1258 FRCHG {: 
  1259     CHECKFPUEN(); 
  1260     sh4r.fpscr ^= FPSCR_FR; 
  1261     sh4_switch_fr_banks();
  1262 :}
  1263 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
  1264 FCNVSD FPUL, FRn {:
  1265     CHECKFPUEN();
  1266     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1267 	DR(FRn) = (double)FPULf;
  1269 :}
  1270 FCNVDS FRm, FPUL {:
  1271     CHECKFPUEN();
  1272     if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  1273 	FPULf = (float)DR(FRm);
  1275 :}
  1277 FSRRA FRn {:
  1278     CHECKFPUEN();
  1279     if( !IS_FPU_DOUBLEPREC() ) {
  1280 	FR(FRn) = 1.0/sqrtf(FR(FRn));
  1282 :}
  1283 FIPR FVm, FVn {:
  1284     CHECKFPUEN();
  1285     if( !IS_FPU_DOUBLEPREC() ) {
  1286         int tmp2 = FVn<<2;
  1287         tmp = FVm<<2;
  1288         FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  1289             FR(tmp+1)*FR(tmp2+1) +
  1290             FR(tmp+2)*FR(tmp2+2) +
  1291             FR(tmp+3)*FR(tmp2+3);
  1293 :}
  1294 FSCA FPUL, FRn {:
  1295     CHECKFPUEN();
  1296     if( !IS_FPU_DOUBLEPREC() ) {
  1297 	sh4_fsca( FPULi, (float *)&(DRF(FRn>>1)) );
  1298 	/*
  1299         float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  1300         FR(FRn) = sinf(angle);
  1301         FR((FRn)+1) = cosf(angle);
  1302 	*/
  1304 :}
  1305 FTRV XMTRX, FVn {:
  1306     CHECKFPUEN();
  1307     if( !IS_FPU_DOUBLEPREC() ) {
  1308 	sh4_ftrv((float *)&(DRF(FVn<<1)) );
  1310 :}
  1311 UNDEF {:
  1312     UNDEF(ir);
  1313 :}
  1314 %%
  1315     sh4r.pc = sh4r.new_pc;
  1316     sh4r.new_pc += 2;
  1318 except:
  1319     sh4r.in_delay_slot = 0;
  1320     return TRUE;
.