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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 397:640324505325
prev395:c473acbde186
next401:f79327f39818
author nkeynes
date Wed Sep 19 11:30:30 2007 +0000 (14 years ago)
permissions -rw-r--r--
last change Fix SHLL/SHLR/SHAL/SHAR flag setting
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     1 /**
     2  * $Id: sh4x86.c,v 1.13 2007-09-19 11:30:30 nkeynes Exp $
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "sh4/sh4core.h"
    29 #include "sh4/sh4trans.h"
    30 #include "sh4/sh4mmio.h"
    31 #include "sh4/x86op.h"
    32 #include "clock.h"
    34 #define DEFAULT_BACKPATCH_SIZE 4096
    36 /** 
    37  * Struct to manage internal translation state. This state is not saved -
    38  * it is only valid between calls to sh4_translate_begin_block() and
    39  * sh4_translate_end_block()
    40  */
    41 struct sh4_x86_state {
    42     gboolean in_delay_slot;
    43     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    44     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    45     int exit_code;
    47     /* Allocated memory for the (block-wide) back-patch list */
    48     uint32_t **backpatch_list;
    49     uint32_t backpatch_posn;
    50     uint32_t backpatch_size;
    51 };
    53 #define EXIT_DATA_ADDR_READ 0
    54 #define EXIT_DATA_ADDR_WRITE 7
    55 #define EXIT_ILLEGAL 14
    56 #define EXIT_SLOT_ILLEGAL 21
    57 #define EXIT_FPU_DISABLED 28
    58 #define EXIT_SLOT_FPU_DISABLED 35
    60 static struct sh4_x86_state sh4_x86;
    62 static uint32_t max_int = 0x7FFFFFFF;
    63 static uint32_t min_int = 0x80000000;
    64 static uint32_t save_fcw; /* save value for fpu control word */
    65 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
    66 void signsat48( void )
    67 {
    68     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
    69 	sh4r.mac = 0xFFFF800000000000LL;
    70     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
    71 	sh4r.mac = 0x00007FFFFFFFFFFFLL;
    72 }
    74 void sh4_fsca( uint32_t anglei, float *fr )
    75 {
    76     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
    77     *fr++ = cosf(angle);
    78     *fr = sinf(angle);
    79 }
    81 void sh4_sleep()
    82 {
    83     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
    84 	sh4r.sh4_state = SH4_STATE_STANDBY;
    85     } else {
    86 	sh4r.sh4_state = SH4_STATE_SLEEP;
    87     }
    88 }
    90 /**
    91  * Compute the matrix tranform of fv given the matrix xf.
    92  * Both fv and xf are word-swapped as per the sh4r.fr banks
    93  */
    94 void sh4_ftrv( float *target, float *xf )
    95 {
    96     float fv[4] = { target[1], target[0], target[3], target[2] };
    97     target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
    98 	xf[9]*fv[2] + xf[13]*fv[3];
    99     target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
   100 	xf[8]*fv[2] + xf[12]*fv[3];
   101     target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
   102 	xf[11]*fv[2] + xf[15]*fv[3];
   103     target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
   104 	xf[10]*fv[2] + xf[14]*fv[3];
   105 }
   109 void sh4_x86_init()
   110 {
   111     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
   112     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
   113 }
   116 static void sh4_x86_add_backpatch( uint8_t *ptr )
   117 {
   118     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
   119 	sh4_x86.backpatch_size <<= 1;
   120 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
   121 	assert( sh4_x86.backpatch_list != NULL );
   122     }
   123     sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
   124 }
   126 static void sh4_x86_do_backpatch( uint8_t *reloc_base )
   127 {
   128     unsigned int i;
   129     for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
   130 	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
   131     }
   132 }
   134 /**
   135  * Emit an instruction to load an SH4 reg into a real register
   136  */
   137 static inline void load_reg( int x86reg, int sh4reg ) 
   138 {
   139     /* mov [bp+n], reg */
   140     OP(0x8B);
   141     OP(0x45 + (x86reg<<3));
   142     OP(REG_OFFSET(r[sh4reg]));
   143 }
   145 static inline void load_reg16s( int x86reg, int sh4reg )
   146 {
   147     OP(0x0F);
   148     OP(0xBF);
   149     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   150 }
   152 static inline void load_reg16u( int x86reg, int sh4reg )
   153 {
   154     OP(0x0F);
   155     OP(0xB7);
   156     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   158 }
   160 #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
   161 #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
   162 /**
   163  * Emit an instruction to load an immediate value into a register
   164  */
   165 static inline void load_imm32( int x86reg, uint32_t value ) {
   166     /* mov #value, reg */
   167     OP(0xB8 + x86reg);
   168     OP32(value);
   169 }
   171 /**
   172  * Emit an instruction to store an SH4 reg (RN)
   173  */
   174 void static inline store_reg( int x86reg, int sh4reg ) {
   175     /* mov reg, [bp+n] */
   176     OP(0x89);
   177     OP(0x45 + (x86reg<<3));
   178     OP(REG_OFFSET(r[sh4reg]));
   179 }
   181 #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
   183 /**
   184  * Load an FR register (single-precision floating point) into an integer x86
   185  * register (eg for register-to-register moves)
   186  */
   187 void static inline load_fr( int bankreg, int x86reg, int frm )
   188 {
   189     OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
   190 }
   192 /**
   193  * Store an FR register (single-precision floating point) into an integer x86
   194  * register (eg for register-to-register moves)
   195  */
   196 void static inline store_fr( int bankreg, int x86reg, int frn )
   197 {
   198     OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
   199 }
   202 /**
   203  * Load a pointer to the back fp back into the specified x86 register. The
   204  * bankreg must have been previously loaded with FPSCR.
   205  * NB: 12 bytes
   206  */
   207 static inline void load_xf_bank( int bankreg )
   208 {
   209     NOT_r32( bankreg );
   210     SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
   211     AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
   212     OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
   213 }
   215 /**
   216  * Update the fr_bank pointer based on the current fpscr value.
   217  */
   218 static inline void update_fr_bank( int fpscrreg )
   219 {
   220     SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
   221     AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
   222     OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
   223     store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
   224 }
   225 /**
   226  * Push FPUL (as a 32-bit float) onto the FPU stack
   227  */
   228 static inline void push_fpul( )
   229 {
   230     OP(0xD9); OP(0x45); OP(R_FPUL);
   231 }
   233 /**
   234  * Pop FPUL (as a 32-bit float) from the FPU stack
   235  */
   236 static inline void pop_fpul( )
   237 {
   238     OP(0xD9); OP(0x5D); OP(R_FPUL);
   239 }
   241 /**
   242  * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
   243  * with the location of the current fp bank.
   244  */
   245 static inline void push_fr( int bankreg, int frm ) 
   246 {
   247     OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
   248 }
   250 /**
   251  * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
   252  * with bankreg previously loaded with the location of the current fp bank.
   253  */
   254 static inline void pop_fr( int bankreg, int frm )
   255 {
   256     OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
   257 }
   259 /**
   260  * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
   261  * with the location of the current fp bank.
   262  */
   263 static inline void push_dr( int bankreg, int frm )
   264 {
   265     OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
   266 }
   268 static inline void pop_dr( int bankreg, int frm )
   269 {
   270     OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
   271 }
   273 /**
   274  * Note: clobbers EAX to make the indirect call - this isn't usually
   275  * a problem since the callee will usually clobber it anyway.
   276  */
   277 static inline void call_func0( void *ptr )
   278 {
   279     load_imm32(R_EAX, (uint32_t)ptr);
   280     CALL_r32(R_EAX);
   281 }
   283 static inline void call_func1( void *ptr, int arg1 )
   284 {
   285     PUSH_r32(arg1);
   286     call_func0(ptr);
   287     ADD_imm8s_r32( 4, R_ESP );
   288 }
   290 static inline void call_func2( void *ptr, int arg1, int arg2 )
   291 {
   292     PUSH_r32(arg2);
   293     PUSH_r32(arg1);
   294     call_func0(ptr);
   295     ADD_imm8s_r32( 8, R_ESP );
   296 }
   298 /**
   299  * Write a double (64-bit) value into memory, with the first word in arg2a, and
   300  * the second in arg2b
   301  * NB: 30 bytes
   302  */
   303 static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
   304 {
   305     ADD_imm8s_r32( 4, addr );
   306     PUSH_r32(arg2b);
   307     PUSH_r32(addr);
   308     ADD_imm8s_r32( -4, addr );
   309     PUSH_r32(arg2a);
   310     PUSH_r32(addr);
   311     call_func0(sh4_write_long);
   312     ADD_imm8s_r32( 8, R_ESP );
   313     call_func0(sh4_write_long);
   314     ADD_imm8s_r32( 8, R_ESP );
   315 }
   317 /**
   318  * Read a double (64-bit) value from memory, writing the first word into arg2a
   319  * and the second into arg2b. The addr must not be in EAX
   320  * NB: 27 bytes
   321  */
   322 static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
   323 {
   324     PUSH_r32(addr);
   325     call_func0(sh4_read_long);
   326     POP_r32(addr);
   327     PUSH_r32(R_EAX);
   328     ADD_imm8s_r32( 4, addr );
   329     PUSH_r32(addr);
   330     call_func0(sh4_read_long);
   331     ADD_imm8s_r32( 4, R_ESP );
   332     MOV_r32_r32( R_EAX, arg2b );
   333     POP_r32(arg2a);
   334 }
   336 /* Exception checks - Note that all exception checks will clobber EAX */
   337 static void check_priv( )
   338 {
   339     if( !sh4_x86.priv_checked ) {
   340 	sh4_x86.priv_checked = TRUE;
   341 	load_spreg( R_EAX, R_SR );
   342 	AND_imm32_r32( SR_MD, R_EAX );
   343 	if( sh4_x86.in_delay_slot ) {
   344 	    JE_exit( EXIT_SLOT_ILLEGAL );
   345 	} else {
   346 	    JE_exit( EXIT_ILLEGAL );
   347 	}
   348     }
   349 }
   351 static void check_fpuen( )
   352 {
   353     if( !sh4_x86.fpuen_checked ) {
   354 	sh4_x86.fpuen_checked = TRUE;
   355 	load_spreg( R_EAX, R_SR );
   356 	AND_imm32_r32( SR_FD, R_EAX );
   357 	if( sh4_x86.in_delay_slot ) {
   358 	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
   359 	} else {
   360 	    JNE_exit(EXIT_FPU_DISABLED);
   361 	}
   362     }
   363 }
   365 static void check_ralign16( int x86reg )
   366 {
   367     TEST_imm32_r32( 0x00000001, x86reg );
   368     JNE_exit(EXIT_DATA_ADDR_READ);
   369 }
   371 static void check_walign16( int x86reg )
   372 {
   373     TEST_imm32_r32( 0x00000001, x86reg );
   374     JNE_exit(EXIT_DATA_ADDR_WRITE);
   375 }
   377 static void check_ralign32( int x86reg )
   378 {
   379     TEST_imm32_r32( 0x00000003, x86reg );
   380     JNE_exit(EXIT_DATA_ADDR_READ);
   381 }
   382 static void check_walign32( int x86reg )
   383 {
   384     TEST_imm32_r32( 0x00000003, x86reg );
   385     JNE_exit(EXIT_DATA_ADDR_WRITE);
   386 }
   388 #define UNDEF()
   389 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   390 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
   391 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
   392 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
   393 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
   394 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
   395 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
   397 #define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
   401 /**
   402  * Emit the 'start of block' assembly. Sets up the stack frame and save
   403  * SI/DI as required
   404  */
   405 void sh4_translate_begin_block() 
   406 {
   407     PUSH_r32(R_EBP);
   408     /* mov &sh4r, ebp */
   409     load_imm32( R_EBP, (uint32_t)&sh4r );
   410     PUSH_r32(R_EDI);
   411     PUSH_r32(R_ESI);
   412     XOR_r32_r32(R_ESI, R_ESI);
   414     sh4_x86.in_delay_slot = FALSE;
   415     sh4_x86.priv_checked = FALSE;
   416     sh4_x86.fpuen_checked = FALSE;
   417     sh4_x86.backpatch_posn = 0;
   418     sh4_x86.exit_code = 1;
   419 }
   421 /**
   422  * Exit the block early (ie branch out), conditionally or otherwise
   423  */
   424 void exit_block( )
   425 {
   426     store_spreg( R_EDI, REG_OFFSET(pc) );
   427     MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
   428     load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   429     MUL_r32( R_ESI );
   430     ADD_r32_r32( R_EAX, R_ECX );
   431     store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   432     load_imm32( R_EAX, sh4_x86.exit_code );
   433     POP_r32(R_ESI);
   434     POP_r32(R_EDI);
   435     POP_r32(R_EBP);
   436     RET();
   437 }
   439 /**
   440  * Flush any open regs back to memory, restore SI/DI/, update PC, etc
   441  */
   442 void sh4_translate_end_block( sh4addr_t pc ) {
   443     assert( !sh4_x86.in_delay_slot ); // should never stop here
   444     // Normal termination - save PC, cycle count
   445     exit_block( );
   447     if( sh4_x86.backpatch_posn != 0 ) {
   448 	uint8_t *end_ptr = xlat_output;
   449 	// Exception termination. Jump block for various exception codes:
   450 	PUSH_imm32( EXC_DATA_ADDR_READ );
   451 	JMP_rel8( 33, target1 );
   452 	PUSH_imm32( EXC_DATA_ADDR_WRITE );
   453 	JMP_rel8( 26, target2 );
   454 	PUSH_imm32( EXC_ILLEGAL );
   455 	JMP_rel8( 19, target3 );
   456 	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
   457 	JMP_rel8( 12, target4 );
   458 	PUSH_imm32( EXC_FPU_DISABLED ); 
   459 	JMP_rel8( 5, target5 );
   460 	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
   461 	// target
   462 	JMP_TARGET(target1);
   463 	JMP_TARGET(target2);
   464 	JMP_TARGET(target3);
   465 	JMP_TARGET(target4);
   466 	JMP_TARGET(target5);
   467 	load_spreg( R_ECX, REG_OFFSET(pc) );
   468 	ADD_r32_r32( R_ESI, R_ECX );
   469 	ADD_r32_r32( R_ESI, R_ECX );
   470 	store_spreg( R_ECX, REG_OFFSET(pc) );
   471 	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
   472 	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   473 	MUL_r32( R_ESI );
   474 	ADD_r32_r32( R_EAX, R_ECX );
   475 	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
   477 	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
   478 	CALL_r32( R_EAX ); // 2
   479 	ADD_imm8s_r32( 4, R_ESP );
   480 	POP_r32(R_ESI);
   481 	POP_r32(R_EDI);
   482 	POP_r32(R_EBP);
   483 	RET();
   485 	sh4_x86_do_backpatch( end_ptr );
   486     }
   488 }
   491 extern uint16_t *sh4_icache;
   492 extern uint32_t sh4_icache_addr;
   494 /**
   495  * Translate a single instruction. Delayed branches are handled specially
   496  * by translating both branch and delayed instruction as a single unit (as
   497  * 
   498  *
   499  * @return true if the instruction marks the end of a basic block
   500  * (eg a branch or 
   501  */
   502 uint32_t sh4_x86_translate_instruction( uint32_t pc )
   503 {
   504     uint32_t ir;
   505     /* Read instruction */
   506     uint32_t pageaddr = pc >> 12;
   507     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   508 	ir = sh4_icache[(pc&0xFFF)>>1];
   509     } else {
   510 	sh4_icache = (uint16_t *)mem_get_page(pc);
   511 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   512 	    /* If someone's actually been so daft as to try to execute out of an IO
   513 	     * region, fallback on the full-blown memory read
   514 	     */
   515 	    sh4_icache = NULL;
   516 	    ir = sh4_read_word(pc);
   517 	} else {
   518 	    sh4_icache_addr = pageaddr;
   519 	    ir = sh4_icache[(pc&0xFFF)>>1];
   520 	}
   521     }
   523         switch( (ir&0xF000) >> 12 ) {
   524             case 0x0:
   525                 switch( ir&0xF ) {
   526                     case 0x2:
   527                         switch( (ir&0x80) >> 7 ) {
   528                             case 0x0:
   529                                 switch( (ir&0x70) >> 4 ) {
   530                                     case 0x0:
   531                                         { /* STC SR, Rn */
   532                                         uint32_t Rn = ((ir>>8)&0xF); 
   533                                         check_priv();
   534                                         call_func0(sh4_read_sr);
   535                                         store_reg( R_EAX, Rn );
   536                                         }
   537                                         break;
   538                                     case 0x1:
   539                                         { /* STC GBR, Rn */
   540                                         uint32_t Rn = ((ir>>8)&0xF); 
   541                                         load_spreg( R_EAX, R_GBR );
   542                                         store_reg( R_EAX, Rn );
   543                                         }
   544                                         break;
   545                                     case 0x2:
   546                                         { /* STC VBR, Rn */
   547                                         uint32_t Rn = ((ir>>8)&0xF); 
   548                                         check_priv();
   549                                         load_spreg( R_EAX, R_VBR );
   550                                         store_reg( R_EAX, Rn );
   551                                         }
   552                                         break;
   553                                     case 0x3:
   554                                         { /* STC SSR, Rn */
   555                                         uint32_t Rn = ((ir>>8)&0xF); 
   556                                         check_priv();
   557                                         load_spreg( R_EAX, R_SSR );
   558                                         store_reg( R_EAX, Rn );
   559                                         }
   560                                         break;
   561                                     case 0x4:
   562                                         { /* STC SPC, Rn */
   563                                         uint32_t Rn = ((ir>>8)&0xF); 
   564                                         check_priv();
   565                                         load_spreg( R_EAX, R_SPC );
   566                                         store_reg( R_EAX, Rn );
   567                                         }
   568                                         break;
   569                                     default:
   570                                         UNDEF();
   571                                         break;
   572                                 }
   573                                 break;
   574                             case 0x1:
   575                                 { /* STC Rm_BANK, Rn */
   576                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   577                                 check_priv();
   578                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
   579                                 store_reg( R_EAX, Rn );
   580                                 }
   581                                 break;
   582                         }
   583                         break;
   584                     case 0x3:
   585                         switch( (ir&0xF0) >> 4 ) {
   586                             case 0x0:
   587                                 { /* BSRF Rn */
   588                                 uint32_t Rn = ((ir>>8)&0xF); 
   589                                 if( sh4_x86.in_delay_slot ) {
   590                             	SLOTILLEGAL();
   591                                 } else {
   592                             	load_imm32( R_EAX, pc + 4 );
   593                             	store_spreg( R_EAX, R_PR );
   594                             	load_reg( R_EDI, Rn );
   595                             	ADD_r32_r32( R_EAX, R_EDI );
   596                             	sh4_x86.in_delay_slot = TRUE;
   597                             	return 0;
   598                                 }
   599                                 }
   600                                 break;
   601                             case 0x2:
   602                                 { /* BRAF Rn */
   603                                 uint32_t Rn = ((ir>>8)&0xF); 
   604                                 if( sh4_x86.in_delay_slot ) {
   605                             	SLOTILLEGAL();
   606                                 } else {
   607                             	load_reg( R_EDI, Rn );
   608                             	ADD_imm32_r32( pc + 4, R_EDI );
   609                             	sh4_x86.in_delay_slot = TRUE;
   610                             	return 0;
   611                                 }
   612                                 }
   613                                 break;
   614                             case 0x8:
   615                                 { /* PREF @Rn */
   616                                 uint32_t Rn = ((ir>>8)&0xF); 
   617                                 load_reg( R_EAX, Rn );
   618                                 PUSH_r32( R_EAX );
   619                                 AND_imm32_r32( 0xFC000000, R_EAX );
   620                                 CMP_imm32_r32( 0xE0000000, R_EAX );
   621                                 JNE_rel8(7, end);
   622                                 call_func0( sh4_flush_store_queue );
   623                                 JMP_TARGET(end);
   624                                 ADD_imm8s_r32( 4, R_ESP );
   625                                 }
   626                                 break;
   627                             case 0x9:
   628                                 { /* OCBI @Rn */
   629                                 uint32_t Rn = ((ir>>8)&0xF); 
   630                                 }
   631                                 break;
   632                             case 0xA:
   633                                 { /* OCBP @Rn */
   634                                 uint32_t Rn = ((ir>>8)&0xF); 
   635                                 }
   636                                 break;
   637                             case 0xB:
   638                                 { /* OCBWB @Rn */
   639                                 uint32_t Rn = ((ir>>8)&0xF); 
   640                                 }
   641                                 break;
   642                             case 0xC:
   643                                 { /* MOVCA.L R0, @Rn */
   644                                 uint32_t Rn = ((ir>>8)&0xF); 
   645                                 load_reg( R_EAX, 0 );
   646                                 load_reg( R_ECX, Rn );
   647                                 check_walign32( R_ECX );
   648                                 MEM_WRITE_LONG( R_ECX, R_EAX );
   649                                 }
   650                                 break;
   651                             default:
   652                                 UNDEF();
   653                                 break;
   654                         }
   655                         break;
   656                     case 0x4:
   657                         { /* MOV.B Rm, @(R0, Rn) */
   658                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   659                         load_reg( R_EAX, 0 );
   660                         load_reg( R_ECX, Rn );
   661                         ADD_r32_r32( R_EAX, R_ECX );
   662                         load_reg( R_EAX, Rm );
   663                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   664                         }
   665                         break;
   666                     case 0x5:
   667                         { /* MOV.W Rm, @(R0, Rn) */
   668                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   669                         load_reg( R_EAX, 0 );
   670                         load_reg( R_ECX, Rn );
   671                         ADD_r32_r32( R_EAX, R_ECX );
   672                         check_walign16( R_ECX );
   673                         load_reg( R_EAX, Rm );
   674                         MEM_WRITE_WORD( R_ECX, R_EAX );
   675                         }
   676                         break;
   677                     case 0x6:
   678                         { /* MOV.L Rm, @(R0, Rn) */
   679                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   680                         load_reg( R_EAX, 0 );
   681                         load_reg( R_ECX, Rn );
   682                         ADD_r32_r32( R_EAX, R_ECX );
   683                         check_walign32( R_ECX );
   684                         load_reg( R_EAX, Rm );
   685                         MEM_WRITE_LONG( R_ECX, R_EAX );
   686                         }
   687                         break;
   688                     case 0x7:
   689                         { /* MUL.L Rm, Rn */
   690                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   691                         load_reg( R_EAX, Rm );
   692                         load_reg( R_ECX, Rn );
   693                         MUL_r32( R_ECX );
   694                         store_spreg( R_EAX, R_MACL );
   695                         }
   696                         break;
   697                     case 0x8:
   698                         switch( (ir&0xFF0) >> 4 ) {
   699                             case 0x0:
   700                                 { /* CLRT */
   701                                 CLC();
   702                                 SETC_t();
   703                                 }
   704                                 break;
   705                             case 0x1:
   706                                 { /* SETT */
   707                                 STC();
   708                                 SETC_t();
   709                                 }
   710                                 break;
   711                             case 0x2:
   712                                 { /* CLRMAC */
   713                                 XOR_r32_r32(R_EAX, R_EAX);
   714                                 store_spreg( R_EAX, R_MACL );
   715                                 store_spreg( R_EAX, R_MACH );
   716                                 }
   717                                 break;
   718                             case 0x3:
   719                                 { /* LDTLB */
   720                                 }
   721                                 break;
   722                             case 0x4:
   723                                 { /* CLRS */
   724                                 CLC();
   725                                 SETC_sh4r(R_S);
   726                                 }
   727                                 break;
   728                             case 0x5:
   729                                 { /* SETS */
   730                                 STC();
   731                                 SETC_sh4r(R_S);
   732                                 }
   733                                 break;
   734                             default:
   735                                 UNDEF();
   736                                 break;
   737                         }
   738                         break;
   739                     case 0x9:
   740                         switch( (ir&0xF0) >> 4 ) {
   741                             case 0x0:
   742                                 { /* NOP */
   743                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   744                                 }
   745                                 break;
   746                             case 0x1:
   747                                 { /* DIV0U */
   748                                 XOR_r32_r32( R_EAX, R_EAX );
   749                                 store_spreg( R_EAX, R_Q );
   750                                 store_spreg( R_EAX, R_M );
   751                                 store_spreg( R_EAX, R_T );
   752                                 }
   753                                 break;
   754                             case 0x2:
   755                                 { /* MOVT Rn */
   756                                 uint32_t Rn = ((ir>>8)&0xF); 
   757                                 load_spreg( R_EAX, R_T );
   758                                 store_reg( R_EAX, Rn );
   759                                 }
   760                                 break;
   761                             default:
   762                                 UNDEF();
   763                                 break;
   764                         }
   765                         break;
   766                     case 0xA:
   767                         switch( (ir&0xF0) >> 4 ) {
   768                             case 0x0:
   769                                 { /* STS MACH, Rn */
   770                                 uint32_t Rn = ((ir>>8)&0xF); 
   771                                 load_spreg( R_EAX, R_MACH );
   772                                 store_reg( R_EAX, Rn );
   773                                 }
   774                                 break;
   775                             case 0x1:
   776                                 { /* STS MACL, Rn */
   777                                 uint32_t Rn = ((ir>>8)&0xF); 
   778                                 load_spreg( R_EAX, R_MACL );
   779                                 store_reg( R_EAX, Rn );
   780                                 }
   781                                 break;
   782                             case 0x2:
   783                                 { /* STS PR, Rn */
   784                                 uint32_t Rn = ((ir>>8)&0xF); 
   785                                 load_spreg( R_EAX, R_PR );
   786                                 store_reg( R_EAX, Rn );
   787                                 }
   788                                 break;
   789                             case 0x3:
   790                                 { /* STC SGR, Rn */
   791                                 uint32_t Rn = ((ir>>8)&0xF); 
   792                                 check_priv();
   793                                 load_spreg( R_EAX, R_SGR );
   794                                 store_reg( R_EAX, Rn );
   795                                 }
   796                                 break;
   797                             case 0x5:
   798                                 { /* STS FPUL, Rn */
   799                                 uint32_t Rn = ((ir>>8)&0xF); 
   800                                 load_spreg( R_EAX, R_FPUL );
   801                                 store_reg( R_EAX, Rn );
   802                                 }
   803                                 break;
   804                             case 0x6:
   805                                 { /* STS FPSCR, Rn */
   806                                 uint32_t Rn = ((ir>>8)&0xF); 
   807                                 load_spreg( R_EAX, R_FPSCR );
   808                                 store_reg( R_EAX, Rn );
   809                                 }
   810                                 break;
   811                             case 0xF:
   812                                 { /* STC DBR, Rn */
   813                                 uint32_t Rn = ((ir>>8)&0xF); 
   814                                 check_priv();
   815                                 load_spreg( R_EAX, R_DBR );
   816                                 store_reg( R_EAX, Rn );
   817                                 }
   818                                 break;
   819                             default:
   820                                 UNDEF();
   821                                 break;
   822                         }
   823                         break;
   824                     case 0xB:
   825                         switch( (ir&0xFF0) >> 4 ) {
   826                             case 0x0:
   827                                 { /* RTS */
   828                                 if( sh4_x86.in_delay_slot ) {
   829                             	SLOTILLEGAL();
   830                                 } else {
   831                             	load_spreg( R_EDI, R_PR );
   832                             	sh4_x86.in_delay_slot = TRUE;
   833                             	return 0;
   834                                 }
   835                                 }
   836                                 break;
   837                             case 0x1:
   838                                 { /* SLEEP */
   839                                 check_priv();
   840                                 call_func0( sh4_sleep );
   841                                 sh4_x86.exit_code = 0;
   842                                 sh4_x86.in_delay_slot = FALSE;
   843                                 INC_r32(R_ESI);
   844                                 return 1;
   845                                 }
   846                                 break;
   847                             case 0x2:
   848                                 { /* RTE */
   849                                 check_priv();
   850                                 if( sh4_x86.in_delay_slot ) {
   851                             	SLOTILLEGAL();
   852                                 } else {
   853                             	load_spreg( R_EDI, R_SPC );
   854                             	load_spreg( R_EAX, R_SSR );
   855                             	call_func1( sh4_write_sr, R_EAX );
   856                             	sh4_x86.in_delay_slot = TRUE;
   857                             	sh4_x86.priv_checked = FALSE;
   858                             	sh4_x86.fpuen_checked = FALSE;
   859                             	return 0;
   860                                 }
   861                                 }
   862                                 break;
   863                             default:
   864                                 UNDEF();
   865                                 break;
   866                         }
   867                         break;
   868                     case 0xC:
   869                         { /* MOV.B @(R0, Rm), Rn */
   870                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   871                         load_reg( R_EAX, 0 );
   872                         load_reg( R_ECX, Rm );
   873                         ADD_r32_r32( R_EAX, R_ECX );
   874                         MEM_READ_BYTE( R_ECX, R_EAX );
   875                         store_reg( R_EAX, Rn );
   876                         }
   877                         break;
   878                     case 0xD:
   879                         { /* MOV.W @(R0, Rm), Rn */
   880                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   881                         load_reg( R_EAX, 0 );
   882                         load_reg( R_ECX, Rm );
   883                         ADD_r32_r32( R_EAX, R_ECX );
   884                         check_ralign16( R_ECX );
   885                         MEM_READ_WORD( R_ECX, R_EAX );
   886                         store_reg( R_EAX, Rn );
   887                         }
   888                         break;
   889                     case 0xE:
   890                         { /* MOV.L @(R0, Rm), Rn */
   891                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   892                         load_reg( R_EAX, 0 );
   893                         load_reg( R_ECX, Rm );
   894                         ADD_r32_r32( R_EAX, R_ECX );
   895                         check_ralign32( R_ECX );
   896                         MEM_READ_LONG( R_ECX, R_EAX );
   897                         store_reg( R_EAX, Rn );
   898                         }
   899                         break;
   900                     case 0xF:
   901                         { /* MAC.L @Rm+, @Rn+ */
   902                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   903                         load_reg( R_ECX, Rm );
   904                         check_ralign32( R_ECX );
   905                         load_reg( R_ECX, Rn );
   906                         check_ralign32( R_ECX );
   907                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
   908                         MEM_READ_LONG( R_ECX, R_EAX );
   909                         PUSH_r32( R_EAX );
   910                         load_reg( R_ECX, Rm );
   911                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
   912                         MEM_READ_LONG( R_ECX, R_EAX );
   913                         POP_r32( R_ECX );
   914                         IMUL_r32( R_ECX );
   915                         ADD_r32_sh4r( R_EAX, R_MACL );
   916                         ADC_r32_sh4r( R_EDX, R_MACH );
   918                         load_spreg( R_ECX, R_S );
   919                         TEST_r32_r32(R_ECX, R_ECX);
   920                         JE_rel8( 7, nosat );
   921                         call_func0( signsat48 );
   922                         JMP_TARGET( nosat );
   923                         }
   924                         break;
   925                     default:
   926                         UNDEF();
   927                         break;
   928                 }
   929                 break;
   930             case 0x1:
   931                 { /* MOV.L Rm, @(disp, Rn) */
   932                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   933                 load_reg( R_ECX, Rn );
   934                 load_reg( R_EAX, Rm );
   935                 ADD_imm32_r32( disp, R_ECX );
   936                 check_walign32( R_ECX );
   937                 MEM_WRITE_LONG( R_ECX, R_EAX );
   938                 }
   939                 break;
   940             case 0x2:
   941                 switch( ir&0xF ) {
   942                     case 0x0:
   943                         { /* MOV.B Rm, @Rn */
   944                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   945                         load_reg( R_EAX, Rm );
   946                         load_reg( R_ECX, Rn );
   947                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   948                         }
   949                         break;
   950                     case 0x1:
   951                         { /* MOV.W Rm, @Rn */
   952                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   953                         load_reg( R_ECX, Rn );
   954                         check_walign16( R_ECX );
   955                         load_reg( R_EAX, Rm );
   956                         MEM_WRITE_WORD( R_ECX, R_EAX );
   957                         }
   958                         break;
   959                     case 0x2:
   960                         { /* MOV.L Rm, @Rn */
   961                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   962                         load_reg( R_EAX, Rm );
   963                         load_reg( R_ECX, Rn );
   964                         check_walign32(R_ECX);
   965                         MEM_WRITE_LONG( R_ECX, R_EAX );
   966                         }
   967                         break;
   968                     case 0x4:
   969                         { /* MOV.B Rm, @-Rn */
   970                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   971                         load_reg( R_EAX, Rm );
   972                         load_reg( R_ECX, Rn );
   973                         ADD_imm8s_r32( -1, R_ECX );
   974                         store_reg( R_ECX, Rn );
   975                         MEM_WRITE_BYTE( R_ECX, R_EAX );
   976                         }
   977                         break;
   978                     case 0x5:
   979                         { /* MOV.W Rm, @-Rn */
   980                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   981                         load_reg( R_ECX, Rn );
   982                         check_walign16( R_ECX );
   983                         load_reg( R_EAX, Rm );
   984                         ADD_imm8s_r32( -2, R_ECX );
   985                         store_reg( R_ECX, Rn );
   986                         MEM_WRITE_WORD( R_ECX, R_EAX );
   987                         }
   988                         break;
   989                     case 0x6:
   990                         { /* MOV.L Rm, @-Rn */
   991                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   992                         load_reg( R_EAX, Rm );
   993                         load_reg( R_ECX, Rn );
   994                         check_walign32( R_ECX );
   995                         ADD_imm8s_r32( -4, R_ECX );
   996                         store_reg( R_ECX, Rn );
   997                         MEM_WRITE_LONG( R_ECX, R_EAX );
   998                         }
   999                         break;
  1000                     case 0x7:
  1001                         { /* DIV0S Rm, Rn */
  1002                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1003                         load_reg( R_EAX, Rm );
  1004                         load_reg( R_ECX, Rn );
  1005                         SHR_imm8_r32( 31, R_EAX );
  1006                         SHR_imm8_r32( 31, R_ECX );
  1007                         store_spreg( R_EAX, R_M );
  1008                         store_spreg( R_ECX, R_Q );
  1009                         CMP_r32_r32( R_EAX, R_ECX );
  1010                         SETNE_t();
  1012                         break;
  1013                     case 0x8:
  1014                         { /* TST Rm, Rn */
  1015                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1016                         load_reg( R_EAX, Rm );
  1017                         load_reg( R_ECX, Rn );
  1018                         TEST_r32_r32( R_EAX, R_ECX );
  1019                         SETE_t();
  1021                         break;
  1022                     case 0x9:
  1023                         { /* AND Rm, Rn */
  1024                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1025                         load_reg( R_EAX, Rm );
  1026                         load_reg( R_ECX, Rn );
  1027                         AND_r32_r32( R_EAX, R_ECX );
  1028                         store_reg( R_ECX, Rn );
  1030                         break;
  1031                     case 0xA:
  1032                         { /* XOR Rm, Rn */
  1033                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1034                         load_reg( R_EAX, Rm );
  1035                         load_reg( R_ECX, Rn );
  1036                         XOR_r32_r32( R_EAX, R_ECX );
  1037                         store_reg( R_ECX, Rn );
  1039                         break;
  1040                     case 0xB:
  1041                         { /* OR Rm, Rn */
  1042                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1043                         load_reg( R_EAX, Rm );
  1044                         load_reg( R_ECX, Rn );
  1045                         OR_r32_r32( R_EAX, R_ECX );
  1046                         store_reg( R_ECX, Rn );
  1048                         break;
  1049                     case 0xC:
  1050                         { /* CMP/STR Rm, Rn */
  1051                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1052                         load_reg( R_EAX, Rm );
  1053                         load_reg( R_ECX, Rn );
  1054                         XOR_r32_r32( R_ECX, R_EAX );
  1055                         TEST_r8_r8( R_AL, R_AL );
  1056                         JE_rel8(13, target1);
  1057                         TEST_r8_r8( R_AH, R_AH ); // 2
  1058                         JE_rel8(9, target2);
  1059                         SHR_imm8_r32( 16, R_EAX ); // 3
  1060                         TEST_r8_r8( R_AL, R_AL ); // 2
  1061                         JE_rel8(2, target3);
  1062                         TEST_r8_r8( R_AH, R_AH ); // 2
  1063                         JMP_TARGET(target1);
  1064                         JMP_TARGET(target2);
  1065                         JMP_TARGET(target3);
  1066                         SETE_t();
  1068                         break;
  1069                     case 0xD:
  1070                         { /* XTRCT Rm, Rn */
  1071                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1072                         load_reg( R_EAX, Rm );
  1073                         load_reg( R_ECX, Rn );
  1074                         SHL_imm8_r32( 16, R_EAX );
  1075                         SHR_imm8_r32( 16, R_ECX );
  1076                         OR_r32_r32( R_EAX, R_ECX );
  1077                         store_reg( R_ECX, Rn );
  1079                         break;
  1080                     case 0xE:
  1081                         { /* MULU.W Rm, Rn */
  1082                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1083                         load_reg16u( R_EAX, Rm );
  1084                         load_reg16u( R_ECX, Rn );
  1085                         MUL_r32( R_ECX );
  1086                         store_spreg( R_EAX, R_MACL );
  1088                         break;
  1089                     case 0xF:
  1090                         { /* MULS.W Rm, Rn */
  1091                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1092                         load_reg16s( R_EAX, Rm );
  1093                         load_reg16s( R_ECX, Rn );
  1094                         MUL_r32( R_ECX );
  1095                         store_spreg( R_EAX, R_MACL );
  1097                         break;
  1098                     default:
  1099                         UNDEF();
  1100                         break;
  1102                 break;
  1103             case 0x3:
  1104                 switch( ir&0xF ) {
  1105                     case 0x0:
  1106                         { /* CMP/EQ Rm, Rn */
  1107                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1108                         load_reg( R_EAX, Rm );
  1109                         load_reg( R_ECX, Rn );
  1110                         CMP_r32_r32( R_EAX, R_ECX );
  1111                         SETE_t();
  1113                         break;
  1114                     case 0x2:
  1115                         { /* CMP/HS Rm, Rn */
  1116                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1117                         load_reg( R_EAX, Rm );
  1118                         load_reg( R_ECX, Rn );
  1119                         CMP_r32_r32( R_EAX, R_ECX );
  1120                         SETAE_t();
  1122                         break;
  1123                     case 0x3:
  1124                         { /* CMP/GE Rm, Rn */
  1125                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1126                         load_reg( R_EAX, Rm );
  1127                         load_reg( R_ECX, Rn );
  1128                         CMP_r32_r32( R_EAX, R_ECX );
  1129                         SETGE_t();
  1131                         break;
  1132                     case 0x4:
  1133                         { /* DIV1 Rm, Rn */
  1134                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1135                         load_spreg( R_ECX, R_M );
  1136                         load_reg( R_EAX, Rn );
  1137                         LDC_t();
  1138                         RCL1_r32( R_EAX );
  1139                         SETC_r8( R_DL ); // Q'
  1140                         CMP_sh4r_r32( R_Q, R_ECX );
  1141                         JE_rel8(5, mqequal);
  1142                         ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1143                         JMP_rel8(3, end);
  1144                         JMP_TARGET(mqequal);
  1145                         SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1146                         JMP_TARGET(end);
  1147                         store_reg( R_EAX, Rn ); // Done with Rn now
  1148                         SETC_r8(R_AL); // tmp1
  1149                         XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  1150                         XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  1151                         store_spreg( R_ECX, R_Q );
  1152                         XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  1153                         MOVZX_r8_r32( R_AL, R_EAX );
  1154                         store_spreg( R_EAX, R_T );
  1156                         break;
  1157                     case 0x5:
  1158                         { /* DMULU.L Rm, Rn */
  1159                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1160                         load_reg( R_EAX, Rm );
  1161                         load_reg( R_ECX, Rn );
  1162                         MUL_r32(R_ECX);
  1163                         store_spreg( R_EDX, R_MACH );
  1164                         store_spreg( R_EAX, R_MACL );
  1166                         break;
  1167                     case 0x6:
  1168                         { /* CMP/HI Rm, Rn */
  1169                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1170                         load_reg( R_EAX, Rm );
  1171                         load_reg( R_ECX, Rn );
  1172                         CMP_r32_r32( R_EAX, R_ECX );
  1173                         SETA_t();
  1175                         break;
  1176                     case 0x7:
  1177                         { /* CMP/GT Rm, Rn */
  1178                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1179                         load_reg( R_EAX, Rm );
  1180                         load_reg( R_ECX, Rn );
  1181                         CMP_r32_r32( R_EAX, R_ECX );
  1182                         SETG_t();
  1184                         break;
  1185                     case 0x8:
  1186                         { /* SUB Rm, Rn */
  1187                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1188                         load_reg( R_EAX, Rm );
  1189                         load_reg( R_ECX, Rn );
  1190                         SUB_r32_r32( R_EAX, R_ECX );
  1191                         store_reg( R_ECX, Rn );
  1193                         break;
  1194                     case 0xA:
  1195                         { /* SUBC Rm, Rn */
  1196                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1197                         load_reg( R_EAX, Rm );
  1198                         load_reg( R_ECX, Rn );
  1199                         LDC_t();
  1200                         SBB_r32_r32( R_EAX, R_ECX );
  1201                         store_reg( R_ECX, Rn );
  1202                         SETC_t();
  1204                         break;
  1205                     case 0xB:
  1206                         { /* SUBV Rm, Rn */
  1207                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1208                         load_reg( R_EAX, Rm );
  1209                         load_reg( R_ECX, Rn );
  1210                         SUB_r32_r32( R_EAX, R_ECX );
  1211                         store_reg( R_ECX, Rn );
  1212                         SETO_t();
  1214                         break;
  1215                     case 0xC:
  1216                         { /* ADD Rm, Rn */
  1217                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1218                         load_reg( R_EAX, Rm );
  1219                         load_reg( R_ECX, Rn );
  1220                         ADD_r32_r32( R_EAX, R_ECX );
  1221                         store_reg( R_ECX, Rn );
  1223                         break;
  1224                     case 0xD:
  1225                         { /* DMULS.L Rm, Rn */
  1226                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1227                         load_reg( R_EAX, Rm );
  1228                         load_reg( R_ECX, Rn );
  1229                         IMUL_r32(R_ECX);
  1230                         store_spreg( R_EDX, R_MACH );
  1231                         store_spreg( R_EAX, R_MACL );
  1233                         break;
  1234                     case 0xE:
  1235                         { /* ADDC Rm, Rn */
  1236                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1237                         load_reg( R_EAX, Rm );
  1238                         load_reg( R_ECX, Rn );
  1239                         LDC_t();
  1240                         ADC_r32_r32( R_EAX, R_ECX );
  1241                         store_reg( R_ECX, Rn );
  1242                         SETC_t();
  1244                         break;
  1245                     case 0xF:
  1246                         { /* ADDV Rm, Rn */
  1247                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1248                         load_reg( R_EAX, Rm );
  1249                         load_reg( R_ECX, Rn );
  1250                         ADD_r32_r32( R_EAX, R_ECX );
  1251                         store_reg( R_ECX, Rn );
  1252                         SETO_t();
  1254                         break;
  1255                     default:
  1256                         UNDEF();
  1257                         break;
  1259                 break;
  1260             case 0x4:
  1261                 switch( ir&0xF ) {
  1262                     case 0x0:
  1263                         switch( (ir&0xF0) >> 4 ) {
  1264                             case 0x0:
  1265                                 { /* SHLL Rn */
  1266                                 uint32_t Rn = ((ir>>8)&0xF); 
  1267                                 load_reg( R_EAX, Rn );
  1268                                 SHL1_r32( R_EAX );
  1269                                 SETC_t();
  1270                                 store_reg( R_EAX, Rn );
  1272                                 break;
  1273                             case 0x1:
  1274                                 { /* DT Rn */
  1275                                 uint32_t Rn = ((ir>>8)&0xF); 
  1276                                 load_reg( R_EAX, Rn );
  1277                                 ADD_imm8s_r32( -1, R_EAX );
  1278                                 store_reg( R_EAX, Rn );
  1279                                 SETE_t();
  1281                                 break;
  1282                             case 0x2:
  1283                                 { /* SHAL Rn */
  1284                                 uint32_t Rn = ((ir>>8)&0xF); 
  1285                                 load_reg( R_EAX, Rn );
  1286                                 SHL1_r32( R_EAX );
  1287                                 SETC_t();
  1288                                 store_reg( R_EAX, Rn );
  1290                                 break;
  1291                             default:
  1292                                 UNDEF();
  1293                                 break;
  1295                         break;
  1296                     case 0x1:
  1297                         switch( (ir&0xF0) >> 4 ) {
  1298                             case 0x0:
  1299                                 { /* SHLR Rn */
  1300                                 uint32_t Rn = ((ir>>8)&0xF); 
  1301                                 load_reg( R_EAX, Rn );
  1302                                 SHR1_r32( R_EAX );
  1303                                 SETC_t();
  1304                                 store_reg( R_EAX, Rn );
  1306                                 break;
  1307                             case 0x1:
  1308                                 { /* CMP/PZ Rn */
  1309                                 uint32_t Rn = ((ir>>8)&0xF); 
  1310                                 load_reg( R_EAX, Rn );
  1311                                 CMP_imm8s_r32( 0, R_EAX );
  1312                                 SETGE_t();
  1314                                 break;
  1315                             case 0x2:
  1316                                 { /* SHAR Rn */
  1317                                 uint32_t Rn = ((ir>>8)&0xF); 
  1318                                 load_reg( R_EAX, Rn );
  1319                                 SAR1_r32( R_EAX );
  1320                                 SETC_t();
  1321                                 store_reg( R_EAX, Rn );
  1323                                 break;
  1324                             default:
  1325                                 UNDEF();
  1326                                 break;
  1328                         break;
  1329                     case 0x2:
  1330                         switch( (ir&0xF0) >> 4 ) {
  1331                             case 0x0:
  1332                                 { /* STS.L MACH, @-Rn */
  1333                                 uint32_t Rn = ((ir>>8)&0xF); 
  1334                                 load_reg( R_ECX, Rn );
  1335                                 check_walign32( R_ECX );
  1336                                 ADD_imm8s_r32( -4, R_ECX );
  1337                                 store_reg( R_ECX, Rn );
  1338                                 load_spreg( R_EAX, R_MACH );
  1339                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1341                                 break;
  1342                             case 0x1:
  1343                                 { /* STS.L MACL, @-Rn */
  1344                                 uint32_t Rn = ((ir>>8)&0xF); 
  1345                                 load_reg( R_ECX, Rn );
  1346                                 check_walign32( R_ECX );
  1347                                 ADD_imm8s_r32( -4, R_ECX );
  1348                                 store_reg( R_ECX, Rn );
  1349                                 load_spreg( R_EAX, R_MACL );
  1350                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1352                                 break;
  1353                             case 0x2:
  1354                                 { /* STS.L PR, @-Rn */
  1355                                 uint32_t Rn = ((ir>>8)&0xF); 
  1356                                 load_reg( R_ECX, Rn );
  1357                                 check_walign32( R_ECX );
  1358                                 ADD_imm8s_r32( -4, R_ECX );
  1359                                 store_reg( R_ECX, Rn );
  1360                                 load_spreg( R_EAX, R_PR );
  1361                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1363                                 break;
  1364                             case 0x3:
  1365                                 { /* STC.L SGR, @-Rn */
  1366                                 uint32_t Rn = ((ir>>8)&0xF); 
  1367                                 check_priv();
  1368                                 load_reg( R_ECX, Rn );
  1369                                 check_walign32( R_ECX );
  1370                                 ADD_imm8s_r32( -4, R_ECX );
  1371                                 store_reg( R_ECX, Rn );
  1372                                 load_spreg( R_EAX, R_SGR );
  1373                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1375                                 break;
  1376                             case 0x5:
  1377                                 { /* STS.L FPUL, @-Rn */
  1378                                 uint32_t Rn = ((ir>>8)&0xF); 
  1379                                 load_reg( R_ECX, Rn );
  1380                                 check_walign32( R_ECX );
  1381                                 ADD_imm8s_r32( -4, R_ECX );
  1382                                 store_reg( R_ECX, Rn );
  1383                                 load_spreg( R_EAX, R_FPUL );
  1384                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1386                                 break;
  1387                             case 0x6:
  1388                                 { /* STS.L FPSCR, @-Rn */
  1389                                 uint32_t Rn = ((ir>>8)&0xF); 
  1390                                 load_reg( R_ECX, Rn );
  1391                                 check_walign32( R_ECX );
  1392                                 ADD_imm8s_r32( -4, R_ECX );
  1393                                 store_reg( R_ECX, Rn );
  1394                                 load_spreg( R_EAX, R_FPSCR );
  1395                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1397                                 break;
  1398                             case 0xF:
  1399                                 { /* STC.L DBR, @-Rn */
  1400                                 uint32_t Rn = ((ir>>8)&0xF); 
  1401                                 check_priv();
  1402                                 load_reg( R_ECX, Rn );
  1403                                 check_walign32( R_ECX );
  1404                                 ADD_imm8s_r32( -4, R_ECX );
  1405                                 store_reg( R_ECX, Rn );
  1406                                 load_spreg( R_EAX, R_DBR );
  1407                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1409                                 break;
  1410                             default:
  1411                                 UNDEF();
  1412                                 break;
  1414                         break;
  1415                     case 0x3:
  1416                         switch( (ir&0x80) >> 7 ) {
  1417                             case 0x0:
  1418                                 switch( (ir&0x70) >> 4 ) {
  1419                                     case 0x0:
  1420                                         { /* STC.L SR, @-Rn */
  1421                                         uint32_t Rn = ((ir>>8)&0xF); 
  1422                                         check_priv();
  1423                                         call_func0( sh4_read_sr );
  1424                                         load_reg( R_ECX, Rn );
  1425                                         check_walign32( R_ECX );
  1426                                         ADD_imm8s_r32( -4, R_ECX );
  1427                                         store_reg( R_ECX, Rn );
  1428                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1430                                         break;
  1431                                     case 0x1:
  1432                                         { /* STC.L GBR, @-Rn */
  1433                                         uint32_t Rn = ((ir>>8)&0xF); 
  1434                                         load_reg( R_ECX, Rn );
  1435                                         check_walign32( R_ECX );
  1436                                         ADD_imm8s_r32( -4, R_ECX );
  1437                                         store_reg( R_ECX, Rn );
  1438                                         load_spreg( R_EAX, R_GBR );
  1439                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1441                                         break;
  1442                                     case 0x2:
  1443                                         { /* STC.L VBR, @-Rn */
  1444                                         uint32_t Rn = ((ir>>8)&0xF); 
  1445                                         check_priv();
  1446                                         load_reg( R_ECX, Rn );
  1447                                         check_walign32( R_ECX );
  1448                                         ADD_imm8s_r32( -4, R_ECX );
  1449                                         store_reg( R_ECX, Rn );
  1450                                         load_spreg( R_EAX, R_VBR );
  1451                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1453                                         break;
  1454                                     case 0x3:
  1455                                         { /* STC.L SSR, @-Rn */
  1456                                         uint32_t Rn = ((ir>>8)&0xF); 
  1457                                         check_priv();
  1458                                         load_reg( R_ECX, Rn );
  1459                                         check_walign32( R_ECX );
  1460                                         ADD_imm8s_r32( -4, R_ECX );
  1461                                         store_reg( R_ECX, Rn );
  1462                                         load_spreg( R_EAX, R_SSR );
  1463                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1465                                         break;
  1466                                     case 0x4:
  1467                                         { /* STC.L SPC, @-Rn */
  1468                                         uint32_t Rn = ((ir>>8)&0xF); 
  1469                                         check_priv();
  1470                                         load_reg( R_ECX, Rn );
  1471                                         check_walign32( R_ECX );
  1472                                         ADD_imm8s_r32( -4, R_ECX );
  1473                                         store_reg( R_ECX, Rn );
  1474                                         load_spreg( R_EAX, R_SPC );
  1475                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1477                                         break;
  1478                                     default:
  1479                                         UNDEF();
  1480                                         break;
  1482                                 break;
  1483                             case 0x1:
  1484                                 { /* STC.L Rm_BANK, @-Rn */
  1485                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1486                                 check_priv();
  1487                                 load_reg( R_ECX, Rn );
  1488                                 check_walign32( R_ECX );
  1489                                 ADD_imm8s_r32( -4, R_ECX );
  1490                                 store_reg( R_ECX, Rn );
  1491                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
  1492                                 MEM_WRITE_LONG( R_ECX, R_EAX );
  1494                                 break;
  1496                         break;
  1497                     case 0x4:
  1498                         switch( (ir&0xF0) >> 4 ) {
  1499                             case 0x0:
  1500                                 { /* ROTL Rn */
  1501                                 uint32_t Rn = ((ir>>8)&0xF); 
  1502                                 load_reg( R_EAX, Rn );
  1503                                 ROL1_r32( R_EAX );
  1504                                 store_reg( R_EAX, Rn );
  1505                                 SETC_t();
  1507                                 break;
  1508                             case 0x2:
  1509                                 { /* ROTCL Rn */
  1510                                 uint32_t Rn = ((ir>>8)&0xF); 
  1511                                 load_reg( R_EAX, Rn );
  1512                                 LDC_t();
  1513                                 RCL1_r32( R_EAX );
  1514                                 store_reg( R_EAX, Rn );
  1515                                 SETC_t();
  1517                                 break;
  1518                             default:
  1519                                 UNDEF();
  1520                                 break;
  1522                         break;
  1523                     case 0x5:
  1524                         switch( (ir&0xF0) >> 4 ) {
  1525                             case 0x0:
  1526                                 { /* ROTR Rn */
  1527                                 uint32_t Rn = ((ir>>8)&0xF); 
  1528                                 load_reg( R_EAX, Rn );
  1529                                 ROR1_r32( R_EAX );
  1530                                 store_reg( R_EAX, Rn );
  1531                                 SETC_t();
  1533                                 break;
  1534                             case 0x1:
  1535                                 { /* CMP/PL Rn */
  1536                                 uint32_t Rn = ((ir>>8)&0xF); 
  1537                                 load_reg( R_EAX, Rn );
  1538                                 CMP_imm8s_r32( 0, R_EAX );
  1539                                 SETG_t();
  1541                                 break;
  1542                             case 0x2:
  1543                                 { /* ROTCR Rn */
  1544                                 uint32_t Rn = ((ir>>8)&0xF); 
  1545                                 load_reg( R_EAX, Rn );
  1546                                 LDC_t();
  1547                                 RCR1_r32( R_EAX );
  1548                                 store_reg( R_EAX, Rn );
  1549                                 SETC_t();
  1551                                 break;
  1552                             default:
  1553                                 UNDEF();
  1554                                 break;
  1556                         break;
  1557                     case 0x6:
  1558                         switch( (ir&0xF0) >> 4 ) {
  1559                             case 0x0:
  1560                                 { /* LDS.L @Rm+, MACH */
  1561                                 uint32_t Rm = ((ir>>8)&0xF); 
  1562                                 load_reg( R_EAX, Rm );
  1563                                 check_ralign32( R_EAX );
  1564                                 MOV_r32_r32( R_EAX, R_ECX );
  1565                                 ADD_imm8s_r32( 4, R_EAX );
  1566                                 store_reg( R_EAX, Rm );
  1567                                 MEM_READ_LONG( R_ECX, R_EAX );
  1568                                 store_spreg( R_EAX, R_MACH );
  1570                                 break;
  1571                             case 0x1:
  1572                                 { /* LDS.L @Rm+, MACL */
  1573                                 uint32_t Rm = ((ir>>8)&0xF); 
  1574                                 load_reg( R_EAX, Rm );
  1575                                 check_ralign32( R_EAX );
  1576                                 MOV_r32_r32( R_EAX, R_ECX );
  1577                                 ADD_imm8s_r32( 4, R_EAX );
  1578                                 store_reg( R_EAX, Rm );
  1579                                 MEM_READ_LONG( R_ECX, R_EAX );
  1580                                 store_spreg( R_EAX, R_MACL );
  1582                                 break;
  1583                             case 0x2:
  1584                                 { /* LDS.L @Rm+, PR */
  1585                                 uint32_t Rm = ((ir>>8)&0xF); 
  1586                                 load_reg( R_EAX, Rm );
  1587                                 check_ralign32( R_EAX );
  1588                                 MOV_r32_r32( R_EAX, R_ECX );
  1589                                 ADD_imm8s_r32( 4, R_EAX );
  1590                                 store_reg( R_EAX, Rm );
  1591                                 MEM_READ_LONG( R_ECX, R_EAX );
  1592                                 store_spreg( R_EAX, R_PR );
  1594                                 break;
  1595                             case 0x3:
  1596                                 { /* LDC.L @Rm+, SGR */
  1597                                 uint32_t Rm = ((ir>>8)&0xF); 
  1598                                 check_priv();
  1599                                 load_reg( R_EAX, Rm );
  1600                                 check_ralign32( R_EAX );
  1601                                 MOV_r32_r32( R_EAX, R_ECX );
  1602                                 ADD_imm8s_r32( 4, R_EAX );
  1603                                 store_reg( R_EAX, Rm );
  1604                                 MEM_READ_LONG( R_ECX, R_EAX );
  1605                                 store_spreg( R_EAX, R_SGR );
  1607                                 break;
  1608                             case 0x5:
  1609                                 { /* LDS.L @Rm+, FPUL */
  1610                                 uint32_t Rm = ((ir>>8)&0xF); 
  1611                                 load_reg( R_EAX, Rm );
  1612                                 check_ralign32( R_EAX );
  1613                                 MOV_r32_r32( R_EAX, R_ECX );
  1614                                 ADD_imm8s_r32( 4, R_EAX );
  1615                                 store_reg( R_EAX, Rm );
  1616                                 MEM_READ_LONG( R_ECX, R_EAX );
  1617                                 store_spreg( R_EAX, R_FPUL );
  1619                                 break;
  1620                             case 0x6:
  1621                                 { /* LDS.L @Rm+, FPSCR */
  1622                                 uint32_t Rm = ((ir>>8)&0xF); 
  1623                                 load_reg( R_EAX, Rm );
  1624                                 check_ralign32( R_EAX );
  1625                                 MOV_r32_r32( R_EAX, R_ECX );
  1626                                 ADD_imm8s_r32( 4, R_EAX );
  1627                                 store_reg( R_EAX, Rm );
  1628                                 MEM_READ_LONG( R_ECX, R_EAX );
  1629                                 store_spreg( R_EAX, R_FPSCR );
  1630                                 update_fr_bank( R_EAX );
  1632                                 break;
  1633                             case 0xF:
  1634                                 { /* LDC.L @Rm+, DBR */
  1635                                 uint32_t Rm = ((ir>>8)&0xF); 
  1636                                 check_priv();
  1637                                 load_reg( R_EAX, Rm );
  1638                                 check_ralign32( R_EAX );
  1639                                 MOV_r32_r32( R_EAX, R_ECX );
  1640                                 ADD_imm8s_r32( 4, R_EAX );
  1641                                 store_reg( R_EAX, Rm );
  1642                                 MEM_READ_LONG( R_ECX, R_EAX );
  1643                                 store_spreg( R_EAX, R_DBR );
  1645                                 break;
  1646                             default:
  1647                                 UNDEF();
  1648                                 break;
  1650                         break;
  1651                     case 0x7:
  1652                         switch( (ir&0x80) >> 7 ) {
  1653                             case 0x0:
  1654                                 switch( (ir&0x70) >> 4 ) {
  1655                                     case 0x0:
  1656                                         { /* LDC.L @Rm+, SR */
  1657                                         uint32_t Rm = ((ir>>8)&0xF); 
  1658                                         if( sh4_x86.in_delay_slot ) {
  1659                                     	SLOTILLEGAL();
  1660                                         } else {
  1661                                     	check_priv();
  1662                                     	load_reg( R_EAX, Rm );
  1663                                     	check_ralign32( R_EAX );
  1664                                     	MOV_r32_r32( R_EAX, R_ECX );
  1665                                     	ADD_imm8s_r32( 4, R_EAX );
  1666                                     	store_reg( R_EAX, Rm );
  1667                                     	MEM_READ_LONG( R_ECX, R_EAX );
  1668                                     	call_func1( sh4_write_sr, R_EAX );
  1669                                     	sh4_x86.priv_checked = FALSE;
  1670                                     	sh4_x86.fpuen_checked = FALSE;
  1673                                         break;
  1674                                     case 0x1:
  1675                                         { /* LDC.L @Rm+, GBR */
  1676                                         uint32_t Rm = ((ir>>8)&0xF); 
  1677                                         load_reg( R_EAX, Rm );
  1678                                         check_ralign32( R_EAX );
  1679                                         MOV_r32_r32( R_EAX, R_ECX );
  1680                                         ADD_imm8s_r32( 4, R_EAX );
  1681                                         store_reg( R_EAX, Rm );
  1682                                         MEM_READ_LONG( R_ECX, R_EAX );
  1683                                         store_spreg( R_EAX, R_GBR );
  1685                                         break;
  1686                                     case 0x2:
  1687                                         { /* LDC.L @Rm+, VBR */
  1688                                         uint32_t Rm = ((ir>>8)&0xF); 
  1689                                         check_priv();
  1690                                         load_reg( R_EAX, Rm );
  1691                                         check_ralign32( R_EAX );
  1692                                         MOV_r32_r32( R_EAX, R_ECX );
  1693                                         ADD_imm8s_r32( 4, R_EAX );
  1694                                         store_reg( R_EAX, Rm );
  1695                                         MEM_READ_LONG( R_ECX, R_EAX );
  1696                                         store_spreg( R_EAX, R_VBR );
  1698                                         break;
  1699                                     case 0x3:
  1700                                         { /* LDC.L @Rm+, SSR */
  1701                                         uint32_t Rm = ((ir>>8)&0xF); 
  1702                                         check_priv();
  1703                                         load_reg( R_EAX, Rm );
  1704                                         MOV_r32_r32( R_EAX, R_ECX );
  1705                                         ADD_imm8s_r32( 4, R_EAX );
  1706                                         store_reg( R_EAX, Rm );
  1707                                         MEM_READ_LONG( R_ECX, R_EAX );
  1708                                         store_spreg( R_EAX, R_SSR );
  1710                                         break;
  1711                                     case 0x4:
  1712                                         { /* LDC.L @Rm+, SPC */
  1713                                         uint32_t Rm = ((ir>>8)&0xF); 
  1714                                         check_priv();
  1715                                         load_reg( R_EAX, Rm );
  1716                                         check_ralign32( R_EAX );
  1717                                         MOV_r32_r32( R_EAX, R_ECX );
  1718                                         ADD_imm8s_r32( 4, R_EAX );
  1719                                         store_reg( R_EAX, Rm );
  1720                                         MEM_READ_LONG( R_ECX, R_EAX );
  1721                                         store_spreg( R_EAX, R_SPC );
  1723                                         break;
  1724                                     default:
  1725                                         UNDEF();
  1726                                         break;
  1728                                 break;
  1729                             case 0x1:
  1730                                 { /* LDC.L @Rm+, Rn_BANK */
  1731                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1732                                 check_priv();
  1733                                 load_reg( R_EAX, Rm );
  1734                                 check_ralign32( R_EAX );
  1735                                 MOV_r32_r32( R_EAX, R_ECX );
  1736                                 ADD_imm8s_r32( 4, R_EAX );
  1737                                 store_reg( R_EAX, Rm );
  1738                                 MEM_READ_LONG( R_ECX, R_EAX );
  1739                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  1741                                 break;
  1743                         break;
  1744                     case 0x8:
  1745                         switch( (ir&0xF0) >> 4 ) {
  1746                             case 0x0:
  1747                                 { /* SHLL2 Rn */
  1748                                 uint32_t Rn = ((ir>>8)&0xF); 
  1749                                 load_reg( R_EAX, Rn );
  1750                                 SHL_imm8_r32( 2, R_EAX );
  1751                                 store_reg( R_EAX, Rn );
  1753                                 break;
  1754                             case 0x1:
  1755                                 { /* SHLL8 Rn */
  1756                                 uint32_t Rn = ((ir>>8)&0xF); 
  1757                                 load_reg( R_EAX, Rn );
  1758                                 SHL_imm8_r32( 8, R_EAX );
  1759                                 store_reg( R_EAX, Rn );
  1761                                 break;
  1762                             case 0x2:
  1763                                 { /* SHLL16 Rn */
  1764                                 uint32_t Rn = ((ir>>8)&0xF); 
  1765                                 load_reg( R_EAX, Rn );
  1766                                 SHL_imm8_r32( 16, R_EAX );
  1767                                 store_reg( R_EAX, Rn );
  1769                                 break;
  1770                             default:
  1771                                 UNDEF();
  1772                                 break;
  1774                         break;
  1775                     case 0x9:
  1776                         switch( (ir&0xF0) >> 4 ) {
  1777                             case 0x0:
  1778                                 { /* SHLR2 Rn */
  1779                                 uint32_t Rn = ((ir>>8)&0xF); 
  1780                                 load_reg( R_EAX, Rn );
  1781                                 SHR_imm8_r32( 2, R_EAX );
  1782                                 store_reg( R_EAX, Rn );
  1784                                 break;
  1785                             case 0x1:
  1786                                 { /* SHLR8 Rn */
  1787                                 uint32_t Rn = ((ir>>8)&0xF); 
  1788                                 load_reg( R_EAX, Rn );
  1789                                 SHR_imm8_r32( 8, R_EAX );
  1790                                 store_reg( R_EAX, Rn );
  1792                                 break;
  1793                             case 0x2:
  1794                                 { /* SHLR16 Rn */
  1795                                 uint32_t Rn = ((ir>>8)&0xF); 
  1796                                 load_reg( R_EAX, Rn );
  1797                                 SHR_imm8_r32( 16, R_EAX );
  1798                                 store_reg( R_EAX, Rn );
  1800                                 break;
  1801                             default:
  1802                                 UNDEF();
  1803                                 break;
  1805                         break;
  1806                     case 0xA:
  1807                         switch( (ir&0xF0) >> 4 ) {
  1808                             case 0x0:
  1809                                 { /* LDS Rm, MACH */
  1810                                 uint32_t Rm = ((ir>>8)&0xF); 
  1811                                 load_reg( R_EAX, Rm );
  1812                                 store_spreg( R_EAX, R_MACH );
  1814                                 break;
  1815                             case 0x1:
  1816                                 { /* LDS Rm, MACL */
  1817                                 uint32_t Rm = ((ir>>8)&0xF); 
  1818                                 load_reg( R_EAX, Rm );
  1819                                 store_spreg( R_EAX, R_MACL );
  1821                                 break;
  1822                             case 0x2:
  1823                                 { /* LDS Rm, PR */
  1824                                 uint32_t Rm = ((ir>>8)&0xF); 
  1825                                 load_reg( R_EAX, Rm );
  1826                                 store_spreg( R_EAX, R_PR );
  1828                                 break;
  1829                             case 0x3:
  1830                                 { /* LDC Rm, SGR */
  1831                                 uint32_t Rm = ((ir>>8)&0xF); 
  1832                                 check_priv();
  1833                                 load_reg( R_EAX, Rm );
  1834                                 store_spreg( R_EAX, R_SGR );
  1836                                 break;
  1837                             case 0x5:
  1838                                 { /* LDS Rm, FPUL */
  1839                                 uint32_t Rm = ((ir>>8)&0xF); 
  1840                                 load_reg( R_EAX, Rm );
  1841                                 store_spreg( R_EAX, R_FPUL );
  1843                                 break;
  1844                             case 0x6:
  1845                                 { /* LDS Rm, FPSCR */
  1846                                 uint32_t Rm = ((ir>>8)&0xF); 
  1847                                 load_reg( R_EAX, Rm );
  1848                                 store_spreg( R_EAX, R_FPSCR );
  1849                                 update_fr_bank( R_EAX );
  1851                                 break;
  1852                             case 0xF:
  1853                                 { /* LDC Rm, DBR */
  1854                                 uint32_t Rm = ((ir>>8)&0xF); 
  1855                                 check_priv();
  1856                                 load_reg( R_EAX, Rm );
  1857                                 store_spreg( R_EAX, R_DBR );
  1859                                 break;
  1860                             default:
  1861                                 UNDEF();
  1862                                 break;
  1864                         break;
  1865                     case 0xB:
  1866                         switch( (ir&0xF0) >> 4 ) {
  1867                             case 0x0:
  1868                                 { /* JSR @Rn */
  1869                                 uint32_t Rn = ((ir>>8)&0xF); 
  1870                                 if( sh4_x86.in_delay_slot ) {
  1871                             	SLOTILLEGAL();
  1872                                 } else {
  1873                             	load_imm32( R_EAX, pc + 4 );
  1874                             	store_spreg( R_EAX, R_PR );
  1875                             	load_reg( R_EDI, Rn );
  1876                             	sh4_x86.in_delay_slot = TRUE;
  1877                             	return 0;
  1880                                 break;
  1881                             case 0x1:
  1882                                 { /* TAS.B @Rn */
  1883                                 uint32_t Rn = ((ir>>8)&0xF); 
  1884                                 load_reg( R_ECX, Rn );
  1885                                 MEM_READ_BYTE( R_ECX, R_EAX );
  1886                                 TEST_r8_r8( R_AL, R_AL );
  1887                                 SETE_t();
  1888                                 OR_imm8_r8( 0x80, R_AL );
  1889                                 load_reg( R_ECX, Rn );
  1890                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  1892                                 break;
  1893                             case 0x2:
  1894                                 { /* JMP @Rn */
  1895                                 uint32_t Rn = ((ir>>8)&0xF); 
  1896                                 if( sh4_x86.in_delay_slot ) {
  1897                             	SLOTILLEGAL();
  1898                                 } else {
  1899                             	load_reg( R_EDI, Rn );
  1900                             	sh4_x86.in_delay_slot = TRUE;
  1901                             	return 0;
  1904                                 break;
  1905                             default:
  1906                                 UNDEF();
  1907                                 break;
  1909                         break;
  1910                     case 0xC:
  1911                         { /* SHAD Rm, Rn */
  1912                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1913                         /* Annoyingly enough, not directly convertible */
  1914                         load_reg( R_EAX, Rn );
  1915                         load_reg( R_ECX, Rm );
  1916                         CMP_imm32_r32( 0, R_ECX );
  1917                         JGE_rel8(16, doshl);
  1919                         NEG_r32( R_ECX );      // 2
  1920                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1921                         JE_rel8( 4, emptysar);     // 2
  1922                         SAR_r32_CL( R_EAX );       // 2
  1923                         JMP_rel8(10, end);          // 2
  1925                         JMP_TARGET(emptysar);
  1926                         SAR_imm8_r32(31, R_EAX );  // 3
  1927                         JMP_rel8(5, end2);
  1929                         JMP_TARGET(doshl);
  1930                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1931                         SHL_r32_CL( R_EAX );       // 2
  1932                         JMP_TARGET(end);
  1933                         JMP_TARGET(end2);
  1934                         store_reg( R_EAX, Rn );
  1936                         break;
  1937                     case 0xD:
  1938                         { /* SHLD Rm, Rn */
  1939                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1940                         load_reg( R_EAX, Rn );
  1941                         load_reg( R_ECX, Rm );
  1942                         CMP_imm32_r32( 0, R_ECX );
  1943                         JGE_rel8(15, doshl);
  1945                         NEG_r32( R_ECX );      // 2
  1946                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1947                         JE_rel8( 4, emptyshr );
  1948                         SHR_r32_CL( R_EAX );       // 2
  1949                         JMP_rel8(9, end);          // 2
  1951                         JMP_TARGET(emptyshr);
  1952                         XOR_r32_r32( R_EAX, R_EAX );
  1953                         JMP_rel8(5, end2);
  1955                         JMP_TARGET(doshl);
  1956                         AND_imm8_r8( 0x1F, R_CL ); // 3
  1957                         SHL_r32_CL( R_EAX );       // 2
  1958                         JMP_TARGET(end);
  1959                         JMP_TARGET(end2);
  1960                         store_reg( R_EAX, Rn );
  1962                         break;
  1963                     case 0xE:
  1964                         switch( (ir&0x80) >> 7 ) {
  1965                             case 0x0:
  1966                                 switch( (ir&0x70) >> 4 ) {
  1967                                     case 0x0:
  1968                                         { /* LDC Rm, SR */
  1969                                         uint32_t Rm = ((ir>>8)&0xF); 
  1970                                         if( sh4_x86.in_delay_slot ) {
  1971                                     	SLOTILLEGAL();
  1972                                         } else {
  1973                                     	check_priv();
  1974                                     	load_reg( R_EAX, Rm );
  1975                                     	call_func1( sh4_write_sr, R_EAX );
  1976                                     	sh4_x86.priv_checked = FALSE;
  1977                                     	sh4_x86.fpuen_checked = FALSE;
  1980                                         break;
  1981                                     case 0x1:
  1982                                         { /* LDC Rm, GBR */
  1983                                         uint32_t Rm = ((ir>>8)&0xF); 
  1984                                         load_reg( R_EAX, Rm );
  1985                                         store_spreg( R_EAX, R_GBR );
  1987                                         break;
  1988                                     case 0x2:
  1989                                         { /* LDC Rm, VBR */
  1990                                         uint32_t Rm = ((ir>>8)&0xF); 
  1991                                         check_priv();
  1992                                         load_reg( R_EAX, Rm );
  1993                                         store_spreg( R_EAX, R_VBR );
  1995                                         break;
  1996                                     case 0x3:
  1997                                         { /* LDC Rm, SSR */
  1998                                         uint32_t Rm = ((ir>>8)&0xF); 
  1999                                         check_priv();
  2000                                         load_reg( R_EAX, Rm );
  2001                                         store_spreg( R_EAX, R_SSR );
  2003                                         break;
  2004                                     case 0x4:
  2005                                         { /* LDC Rm, SPC */
  2006                                         uint32_t Rm = ((ir>>8)&0xF); 
  2007                                         check_priv();
  2008                                         load_reg( R_EAX, Rm );
  2009                                         store_spreg( R_EAX, R_SPC );
  2011                                         break;
  2012                                     default:
  2013                                         UNDEF();
  2014                                         break;
  2016                                 break;
  2017                             case 0x1:
  2018                                 { /* LDC Rm, Rn_BANK */
  2019                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  2020                                 check_priv();
  2021                                 load_reg( R_EAX, Rm );
  2022                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2024                                 break;
  2026                         break;
  2027                     case 0xF:
  2028                         { /* MAC.W @Rm+, @Rn+ */
  2029                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2030                         load_reg( R_ECX, Rm );
  2031                         check_ralign16( R_ECX );
  2032                         load_reg( R_ECX, Rn );
  2033                         check_ralign16( R_ECX );
  2034                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  2035                         MEM_READ_WORD( R_ECX, R_EAX );
  2036                         PUSH_r32( R_EAX );
  2037                         load_reg( R_ECX, Rm );
  2038                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2039                         MEM_READ_WORD( R_ECX, R_EAX );
  2040                         POP_r32( R_ECX );
  2041                         IMUL_r32( R_ECX );
  2043                         load_spreg( R_ECX, R_S );
  2044                         TEST_r32_r32( R_ECX, R_ECX );
  2045                         JE_rel8( 47, nosat );
  2047                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2048                         JNO_rel8( 51, end );            // 2
  2049                         load_imm32( R_EDX, 1 );         // 5
  2050                         store_spreg( R_EDX, R_MACH );   // 6
  2051                         JS_rel8( 13, positive );        // 2
  2052                         load_imm32( R_EAX, 0x80000000 );// 5
  2053                         store_spreg( R_EAX, R_MACL );   // 6
  2054                         JMP_rel8( 25, end2 );           // 2
  2056                         JMP_TARGET(positive);
  2057                         load_imm32( R_EAX, 0x7FFFFFFF );// 5
  2058                         store_spreg( R_EAX, R_MACL );   // 6
  2059                         JMP_rel8( 12, end3);            // 2
  2061                         JMP_TARGET(nosat);
  2062                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2063                         ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  2064                         JMP_TARGET(end);
  2065                         JMP_TARGET(end2);
  2066                         JMP_TARGET(end3);
  2068                         break;
  2070                 break;
  2071             case 0x5:
  2072                 { /* MOV.L @(disp, Rm), Rn */
  2073                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  2074                 load_reg( R_ECX, Rm );
  2075                 ADD_imm8s_r32( disp, R_ECX );
  2076                 check_ralign32( R_ECX );
  2077                 MEM_READ_LONG( R_ECX, R_EAX );
  2078                 store_reg( R_EAX, Rn );
  2080                 break;
  2081             case 0x6:
  2082                 switch( ir&0xF ) {
  2083                     case 0x0:
  2084                         { /* MOV.B @Rm, Rn */
  2085                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2086                         load_reg( R_ECX, Rm );
  2087                         MEM_READ_BYTE( R_ECX, R_EAX );
  2088                         store_reg( R_EAX, Rn );
  2090                         break;
  2091                     case 0x1:
  2092                         { /* MOV.W @Rm, Rn */
  2093                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2094                         load_reg( R_ECX, Rm );
  2095                         check_ralign16( R_ECX );
  2096                         MEM_READ_WORD( R_ECX, R_EAX );
  2097                         store_reg( R_EAX, Rn );
  2099                         break;
  2100                     case 0x2:
  2101                         { /* MOV.L @Rm, Rn */
  2102                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2103                         load_reg( R_ECX, Rm );
  2104                         check_ralign32( R_ECX );
  2105                         MEM_READ_LONG( R_ECX, R_EAX );
  2106                         store_reg( R_EAX, Rn );
  2108                         break;
  2109                     case 0x3:
  2110                         { /* MOV Rm, Rn */
  2111                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2112                         load_reg( R_EAX, Rm );
  2113                         store_reg( R_EAX, Rn );
  2115                         break;
  2116                     case 0x4:
  2117                         { /* MOV.B @Rm+, Rn */
  2118                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2119                         load_reg( R_ECX, Rm );
  2120                         MOV_r32_r32( R_ECX, R_EAX );
  2121                         ADD_imm8s_r32( 1, R_EAX );
  2122                         store_reg( R_EAX, Rm );
  2123                         MEM_READ_BYTE( R_ECX, R_EAX );
  2124                         store_reg( R_EAX, Rn );
  2126                         break;
  2127                     case 0x5:
  2128                         { /* MOV.W @Rm+, Rn */
  2129                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2130                         load_reg( R_EAX, Rm );
  2131                         check_ralign16( R_EAX );
  2132                         MOV_r32_r32( R_EAX, R_ECX );
  2133                         ADD_imm8s_r32( 2, R_EAX );
  2134                         store_reg( R_EAX, Rm );
  2135                         MEM_READ_WORD( R_ECX, R_EAX );
  2136                         store_reg( R_EAX, Rn );
  2138                         break;
  2139                     case 0x6:
  2140                         { /* MOV.L @Rm+, Rn */
  2141                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2142                         load_reg( R_EAX, Rm );
  2143                         check_ralign32( R_EAX );
  2144                         MOV_r32_r32( R_EAX, R_ECX );
  2145                         ADD_imm8s_r32( 4, R_EAX );
  2146                         store_reg( R_EAX, Rm );
  2147                         MEM_READ_LONG( R_ECX, R_EAX );
  2148                         store_reg( R_EAX, Rn );
  2150                         break;
  2151                     case 0x7:
  2152                         { /* NOT Rm, Rn */
  2153                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2154                         load_reg( R_EAX, Rm );
  2155                         NOT_r32( R_EAX );
  2156                         store_reg( R_EAX, Rn );
  2158                         break;
  2159                     case 0x8:
  2160                         { /* SWAP.B Rm, Rn */
  2161                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2162                         load_reg( R_EAX, Rm );
  2163                         XCHG_r8_r8( R_AL, R_AH );
  2164                         store_reg( R_EAX, Rn );
  2166                         break;
  2167                     case 0x9:
  2168                         { /* SWAP.W Rm, Rn */
  2169                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2170                         load_reg( R_EAX, Rm );
  2171                         MOV_r32_r32( R_EAX, R_ECX );
  2172                         SHL_imm8_r32( 16, R_ECX );
  2173                         SHR_imm8_r32( 16, R_EAX );
  2174                         OR_r32_r32( R_EAX, R_ECX );
  2175                         store_reg( R_ECX, Rn );
  2177                         break;
  2178                     case 0xA:
  2179                         { /* NEGC Rm, Rn */
  2180                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2181                         load_reg( R_EAX, Rm );
  2182                         XOR_r32_r32( R_ECX, R_ECX );
  2183                         LDC_t();
  2184                         SBB_r32_r32( R_EAX, R_ECX );
  2185                         store_reg( R_ECX, Rn );
  2186                         SETC_t();
  2188                         break;
  2189                     case 0xB:
  2190                         { /* NEG Rm, Rn */
  2191                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2192                         load_reg( R_EAX, Rm );
  2193                         NEG_r32( R_EAX );
  2194                         store_reg( R_EAX, Rn );
  2196                         break;
  2197                     case 0xC:
  2198                         { /* EXTU.B Rm, Rn */
  2199                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2200                         load_reg( R_EAX, Rm );
  2201                         MOVZX_r8_r32( R_EAX, R_EAX );
  2202                         store_reg( R_EAX, Rn );
  2204                         break;
  2205                     case 0xD:
  2206                         { /* EXTU.W Rm, Rn */
  2207                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2208                         load_reg( R_EAX, Rm );
  2209                         MOVZX_r16_r32( R_EAX, R_EAX );
  2210                         store_reg( R_EAX, Rn );
  2212                         break;
  2213                     case 0xE:
  2214                         { /* EXTS.B Rm, Rn */
  2215                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2216                         load_reg( R_EAX, Rm );
  2217                         MOVSX_r8_r32( R_EAX, R_EAX );
  2218                         store_reg( R_EAX, Rn );
  2220                         break;
  2221                     case 0xF:
  2222                         { /* EXTS.W Rm, Rn */
  2223                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2224                         load_reg( R_EAX, Rm );
  2225                         MOVSX_r16_r32( R_EAX, R_EAX );
  2226                         store_reg( R_EAX, Rn );
  2228                         break;
  2230                 break;
  2231             case 0x7:
  2232                 { /* ADD #imm, Rn */
  2233                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2234                 load_reg( R_EAX, Rn );
  2235                 ADD_imm8s_r32( imm, R_EAX );
  2236                 store_reg( R_EAX, Rn );
  2238                 break;
  2239             case 0x8:
  2240                 switch( (ir&0xF00) >> 8 ) {
  2241                     case 0x0:
  2242                         { /* MOV.B R0, @(disp, Rn) */
  2243                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2244                         load_reg( R_EAX, 0 );
  2245                         load_reg( R_ECX, Rn );
  2246                         ADD_imm32_r32( disp, R_ECX );
  2247                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2249                         break;
  2250                     case 0x1:
  2251                         { /* MOV.W R0, @(disp, Rn) */
  2252                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2253                         load_reg( R_ECX, Rn );
  2254                         load_reg( R_EAX, 0 );
  2255                         ADD_imm32_r32( disp, R_ECX );
  2256                         check_walign16( R_ECX );
  2257                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2259                         break;
  2260                     case 0x4:
  2261                         { /* MOV.B @(disp, Rm), R0 */
  2262                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2263                         load_reg( R_ECX, Rm );
  2264                         ADD_imm32_r32( disp, R_ECX );
  2265                         MEM_READ_BYTE( R_ECX, R_EAX );
  2266                         store_reg( R_EAX, 0 );
  2268                         break;
  2269                     case 0x5:
  2270                         { /* MOV.W @(disp, Rm), R0 */
  2271                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2272                         load_reg( R_ECX, Rm );
  2273                         ADD_imm32_r32( disp, R_ECX );
  2274                         check_ralign16( R_ECX );
  2275                         MEM_READ_WORD( R_ECX, R_EAX );
  2276                         store_reg( R_EAX, 0 );
  2278                         break;
  2279                     case 0x8:
  2280                         { /* CMP/EQ #imm, R0 */
  2281                         int32_t imm = SIGNEXT8(ir&0xFF); 
  2282                         load_reg( R_EAX, 0 );
  2283                         CMP_imm8s_r32(imm, R_EAX);
  2284                         SETE_t();
  2286                         break;
  2287                     case 0x9:
  2288                         { /* BT disp */
  2289                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2290                         if( sh4_x86.in_delay_slot ) {
  2291                     	SLOTILLEGAL();
  2292                         } else {
  2293                     	load_imm32( R_EDI, pc + 2 );
  2294                     	CMP_imm8s_sh4r( 0, R_T );
  2295                     	JE_rel8( 5, nottaken );
  2296                     	load_imm32( R_EDI, disp + pc + 4 );
  2297                     	JMP_TARGET(nottaken);
  2298                     	INC_r32(R_ESI);
  2299                     	return 1;
  2302                         break;
  2303                     case 0xB:
  2304                         { /* BF disp */
  2305                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2306                         if( sh4_x86.in_delay_slot ) {
  2307                     	SLOTILLEGAL();
  2308                         } else {
  2309                     	load_imm32( R_EDI, pc + 2 );
  2310                     	CMP_imm8s_sh4r( 0, R_T );
  2311                     	JNE_rel8( 5, nottaken );
  2312                     	load_imm32( R_EDI, disp + pc + 4 );
  2313                     	JMP_TARGET(nottaken);
  2314                     	INC_r32(R_ESI);
  2315                     	return 1;
  2318                         break;
  2319                     case 0xD:
  2320                         { /* BT/S disp */
  2321                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2322                         if( sh4_x86.in_delay_slot ) {
  2323                     	SLOTILLEGAL();
  2324                         } else {
  2325                     	load_imm32( R_EDI, pc + 4 );
  2326                     	CMP_imm8s_sh4r( 0, R_T );
  2327                     	JE_rel8( 5, nottaken );
  2328                     	load_imm32( R_EDI, disp + pc + 4 );
  2329                     	JMP_TARGET(nottaken);
  2330                     	sh4_x86.in_delay_slot = TRUE;
  2331                     	return 0;
  2334                         break;
  2335                     case 0xF:
  2336                         { /* BF/S disp */
  2337                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2338                         if( sh4_x86.in_delay_slot ) {
  2339                     	SLOTILLEGAL();
  2340                         } else {
  2341                     	load_imm32( R_EDI, pc + 4 );
  2342                     	CMP_imm8s_sh4r( 0, R_T );
  2343                     	JNE_rel8( 5, nottaken );
  2344                     	load_imm32( R_EDI, disp + pc + 4 );
  2345                     	JMP_TARGET(nottaken);
  2346                     	sh4_x86.in_delay_slot = TRUE;
  2347                     	return 0;
  2350                         break;
  2351                     default:
  2352                         UNDEF();
  2353                         break;
  2355                 break;
  2356             case 0x9:
  2357                 { /* MOV.W @(disp, PC), Rn */
  2358                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  2359                 if( sh4_x86.in_delay_slot ) {
  2360             	SLOTILLEGAL();
  2361                 } else {
  2362             	load_imm32( R_ECX, pc + disp + 4 );
  2363             	MEM_READ_WORD( R_ECX, R_EAX );
  2364             	store_reg( R_EAX, Rn );
  2367                 break;
  2368             case 0xA:
  2369                 { /* BRA disp */
  2370                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2371                 if( sh4_x86.in_delay_slot ) {
  2372             	SLOTILLEGAL();
  2373                 } else {
  2374             	load_imm32( R_EDI, disp + pc + 4 );
  2375             	sh4_x86.in_delay_slot = TRUE;
  2376             	return 0;
  2379                 break;
  2380             case 0xB:
  2381                 { /* BSR disp */
  2382                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2383                 if( sh4_x86.in_delay_slot ) {
  2384             	SLOTILLEGAL();
  2385                 } else {
  2386             	load_imm32( R_EAX, pc + 4 );
  2387             	store_spreg( R_EAX, R_PR );
  2388             	load_imm32( R_EDI, disp + pc + 4 );
  2389             	sh4_x86.in_delay_slot = TRUE;
  2390             	return 0;
  2393                 break;
  2394             case 0xC:
  2395                 switch( (ir&0xF00) >> 8 ) {
  2396                     case 0x0:
  2397                         { /* MOV.B R0, @(disp, GBR) */
  2398                         uint32_t disp = (ir&0xFF); 
  2399                         load_reg( R_EAX, 0 );
  2400                         load_spreg( R_ECX, R_GBR );
  2401                         ADD_imm32_r32( disp, R_ECX );
  2402                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2404                         break;
  2405                     case 0x1:
  2406                         { /* MOV.W R0, @(disp, GBR) */
  2407                         uint32_t disp = (ir&0xFF)<<1; 
  2408                         load_spreg( R_ECX, R_GBR );
  2409                         load_reg( R_EAX, 0 );
  2410                         ADD_imm32_r32( disp, R_ECX );
  2411                         check_walign16( R_ECX );
  2412                         MEM_WRITE_WORD( R_ECX, R_EAX );
  2414                         break;
  2415                     case 0x2:
  2416                         { /* MOV.L R0, @(disp, GBR) */
  2417                         uint32_t disp = (ir&0xFF)<<2; 
  2418                         load_spreg( R_ECX, R_GBR );
  2419                         load_reg( R_EAX, 0 );
  2420                         ADD_imm32_r32( disp, R_ECX );
  2421                         check_walign32( R_ECX );
  2422                         MEM_WRITE_LONG( R_ECX, R_EAX );
  2424                         break;
  2425                     case 0x3:
  2426                         { /* TRAPA #imm */
  2427                         uint32_t imm = (ir&0xFF); 
  2428                         if( sh4_x86.in_delay_slot ) {
  2429                     	SLOTILLEGAL();
  2430                         } else {
  2431                     	PUSH_imm32( imm );
  2432                     	call_func0( sh4_raise_trap );
  2433                     	ADD_imm8s_r32( 4, R_ESP );
  2436                         break;
  2437                     case 0x4:
  2438                         { /* MOV.B @(disp, GBR), R0 */
  2439                         uint32_t disp = (ir&0xFF); 
  2440                         load_spreg( R_ECX, R_GBR );
  2441                         ADD_imm32_r32( disp, R_ECX );
  2442                         MEM_READ_BYTE( R_ECX, R_EAX );
  2443                         store_reg( R_EAX, 0 );
  2445                         break;
  2446                     case 0x5:
  2447                         { /* MOV.W @(disp, GBR), R0 */
  2448                         uint32_t disp = (ir&0xFF)<<1; 
  2449                         load_spreg( R_ECX, R_GBR );
  2450                         ADD_imm32_r32( disp, R_ECX );
  2451                         check_ralign16( R_ECX );
  2452                         MEM_READ_WORD( R_ECX, R_EAX );
  2453                         store_reg( R_EAX, 0 );
  2455                         break;
  2456                     case 0x6:
  2457                         { /* MOV.L @(disp, GBR), R0 */
  2458                         uint32_t disp = (ir&0xFF)<<2; 
  2459                         load_spreg( R_ECX, R_GBR );
  2460                         ADD_imm32_r32( disp, R_ECX );
  2461                         check_ralign32( R_ECX );
  2462                         MEM_READ_LONG( R_ECX, R_EAX );
  2463                         store_reg( R_EAX, 0 );
  2465                         break;
  2466                     case 0x7:
  2467                         { /* MOVA @(disp, PC), R0 */
  2468                         uint32_t disp = (ir&0xFF)<<2; 
  2469                         if( sh4_x86.in_delay_slot ) {
  2470                     	SLOTILLEGAL();
  2471                         } else {
  2472                     	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
  2473                     	store_reg( R_ECX, 0 );
  2476                         break;
  2477                     case 0x8:
  2478                         { /* TST #imm, R0 */
  2479                         uint32_t imm = (ir&0xFF); 
  2480                         load_reg( R_EAX, 0 );
  2481                         TEST_imm32_r32( imm, R_EAX );
  2482                         SETE_t();
  2484                         break;
  2485                     case 0x9:
  2486                         { /* AND #imm, R0 */
  2487                         uint32_t imm = (ir&0xFF); 
  2488                         load_reg( R_EAX, 0 );
  2489                         AND_imm32_r32(imm, R_EAX); 
  2490                         store_reg( R_EAX, 0 );
  2492                         break;
  2493                     case 0xA:
  2494                         { /* XOR #imm, R0 */
  2495                         uint32_t imm = (ir&0xFF); 
  2496                         load_reg( R_EAX, 0 );
  2497                         XOR_imm32_r32( imm, R_EAX );
  2498                         store_reg( R_EAX, 0 );
  2500                         break;
  2501                     case 0xB:
  2502                         { /* OR #imm, R0 */
  2503                         uint32_t imm = (ir&0xFF); 
  2504                         load_reg( R_EAX, 0 );
  2505                         OR_imm32_r32(imm, R_EAX);
  2506                         store_reg( R_EAX, 0 );
  2508                         break;
  2509                     case 0xC:
  2510                         { /* TST.B #imm, @(R0, GBR) */
  2511                         uint32_t imm = (ir&0xFF); 
  2512                         load_reg( R_EAX, 0);
  2513                         load_reg( R_ECX, R_GBR);
  2514                         ADD_r32_r32( R_EAX, R_ECX );
  2515                         MEM_READ_BYTE( R_ECX, R_EAX );
  2516                         TEST_imm8_r8( imm, R_AL );
  2517                         SETE_t();
  2519                         break;
  2520                     case 0xD:
  2521                         { /* AND.B #imm, @(R0, GBR) */
  2522                         uint32_t imm = (ir&0xFF); 
  2523                         load_reg( R_EAX, 0 );
  2524                         load_spreg( R_ECX, R_GBR );
  2525                         ADD_r32_r32( R_EAX, R_ECX );
  2526                         PUSH_r32(R_ECX);
  2527                         call_func0(sh4_read_byte);
  2528                         POP_r32(R_ECX);
  2529                         AND_imm32_r32(imm, R_EAX );
  2530                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2532                         break;
  2533                     case 0xE:
  2534                         { /* XOR.B #imm, @(R0, GBR) */
  2535                         uint32_t imm = (ir&0xFF); 
  2536                         load_reg( R_EAX, 0 );
  2537                         load_spreg( R_ECX, R_GBR );
  2538                         ADD_r32_r32( R_EAX, R_ECX );
  2539                         PUSH_r32(R_ECX);
  2540                         call_func0(sh4_read_byte);
  2541                         POP_r32(R_ECX);
  2542                         XOR_imm32_r32( imm, R_EAX );
  2543                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2545                         break;
  2546                     case 0xF:
  2547                         { /* OR.B #imm, @(R0, GBR) */
  2548                         uint32_t imm = (ir&0xFF); 
  2549                         load_reg( R_EAX, 0 );
  2550                         load_spreg( R_ECX, R_GBR );
  2551                         ADD_r32_r32( R_EAX, R_ECX );
  2552                         PUSH_r32(R_ECX);
  2553                         call_func0(sh4_read_byte);
  2554                         POP_r32(R_ECX);
  2555                         OR_imm32_r32(imm, R_EAX );
  2556                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2558                         break;
  2560                 break;
  2561             case 0xD:
  2562                 { /* MOV.L @(disp, PC), Rn */
  2563                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2564                 if( sh4_x86.in_delay_slot ) {
  2565             	SLOTILLEGAL();
  2566                 } else {
  2567             	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  2568             	char *ptr = mem_get_region(target);
  2569             	if( ptr != NULL ) {
  2570             	    MOV_moff32_EAX( (uint32_t)ptr );
  2571             	} else {
  2572             	    load_imm32( R_ECX, target );
  2573             	    MEM_READ_LONG( R_ECX, R_EAX );
  2575             	store_reg( R_EAX, Rn );
  2578                 break;
  2579             case 0xE:
  2580                 { /* MOV #imm, Rn */
  2581                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2582                 load_imm32( R_EAX, imm );
  2583                 store_reg( R_EAX, Rn );
  2585                 break;
  2586             case 0xF:
  2587                 switch( ir&0xF ) {
  2588                     case 0x0:
  2589                         { /* FADD FRm, FRn */
  2590                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2591                         check_fpuen();
  2592                         load_spreg( R_ECX, R_FPSCR );
  2593                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2594                         load_fr_bank( R_EDX );
  2595                         JNE_rel8(13,doubleprec);
  2596                         push_fr(R_EDX, FRm);
  2597                         push_fr(R_EDX, FRn);
  2598                         FADDP_st(1);
  2599                         pop_fr(R_EDX, FRn);
  2600                         JMP_rel8(11,end);
  2601                         JMP_TARGET(doubleprec);
  2602                         push_dr(R_EDX, FRm);
  2603                         push_dr(R_EDX, FRn);
  2604                         FADDP_st(1);
  2605                         pop_dr(R_EDX, FRn);
  2606                         JMP_TARGET(end);
  2608                         break;
  2609                     case 0x1:
  2610                         { /* FSUB FRm, FRn */
  2611                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2612                         check_fpuen();
  2613                         load_spreg( R_ECX, R_FPSCR );
  2614                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2615                         load_fr_bank( R_EDX );
  2616                         JNE_rel8(13, doubleprec);
  2617                         push_fr(R_EDX, FRn);
  2618                         push_fr(R_EDX, FRm);
  2619                         FSUBP_st(1);
  2620                         pop_fr(R_EDX, FRn);
  2621                         JMP_rel8(11, end);
  2622                         JMP_TARGET(doubleprec);
  2623                         push_dr(R_EDX, FRn);
  2624                         push_dr(R_EDX, FRm);
  2625                         FSUBP_st(1);
  2626                         pop_dr(R_EDX, FRn);
  2627                         JMP_TARGET(end);
  2629                         break;
  2630                     case 0x2:
  2631                         { /* FMUL FRm, FRn */
  2632                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2633                         check_fpuen();
  2634                         load_spreg( R_ECX, R_FPSCR );
  2635                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2636                         load_fr_bank( R_EDX );
  2637                         JNE_rel8(13, doubleprec);
  2638                         push_fr(R_EDX, FRm);
  2639                         push_fr(R_EDX, FRn);
  2640                         FMULP_st(1);
  2641                         pop_fr(R_EDX, FRn);
  2642                         JMP_rel8(11, end);
  2643                         JMP_TARGET(doubleprec);
  2644                         push_dr(R_EDX, FRm);
  2645                         push_dr(R_EDX, FRn);
  2646                         FMULP_st(1);
  2647                         pop_dr(R_EDX, FRn);
  2648                         JMP_TARGET(end);
  2650                         break;
  2651                     case 0x3:
  2652                         { /* FDIV FRm, FRn */
  2653                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2654                         check_fpuen();
  2655                         load_spreg( R_ECX, R_FPSCR );
  2656                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2657                         load_fr_bank( R_EDX );
  2658                         JNE_rel8(13, doubleprec);
  2659                         push_fr(R_EDX, FRn);
  2660                         push_fr(R_EDX, FRm);
  2661                         FDIVP_st(1);
  2662                         pop_fr(R_EDX, FRn);
  2663                         JMP_rel8(11, end);
  2664                         JMP_TARGET(doubleprec);
  2665                         push_dr(R_EDX, FRn);
  2666                         push_dr(R_EDX, FRm);
  2667                         FDIVP_st(1);
  2668                         pop_dr(R_EDX, FRn);
  2669                         JMP_TARGET(end);
  2671                         break;
  2672                     case 0x4:
  2673                         { /* FCMP/EQ FRm, FRn */
  2674                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2675                         check_fpuen();
  2676                         load_spreg( R_ECX, R_FPSCR );
  2677                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2678                         load_fr_bank( R_EDX );
  2679                         JNE_rel8(8, doubleprec);
  2680                         push_fr(R_EDX, FRm);
  2681                         push_fr(R_EDX, FRn);
  2682                         JMP_rel8(6, end);
  2683                         JMP_TARGET(doubleprec);
  2684                         push_dr(R_EDX, FRm);
  2685                         push_dr(R_EDX, FRn);
  2686                         JMP_TARGET(end);
  2687                         FCOMIP_st(1);
  2688                         SETE_t();
  2689                         FPOP_st();
  2691                         break;
  2692                     case 0x5:
  2693                         { /* FCMP/GT FRm, FRn */
  2694                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2695                         check_fpuen();
  2696                         load_spreg( R_ECX, R_FPSCR );
  2697                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2698                         load_fr_bank( R_EDX );
  2699                         JNE_rel8(8, doubleprec);
  2700                         push_fr(R_EDX, FRm);
  2701                         push_fr(R_EDX, FRn);
  2702                         JMP_rel8(6, end);
  2703                         JMP_TARGET(doubleprec);
  2704                         push_dr(R_EDX, FRm);
  2705                         push_dr(R_EDX, FRn);
  2706                         JMP_TARGET(end);
  2707                         FCOMIP_st(1);
  2708                         SETA_t();
  2709                         FPOP_st();
  2711                         break;
  2712                     case 0x6:
  2713                         { /* FMOV @(R0, Rm), FRn */
  2714                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2715                         check_fpuen();
  2716                         load_reg( R_EDX, Rm );
  2717                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
  2718                         check_ralign32( R_EDX );
  2719                         load_spreg( R_ECX, R_FPSCR );
  2720                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2721                         JNE_rel8(19, doublesize);
  2722                         MEM_READ_LONG( R_EDX, R_EAX );
  2723                         load_fr_bank( R_ECX );
  2724                         store_fr( R_ECX, R_EAX, FRn );
  2725                         if( FRn&1 ) {
  2726                     	JMP_rel8(48, end);
  2727                     	JMP_TARGET(doublesize);
  2728                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2729                     	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
  2730                     	load_xf_bank( R_ECX );
  2731                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2732                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2733                     	JMP_TARGET(end);
  2734                         } else {
  2735                     	JMP_rel8(36, end);
  2736                     	JMP_TARGET(doublesize);
  2737                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2738                     	load_fr_bank( R_ECX );
  2739                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2740                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2741                     	JMP_TARGET(end);
  2744                         break;
  2745                     case 0x7:
  2746                         { /* FMOV FRm, @(R0, Rn) */
  2747                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2748                         check_fpuen();
  2749                         load_reg( R_EDX, Rn );
  2750                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
  2751                         check_walign32( R_EDX );
  2752                         load_spreg( R_ECX, R_FPSCR );
  2753                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2754                         JNE_rel8(20, doublesize);
  2755                         load_fr_bank( R_ECX );
  2756                         load_fr( R_ECX, R_EAX, FRm );
  2757                         MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
  2758                         if( FRm&1 ) {
  2759                     	JMP_rel8( 48, end );
  2760                     	JMP_TARGET(doublesize);
  2761                     	load_xf_bank( R_ECX );
  2762                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2763                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2764                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2765                     	JMP_TARGET(end);
  2766                         } else {
  2767                     	JMP_rel8( 39, end );
  2768                     	JMP_TARGET(doublesize);
  2769                     	load_fr_bank( R_ECX );
  2770                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2771                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2772                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2773                     	JMP_TARGET(end);
  2776                         break;
  2777                     case 0x8:
  2778                         { /* FMOV @Rm, FRn */
  2779                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2780                         check_fpuen();
  2781                         load_reg( R_EDX, Rm );
  2782                         check_ralign32( R_EDX );
  2783                         load_spreg( R_ECX, R_FPSCR );
  2784                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2785                         JNE_rel8(19, doublesize);
  2786                         MEM_READ_LONG( R_EDX, R_EAX );
  2787                         load_fr_bank( R_ECX );
  2788                         store_fr( R_ECX, R_EAX, FRn );
  2789                         if( FRn&1 ) {
  2790                     	JMP_rel8(48, end);
  2791                     	JMP_TARGET(doublesize);
  2792                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2793                     	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
  2794                     	load_xf_bank( R_ECX );
  2795                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2796                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2797                     	JMP_TARGET(end);
  2798                         } else {
  2799                     	JMP_rel8(36, end);
  2800                     	JMP_TARGET(doublesize);
  2801                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2802                     	load_fr_bank( R_ECX );
  2803                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2804                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2805                     	JMP_TARGET(end);
  2808                         break;
  2809                     case 0x9:
  2810                         { /* FMOV @Rm+, FRn */
  2811                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2812                         check_fpuen();
  2813                         load_reg( R_EDX, Rm );
  2814                         check_ralign32( R_EDX );
  2815                         MOV_r32_r32( R_EDX, R_EAX );
  2816                         load_spreg( R_ECX, R_FPSCR );
  2817                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2818                         JNE_rel8(25, doublesize);
  2819                         ADD_imm8s_r32( 4, R_EAX );
  2820                         store_reg( R_EAX, Rm );
  2821                         MEM_READ_LONG( R_EDX, R_EAX );
  2822                         load_fr_bank( R_ECX );
  2823                         store_fr( R_ECX, R_EAX, FRn );
  2824                         if( FRn&1 ) {
  2825                     	JMP_rel8(54, end);
  2826                     	JMP_TARGET(doublesize);
  2827                     	ADD_imm8s_r32( 8, R_EAX );
  2828                     	store_reg(R_EAX, Rm);
  2829                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2830                     	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
  2831                     	load_xf_bank( R_ECX );
  2832                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2833                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2834                     	JMP_TARGET(end);
  2835                         } else {
  2836                     	JMP_rel8(42, end);
  2837                     	ADD_imm8s_r32( 8, R_EAX );
  2838                     	store_reg(R_EAX, Rm);
  2839                     	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
  2840                     	load_fr_bank( R_ECX );
  2841                     	store_fr( R_ECX, R_EAX, FRn&0x0E );
  2842                     	store_fr( R_ECX, R_EDX, FRn|0x01 );
  2843                     	JMP_TARGET(end);
  2846                         break;
  2847                     case 0xA:
  2848                         { /* FMOV FRm, @Rn */
  2849                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2850                         check_fpuen();
  2851                         load_reg( R_EDX, Rn );
  2852                         check_walign32( R_EDX );
  2853                         load_spreg( R_ECX, R_FPSCR );
  2854                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2855                         JNE_rel8(20, doublesize);
  2856                         load_fr_bank( R_ECX );
  2857                         load_fr( R_ECX, R_EAX, FRm );
  2858                         MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
  2859                         if( FRm&1 ) {
  2860                     	JMP_rel8( 48, end );
  2861                     	JMP_TARGET(doublesize);
  2862                     	load_xf_bank( R_ECX );
  2863                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2864                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2865                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2866                     	JMP_TARGET(end);
  2867                         } else {
  2868                     	JMP_rel8( 39, end );
  2869                     	JMP_TARGET(doublesize);
  2870                     	load_fr_bank( R_ECX );
  2871                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2872                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2873                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2874                     	JMP_TARGET(end);
  2877                         break;
  2878                     case 0xB:
  2879                         { /* FMOV FRm, @-Rn */
  2880                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2881                         check_fpuen();
  2882                         load_reg( R_EDX, Rn );
  2883                         check_walign32( R_EDX );
  2884                         load_spreg( R_ECX, R_FPSCR );
  2885                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2886                         JNE_rel8(26, doublesize);
  2887                         load_fr_bank( R_ECX );
  2888                         load_fr( R_ECX, R_EAX, FRm );
  2889                         ADD_imm8s_r32(-4,R_EDX);
  2890                         store_reg( R_EDX, Rn );
  2891                         MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
  2892                         if( FRm&1 ) {
  2893                     	JMP_rel8( 54, end );
  2894                     	JMP_TARGET(doublesize);
  2895                     	load_xf_bank( R_ECX );
  2896                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2897                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2898                     	ADD_imm8s_r32(-8,R_EDX);
  2899                     	store_reg( R_EDX, Rn );
  2900                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2901                     	JMP_TARGET(end);
  2902                         } else {
  2903                     	JMP_rel8( 45, end );
  2904                     	JMP_TARGET(doublesize);
  2905                     	load_fr_bank( R_ECX );
  2906                     	load_fr( R_ECX, R_EAX, FRm&0x0E );
  2907                     	load_fr( R_ECX, R_ECX, FRm|0x01 );
  2908                     	ADD_imm8s_r32(-8,R_EDX);
  2909                     	store_reg( R_EDX, Rn );
  2910                     	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
  2911                     	JMP_TARGET(end);
  2914                         break;
  2915                     case 0xC:
  2916                         { /* FMOV FRm, FRn */
  2917                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2918                         /* As horrible as this looks, it's actually covering 5 separate cases:
  2919                          * 1. 32-bit fr-to-fr (PR=0)
  2920                          * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
  2921                          * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
  2922                          * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
  2923                          * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
  2924                          */
  2925                         check_fpuen();
  2926                         load_spreg( R_ECX, R_FPSCR );
  2927                         load_fr_bank( R_EDX );
  2928                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  2929                         JNE_rel8(8, doublesize);
  2930                         load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
  2931                         store_fr( R_EDX, R_EAX, FRn );
  2932                         if( FRm&1 ) {
  2933                     	JMP_rel8(24, end);
  2934                     	JMP_TARGET(doublesize);
  2935                     	load_xf_bank( R_ECX ); 
  2936                     	load_fr( R_ECX, R_EAX, FRm-1 );
  2937                     	if( FRn&1 ) {
  2938                     	    load_fr( R_ECX, R_EDX, FRm );
  2939                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  2940                     	    store_fr( R_ECX, R_EDX, FRn );
  2941                     	} else /* FRn&1 == 0 */ {
  2942                     	    load_fr( R_ECX, R_ECX, FRm );
  2943                     	    store_fr( R_EDX, R_EAX, FRn );
  2944                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  2946                     	JMP_TARGET(end);
  2947                         } else /* FRm&1 == 0 */ {
  2948                     	if( FRn&1 ) {
  2949                     	    JMP_rel8(24, end);
  2950                     	    load_xf_bank( R_ECX );
  2951                     	    load_fr( R_EDX, R_EAX, FRm );
  2952                     	    load_fr( R_EDX, R_EDX, FRm+1 );
  2953                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  2954                     	    store_fr( R_ECX, R_EDX, FRn );
  2955                     	    JMP_TARGET(end);
  2956                     	} else /* FRn&1 == 0 */ {
  2957                     	    JMP_rel8(12, end);
  2958                     	    load_fr( R_EDX, R_EAX, FRm );
  2959                     	    load_fr( R_EDX, R_ECX, FRm+1 );
  2960                     	    store_fr( R_EDX, R_EAX, FRn );
  2961                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  2962                     	    JMP_TARGET(end);
  2966                         break;
  2967                     case 0xD:
  2968                         switch( (ir&0xF0) >> 4 ) {
  2969                             case 0x0:
  2970                                 { /* FSTS FPUL, FRn */
  2971                                 uint32_t FRn = ((ir>>8)&0xF); 
  2972                                 check_fpuen();
  2973                                 load_fr_bank( R_ECX );
  2974                                 load_spreg( R_EAX, R_FPUL );
  2975                                 store_fr( R_ECX, R_EAX, FRn );
  2977                                 break;
  2978                             case 0x1:
  2979                                 { /* FLDS FRm, FPUL */
  2980                                 uint32_t FRm = ((ir>>8)&0xF); 
  2981                                 check_fpuen();
  2982                                 load_fr_bank( R_ECX );
  2983                                 load_fr( R_ECX, R_EAX, FRm );
  2984                                 store_spreg( R_EAX, R_FPUL );
  2986                                 break;
  2987                             case 0x2:
  2988                                 { /* FLOAT FPUL, FRn */
  2989                                 uint32_t FRn = ((ir>>8)&0xF); 
  2990                                 check_fpuen();
  2991                                 load_spreg( R_ECX, R_FPSCR );
  2992                                 load_spreg(R_EDX, REG_OFFSET(fr_bank));
  2993                                 FILD_sh4r(R_FPUL);
  2994                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  2995                                 JNE_rel8(5, doubleprec);
  2996                                 pop_fr( R_EDX, FRn );
  2997                                 JMP_rel8(3, end);
  2998                                 JMP_TARGET(doubleprec);
  2999                                 pop_dr( R_EDX, FRn );
  3000                                 JMP_TARGET(end);
  3002                                 break;
  3003                             case 0x3:
  3004                                 { /* FTRC FRm, FPUL */
  3005                                 uint32_t FRm = ((ir>>8)&0xF); 
  3006                                 check_fpuen();
  3007                                 load_spreg( R_ECX, R_FPSCR );
  3008                                 load_fr_bank( R_EDX );
  3009                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3010                                 JNE_rel8(5, doubleprec);
  3011                                 push_fr( R_EDX, FRm );
  3012                                 JMP_rel8(3, doop);
  3013                                 JMP_TARGET(doubleprec);
  3014                                 push_dr( R_EDX, FRm );
  3015                                 JMP_TARGET( doop );
  3016                                 load_imm32( R_ECX, (uint32_t)&max_int );
  3017                                 FILD_r32ind( R_ECX );
  3018                                 FCOMIP_st(1);
  3019                                 JNA_rel8( 32, sat );
  3020                                 load_imm32( R_ECX, (uint32_t)&min_int );  // 5
  3021                                 FILD_r32ind( R_ECX );           // 2
  3022                                 FCOMIP_st(1);                   // 2
  3023                                 JAE_rel8( 21, sat2 );            // 2
  3024                                 load_imm32( R_EAX, (uint32_t)&save_fcw );
  3025                                 FNSTCW_r32ind( R_EAX );
  3026                                 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
  3027                                 FLDCW_r32ind( R_EDX );
  3028                                 FISTP_sh4r(R_FPUL);             // 3
  3029                                 FLDCW_r32ind( R_EAX );
  3030                                 JMP_rel8( 9, end );             // 2
  3032                                 JMP_TARGET(sat);
  3033                                 JMP_TARGET(sat2);
  3034                                 MOV_r32ind_r32( R_ECX, R_ECX ); // 2
  3035                                 store_spreg( R_ECX, R_FPUL );
  3036                                 FPOP_st();
  3037                                 JMP_TARGET(end);
  3039                                 break;
  3040                             case 0x4:
  3041                                 { /* FNEG FRn */
  3042                                 uint32_t FRn = ((ir>>8)&0xF); 
  3043                                 check_fpuen();
  3044                                 load_spreg( R_ECX, R_FPSCR );
  3045                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3046                                 load_fr_bank( R_EDX );
  3047                                 JNE_rel8(10, doubleprec);
  3048                                 push_fr(R_EDX, FRn);
  3049                                 FCHS_st0();
  3050                                 pop_fr(R_EDX, FRn);
  3051                                 JMP_rel8(8, end);
  3052                                 JMP_TARGET(doubleprec);
  3053                                 push_dr(R_EDX, FRn);
  3054                                 FCHS_st0();
  3055                                 pop_dr(R_EDX, FRn);
  3056                                 JMP_TARGET(end);
  3058                                 break;
  3059                             case 0x5:
  3060                                 { /* FABS FRn */
  3061                                 uint32_t FRn = ((ir>>8)&0xF); 
  3062                                 check_fpuen();
  3063                                 load_spreg( R_ECX, R_FPSCR );
  3064                                 load_fr_bank( R_EDX );
  3065                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3066                                 JNE_rel8(10, doubleprec);
  3067                                 push_fr(R_EDX, FRn); // 3
  3068                                 FABS_st0(); // 2
  3069                                 pop_fr( R_EDX, FRn); //3
  3070                                 JMP_rel8(8,end); // 2
  3071                                 JMP_TARGET(doubleprec);
  3072                                 push_dr(R_EDX, FRn);
  3073                                 FABS_st0();
  3074                                 pop_dr(R_EDX, FRn);
  3075                                 JMP_TARGET(end);
  3077                                 break;
  3078                             case 0x6:
  3079                                 { /* FSQRT FRn */
  3080                                 uint32_t FRn = ((ir>>8)&0xF); 
  3081                                 check_fpuen();
  3082                                 load_spreg( R_ECX, R_FPSCR );
  3083                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3084                                 load_fr_bank( R_EDX );
  3085                                 JNE_rel8(10, doubleprec);
  3086                                 push_fr(R_EDX, FRn);
  3087                                 FSQRT_st0();
  3088                                 pop_fr(R_EDX, FRn);
  3089                                 JMP_rel8(8, end);
  3090                                 JMP_TARGET(doubleprec);
  3091                                 push_dr(R_EDX, FRn);
  3092                                 FSQRT_st0();
  3093                                 pop_dr(R_EDX, FRn);
  3094                                 JMP_TARGET(end);
  3096                                 break;
  3097                             case 0x7:
  3098                                 { /* FSRRA FRn */
  3099                                 uint32_t FRn = ((ir>>8)&0xF); 
  3100                                 check_fpuen();
  3101                                 load_spreg( R_ECX, R_FPSCR );
  3102                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3103                                 load_fr_bank( R_EDX );
  3104                                 JNE_rel8(12, end); // PR=0 only
  3105                                 FLD1_st0();
  3106                                 push_fr(R_EDX, FRn);
  3107                                 FSQRT_st0();
  3108                                 FDIVP_st(1);
  3109                                 pop_fr(R_EDX, FRn);
  3110                                 JMP_TARGET(end);
  3112                                 break;
  3113                             case 0x8:
  3114                                 { /* FLDI0 FRn */
  3115                                 uint32_t FRn = ((ir>>8)&0xF); 
  3116                                 /* IFF PR=0 */
  3117                                   check_fpuen();
  3118                                   load_spreg( R_ECX, R_FPSCR );
  3119                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3120                                   JNE_rel8(8, end);
  3121                                   XOR_r32_r32( R_EAX, R_EAX );
  3122                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3123                                   store_fr( R_ECX, R_EAX, FRn );
  3124                                   JMP_TARGET(end);
  3126                                 break;
  3127                             case 0x9:
  3128                                 { /* FLDI1 FRn */
  3129                                 uint32_t FRn = ((ir>>8)&0xF); 
  3130                                 /* IFF PR=0 */
  3131                                   check_fpuen();
  3132                                   load_spreg( R_ECX, R_FPSCR );
  3133                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3134                                   JNE_rel8(11, end);
  3135                                   load_imm32(R_EAX, 0x3F800000);
  3136                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3137                                   store_fr( R_ECX, R_EAX, FRn );
  3138                                   JMP_TARGET(end);
  3140                                 break;
  3141                             case 0xA:
  3142                                 { /* FCNVSD FPUL, FRn */
  3143                                 uint32_t FRn = ((ir>>8)&0xF); 
  3144                                 check_fpuen();
  3145                                 load_spreg( R_ECX, R_FPSCR );
  3146                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3147                                 JE_rel8(9, end); // only when PR=1
  3148                                 load_fr_bank( R_ECX );
  3149                                 push_fpul();
  3150                                 pop_dr( R_ECX, FRn );
  3151                                 JMP_TARGET(end);
  3153                                 break;
  3154                             case 0xB:
  3155                                 { /* FCNVDS FRm, FPUL */
  3156                                 uint32_t FRm = ((ir>>8)&0xF); 
  3157                                 check_fpuen();
  3158                                 load_spreg( R_ECX, R_FPSCR );
  3159                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3160                                 JE_rel8(9, end); // only when PR=1
  3161                                 load_fr_bank( R_ECX );
  3162                                 push_dr( R_ECX, FRm );
  3163                                 pop_fpul();
  3164                                 JMP_TARGET(end);
  3166                                 break;
  3167                             case 0xE:
  3168                                 { /* FIPR FVm, FVn */
  3169                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  3170                                 check_fpuen();
  3171                                 load_spreg( R_ECX, R_FPSCR );
  3172                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3173                                 JNE_rel8(44, doubleprec);
  3175                                 load_fr_bank( R_ECX );
  3176                                 push_fr( R_ECX, FVm<<2 );
  3177                                 push_fr( R_ECX, FVn<<2 );
  3178                                 FMULP_st(1);
  3179                                 push_fr( R_ECX, (FVm<<2)+1);
  3180                                 push_fr( R_ECX, (FVn<<2)+1);
  3181                                 FMULP_st(1);
  3182                                 FADDP_st(1);
  3183                                 push_fr( R_ECX, (FVm<<2)+2);
  3184                                 push_fr( R_ECX, (FVn<<2)+2);
  3185                                 FMULP_st(1);
  3186                                 FADDP_st(1);
  3187                                 push_fr( R_ECX, (FVm<<2)+3);
  3188                                 push_fr( R_ECX, (FVn<<2)+3);
  3189                                 FMULP_st(1);
  3190                                 FADDP_st(1);
  3191                                 pop_fr( R_ECX, (FVn<<2)+3);
  3192                                 JMP_TARGET(doubleprec);
  3194                                 break;
  3195                             case 0xF:
  3196                                 switch( (ir&0x100) >> 8 ) {
  3197                                     case 0x0:
  3198                                         { /* FSCA FPUL, FRn */
  3199                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  3200                                         check_fpuen();
  3201                                         load_spreg( R_ECX, R_FPSCR );
  3202                                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3203                                         JNE_rel8( 21, doubleprec );
  3204                                         load_fr_bank( R_ECX );
  3205                                         ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
  3206                                         load_spreg( R_EDX, R_FPUL );
  3207                                         call_func2( sh4_fsca, R_EDX, R_ECX );
  3208                                         JMP_TARGET(doubleprec);
  3210                                         break;
  3211                                     case 0x1:
  3212                                         switch( (ir&0x200) >> 9 ) {
  3213                                             case 0x0:
  3214                                                 { /* FTRV XMTRX, FVn */
  3215                                                 uint32_t FVn = ((ir>>10)&0x3); 
  3216                                                 check_fpuen();
  3217                                                 load_spreg( R_ECX, R_FPSCR );
  3218                                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3219                                                 JNE_rel8( 30, doubleprec );
  3220                                                 load_fr_bank( R_EDX );                 // 3
  3221                                                 ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
  3222                                                 load_xf_bank( R_ECX );                 // 12
  3223                                                 call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
  3224                                                 JMP_TARGET(doubleprec);
  3226                                                 break;
  3227                                             case 0x1:
  3228                                                 switch( (ir&0xC00) >> 10 ) {
  3229                                                     case 0x0:
  3230                                                         { /* FSCHG */
  3231                                                         check_fpuen();
  3232                                                         load_spreg( R_ECX, R_FPSCR );
  3233                                                         XOR_imm32_r32( FPSCR_SZ, R_ECX );
  3234                                                         store_spreg( R_ECX, R_FPSCR );
  3236                                                         break;
  3237                                                     case 0x2:
  3238                                                         { /* FRCHG */
  3239                                                         check_fpuen();
  3240                                                         load_spreg( R_ECX, R_FPSCR );
  3241                                                         XOR_imm32_r32( FPSCR_FR, R_ECX );
  3242                                                         store_spreg( R_ECX, R_FPSCR );
  3243                                                         update_fr_bank( R_ECX );
  3245                                                         break;
  3246                                                     case 0x3:
  3247                                                         { /* UNDEF */
  3248                                                         if( sh4_x86.in_delay_slot ) {
  3249                                                     	SLOTILLEGAL();
  3250                                                         } else {
  3251                                                     	JMP_exit(EXIT_ILLEGAL);
  3252                                                     	return 1;
  3255                                                         break;
  3256                                                     default:
  3257                                                         UNDEF();
  3258                                                         break;
  3260                                                 break;
  3262                                         break;
  3264                                 break;
  3265                             default:
  3266                                 UNDEF();
  3267                                 break;
  3269                         break;
  3270                     case 0xE:
  3271                         { /* FMAC FR0, FRm, FRn */
  3272                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3273                         check_fpuen();
  3274                         load_spreg( R_ECX, R_FPSCR );
  3275                         load_spreg( R_EDX, REG_OFFSET(fr_bank));
  3276                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3277                         JNE_rel8(18, doubleprec);
  3278                         push_fr( R_EDX, 0 );
  3279                         push_fr( R_EDX, FRm );
  3280                         FMULP_st(1);
  3281                         push_fr( R_EDX, FRn );
  3282                         FADDP_st(1);
  3283                         pop_fr( R_EDX, FRn );
  3284                         JMP_rel8(16, end);
  3285                         JMP_TARGET(doubleprec);
  3286                         push_dr( R_EDX, 0 );
  3287                         push_dr( R_EDX, FRm );
  3288                         FMULP_st(1);
  3289                         push_dr( R_EDX, FRn );
  3290                         FADDP_st(1);
  3291                         pop_dr( R_EDX, FRn );
  3292                         JMP_TARGET(end);
  3294                         break;
  3295                     default:
  3296                         UNDEF();
  3297                         break;
  3299                 break;
  3302     if( sh4_x86.in_delay_slot ) {
  3303 	ADD_imm8s_r32(2,R_ESI);
  3304 	sh4_x86.in_delay_slot = FALSE;
  3305 	return 1;
  3306     } else {
  3307 	INC_r32(R_ESI);
  3309     return 0;
.