filename | src/sh4/sh4core.h |
changeset | 1067:d3c00ffccfcd |
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author | nkeynes |
date | Thu Dec 23 17:50:10 2010 +1000 (13 years ago) |
permissions | -rw-r--r-- |
last change | Clone iso_memory_stream_new() as iso_mem_stream_new(), since current versions of libisofs have made it unlinkable on linux |
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1 /**
2 * $Id$
3 *
4 * This file defines the internal functions used by the SH4 core,
5 *
6 * Copyright (c) 2005-2008 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #ifndef lxdream_sh4core_H
20 #define lxdream_sh4core_H 1
22 #include <glib/gtypes.h>
23 #include <stdint.h>
24 #include <stdio.h>
25 #include "mem.h"
26 #include "sh4/sh4.h"
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
32 /* Breakpoint data structure */
33 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
34 extern int sh4_breakpoint_count;
35 extern gboolean sh4_starting;
37 /**
38 * Cached direct pointer to the current instruction page. If AT is on, this
39 * is derived from the ITLB, otherwise this will be the entire memory region.
40 * This is actually a fairly useful optimization, as we can make a lot of
41 * assumptions about the "current page" that we can't make in general for
42 * arbitrary virtual addresses.
43 */
44 struct sh4_icache_struct {
45 sh4ptr_t page; // Page pointer (NULL if no page)
46 sh4vma_t page_vma; // virtual address of the page.
47 sh4addr_t page_ppa; // physical address of the page
48 uint32_t mask; // page mask
49 };
50 extern struct sh4_icache_struct sh4_icache;
52 /**
53 * Test if a given address is contained in the current icache entry
54 */
55 #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask))
56 /**
57 * Return a pointer for the given vma, under the assumption that it is
58 * actually contained in the current icache entry.
59 */
60 #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma))
61 /**
62 * Return the physical (external) address for the given vma, assuming that it is
63 * actually contained in the current icache entry.
64 */
65 #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma))
67 /**
68 * Return the virtual (vma) address for the first address past the end of the
69 * cache entry. Assumes that there is in fact a current icache entry.
70 */
71 #define GET_ICACHE_END() (sh4_icache.page_vma + (~sh4_icache.mask) + 1)
74 /**
75 * SH4 vm-exit flag - exit the current block but continue normally
76 */
77 #define CORE_EXIT_CONTINUE 1
79 /**
80 * SH4 vm-exit flag - exit the current block and halt immediately (eg fatal error)
81 */
82 #define CORE_EXIT_HALT 2
84 /**
85 * SH4 vm-exit flag - exit the current block and halt immediately for a system
86 * breakpoint.
87 */
88 #define CORE_EXIT_BREAKPOINT 3
90 /**
91 * SH4 vm-exit flag - exit the current block and continue after performing a full
92 * system reset (dreamcast_reset())
93 */
94 #define CORE_EXIT_SYSRESET 4
96 /**
97 * SH4 vm-exit flag - exit the current block and continue after the next IRQ.
98 */
99 #define CORE_EXIT_SLEEP 5
101 /**
102 * SH4 vm-exit flag - exit the current block and flush all instruction caches (ie
103 * if address translation has changed)
104 */
105 #define CORE_EXIT_FLUSH_ICACHE 6
107 /**
108 * SH4 vm-exit flag - exit the current block following a taken exception. sh4r.spc
109 * is fixed up by recovery rather than sh4r.pc.
110 */
111 #define CORE_EXIT_EXCEPTION 7
113 typedef uint32_t (*sh4_run_slice_fn)(uint32_t);
115 /* SH4 module functions */
116 void sh4_init( void );
117 void sh4_reset( void );
118 void sh4_run( void );
119 void sh4_stop( void );
120 uint32_t sh4_run_slice( uint32_t nanos ); // Run single timeslice using emulator
121 uint32_t sh4_xlat_run_slice( uint32_t nanos ); // Run single timeslice using translator
122 uint32_t sh4_sleep_run_slice( uint32_t nanos ); // Run single timeslice while the CPU is asleep
124 /**
125 * Immediately exit from the currently executing instruction with the given
126 * exit code. This method does not return.
127 */
128 void sh4_core_exit( int exit_code );
130 /**
131 * Exit the current block at the end of the current instruction, flush the
132 * translation cache (completely) and return control to sh4_xlat_run_slice.
133 *
134 * As a special case, if the current instruction is actually the last
135 * instruction in the block (ie it's in a delay slot), this function
136 * returns to allow normal completion of the translation block. Otherwise
137 * this function never returns.
138 *
139 * Must only be invoked (indirectly) from within translated code.
140 */
141 void sh4_flush_icache();
143 /* SH4 peripheral module functions */
144 void CPG_reset( void );
145 void DMAC_reset( void );
146 void DMAC_run_slice( uint32_t );
147 void DMAC_save_state( FILE * );
148 int DMAC_load_state( FILE * );
149 void INTC_reset( void );
150 void INTC_save_state( FILE *f );
151 int INTC_load_state( FILE *f );
152 void MMU_init( void );
153 void MMU_reset( void );
154 void MMU_save_state( FILE *f );
155 int MMU_load_state( FILE *f );
156 void MMU_ldtlb();
157 void CCN_reset();
158 void CCN_set_cache_control( int reg );
159 void CCN_save_state( FILE *f );
160 int CCN_load_state( FILE *f );
161 void SCIF_reset( void );
162 void SCIF_run_slice( uint32_t );
163 void SCIF_save_state( FILE *f );
164 int SCIF_load_state( FILE *f );
165 void SCIF_update_line_speed(void);
166 void TMU_init( void );
167 void TMU_reset( void );
168 void TMU_run_slice( uint32_t );
169 void TMU_save_state( FILE * );
170 int TMU_load_state( FILE * );
171 void TMU_update_clocks( void );
172 void PMM_reset( void );
173 void PMM_write_control( int, uint32_t );
174 void PMM_save_state( FILE * );
175 int PMM_load_state( FILE * );
176 uint32_t PMM_run_slice( uint32_t );
177 uint32_t sh4_translate_run_slice(uint32_t);
178 uint32_t sh4_emulate_run_slice(uint32_t);
180 /* SH4 instruction support methods */
181 mem_region_fn_t FASTCALL sh7750_decode_address( sh4addr_t address );
182 void FASTCALL sh7750_decode_address_copy( sh4addr_t address, mem_region_fn_t result );
183 void FASTCALL sh4_sleep( void );
184 void FASTCALL sh4_fsca( uint32_t angle, float *fr );
185 void FASTCALL sh4_ftrv( float *fv );
186 uint32_t FASTCALL sh4_read_sr(void);
187 void FASTCALL sh4_write_sr(uint32_t val);
188 void FASTCALL sh4_write_fpscr(uint32_t val);
189 void FASTCALL sh4_switch_fr_banks(void);
190 void FASTCALL signsat48(void);
191 gboolean sh4_has_page( sh4vma_t vma );
193 /* SH4 Memory */
194 #define MMU_VMA_ERROR 0x80000000
195 /**
196 * Update the sh4_icache structure to contain the specified vma. If the vma
197 * cannot be resolved, an MMU exception is raised and the function returns
198 * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly.
199 * Note: If the vma resolves to a non-memory area, sh4_icache will be
200 * invalidated, but the function will still return TRUE.
201 * @return FALSE if an MMU exception was raised, otherwise TRUE.
202 */
203 gboolean FASTCALL mmu_update_icache( sh4vma_t addr );
205 int64_t FASTCALL sh4_read_quad( sh4addr_t addr );
206 int32_t FASTCALL sh4_read_long( sh4addr_t addr );
207 int32_t FASTCALL sh4_read_word( sh4addr_t addr );
208 int32_t FASTCALL sh4_read_byte( sh4addr_t addr );
209 void FASTCALL sh4_write_quad( sh4addr_t addr, uint64_t val );
210 void FASTCALL sh4_write_long( sh4addr_t addr, uint32_t val );
211 void FASTCALL sh4_write_word( sh4addr_t addr, uint32_t val );
212 void FASTCALL sh4_write_byte( sh4addr_t addr, uint32_t val );
213 int32_t sh4_read_phys_word( sh4addr_t addr );
214 void FASTCALL sh4_flush_store_queue( sh4addr_t addr );
215 void FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr, void *exc );
217 /* SH4 Exceptions */
218 #define EXC_POWER_RESET 0x000 /* reset vector */
219 #define EXC_MANUAL_RESET 0x020 /* reset vector */
220 #define EXC_TLB_MISS_READ 0x040 /* TLB vector */
221 #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */
222 #define EXC_INIT_PAGE_WRITE 0x080
223 #define EXC_TLB_PROT_READ 0x0A0
224 #define EXC_TLB_PROT_WRITE 0x0C0
225 #define EXC_DATA_ADDR_READ 0x0E0
226 #define EXC_DATA_ADDR_WRITE 0x100
227 #define EXC_TLB_MULTI_HIT 0x140
228 #define EXC_SLOT_ILLEGAL 0x1A0
229 #define EXC_ILLEGAL 0x180
230 #define EXC_TRAP 0x160
231 #define EXC_FPU_DISABLED 0x800
232 #define EXC_SLOT_FPU_DISABLED 0x820
234 #define EXV_EXCEPTION 0x100 /* General exception vector */
235 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
236 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
238 void FASTCALL sh4_raise_exception( int );
239 void FASTCALL sh4_raise_reset( int );
240 void FASTCALL sh4_raise_trap( int );
241 void FASTCALL sh4_raise_tlb_exception( int, sh4vma_t );
242 void FASTCALL sh4_raise_tlb_multihit( sh4vma_t );
243 void FASTCALL sh4_accept_interrupt( void );
245 /**
246 * Complete the current instruction as part of a core exit. Prevents the
247 * system from being left in an inconsistent state when an exit is
248 * triggered during a memory write.
249 */
250 void sh4_finalize_instruction( void );
252 /* Status Register (SR) bits */
253 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
254 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
255 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
256 #define SR_FD 0x00008000 /* FPU disable */
257 #define SR_M 0x00000200
258 #define SR_Q 0x00000100
259 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
260 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
261 #define SR_T 0x00000001 /* True/false or carry/borrow */
262 #define SR_MASK 0x700083F3
263 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
264 #define SR_MDRB 0x60000000 /* MD+RB mask for convenience */
266 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
267 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
268 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
270 #define FPSCR_FR 0x00200000 /* FPU register bank */
271 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
272 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
273 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
274 #define FPSCR_CAUSE 0x0003F000
275 #define FPSCR_ENABLE 0x00000F80
276 #define FPSCR_FLAG 0x0000007C
277 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
278 #define FPSCR_MASK 0x003FFFFF
280 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
281 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
282 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
284 #define FR(x) sh4r.fr[0][(x)^1]
285 #define DRF(x) *((double *)&sh4r.fr[0][(x)<<1])
286 #define XF(x) sh4r.fr[1][(x)^1]
287 #define XDR(x) *((double *)&sh4r.fr[1][(x)<<1])
288 #define DRb(x,b) *((double *)&sh4r.fr[b][(x)<<1])
289 #define DR(x) *((double *)&sh4r.fr[x&1][x&0x0E])
290 #define FPULf (sh4r.fpul.f)
291 #define FPULi (sh4r.fpul.i)
293 /**************** SH4 internal memory regions *****************/
294 extern struct mem_region_fn p4_region_itlb_addr;
295 extern struct mem_region_fn p4_region_itlb_data;
296 extern struct mem_region_fn p4_region_utlb_addr;
297 extern struct mem_region_fn p4_region_utlb_data;
298 extern struct mem_region_fn p4_region_icache_addr;
299 extern struct mem_region_fn p4_region_icache_data;
300 extern struct mem_region_fn p4_region_ocache_addr;
301 extern struct mem_region_fn p4_region_ocache_data;
303 #define OC_ENABLED 1
305 #ifdef __cplusplus
306 }
307 #endif
309 #endif /* !lxdream_sh4core_H */
.