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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 295:6637664291a8
prev284:808617ee7135
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author nkeynes
date Tue Jan 16 10:34:46 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Bug 24: Initial implementation of "save scene" function
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     1 /**
     2  * $Id: pvr2.c,v 1.40 2007-01-16 10:34:46 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "eventq.h"
    22 #include "display.h"
    23 #include "mem.h"
    24 #include "asic.h"
    25 #include "clock.h"
    26 #include "pvr2/pvr2.h"
    27 #include "sh4/sh4core.h"
    28 #define MMIO_IMPL
    29 #include "pvr2/pvr2mmio.h"
    31 char *video_base;
    33 static void pvr2_init( void );
    34 static void pvr2_reset( void );
    35 static uint32_t pvr2_run_slice( uint32_t );
    36 static void pvr2_save_state( FILE *f );
    37 static int pvr2_load_state( FILE *f );
    38 static void pvr2_update_raster_posn( uint32_t nanosecs );
    39 static void pvr2_schedule_line_event( int eventid, int line );
    40 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines );
    41 uint32_t pvr2_get_sync_status();
    43 void pvr2_display_frame( void );
    45 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
    47 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    48 					pvr2_run_slice, NULL,
    49 					pvr2_save_state, pvr2_load_state };
    52 display_driver_t display_driver = NULL;
    54 struct video_timing {
    55     int fields_per_second;
    56     int total_lines;
    57     int retrace_lines;
    58     int line_time_ns;
    59 };
    61 struct video_timing pal_timing = { 50, 625, 65, 31945 };
    62 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    64 struct pvr2_state {
    65     uint32_t frame_count;
    66     uint32_t line_count;
    67     uint32_t line_remainder;
    68     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    69     uint32_t irq_vpos1;
    70     uint32_t irq_vpos2;
    71     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    72     gchar *save_next_render_filename;
    73     /* timing */
    74     uint32_t dot_clock;
    75     uint32_t total_lines;
    76     uint32_t line_size;
    77     uint32_t line_time_ns;
    78     uint32_t vsync_lines;
    79     uint32_t hsync_width_ns;
    80     uint32_t front_porch_ns;
    81     uint32_t back_porch_ns;
    82     uint32_t retrace_start_line;
    83     uint32_t retrace_end_line;
    84     gboolean interlaced;
    85     struct video_timing timing;
    86 } pvr2_state;
    88 struct video_buffer video_buffer[2];
    89 int video_buffer_idx = 0;
    91 /**
    92  * Event handler for the retrace callback (fires on line 0 normally)
    93  */
    94 static void pvr2_retrace_callback( int eventid ) {
    95     asic_event( eventid );
    96     pvr2_update_raster_posn(sh4r.slice_cycle);
    97     pvr2_schedule_line_event( EVENT_RETRACE, 0 );
    98 }
   100 /**
   101  * Event handler for the scanline callbacks. Fires the corresponding
   102  * ASIC event, and resets the timer for the next field.
   103  */
   104 static void pvr2_scanline_callback( int eventid ) {
   105     asic_event( eventid );
   106     pvr2_update_raster_posn(sh4r.slice_cycle);
   107     if( eventid == EVENT_SCANLINE1 ) {
   108 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1 );
   109     } else {
   110 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1 );
   111     }
   112 }
   114 static void pvr2_init( void )
   115 {
   116     register_io_region( &mmio_region_PVR2 );
   117     register_io_region( &mmio_region_PVR2PAL );
   118     register_io_region( &mmio_region_PVR2TA );
   119     register_event_callback( EVENT_RETRACE, pvr2_retrace_callback );
   120     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   121     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   122     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   123     texcache_init();
   124     pvr2_reset();
   125     pvr2_ta_reset();
   126     pvr2_state.save_next_render_filename = NULL;
   127 }
   129 static void pvr2_reset( void )
   130 {
   131     pvr2_state.line_count = 0;
   132     pvr2_state.line_remainder = 0;
   133     pvr2_state.cycles_run = 0;
   134     pvr2_state.irq_vpos1 = 0;
   135     pvr2_state.irq_vpos2 = 0;
   136     pvr2_state.timing = ntsc_timing;
   137     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   138     pvr2_state.back_porch_ns = 4000;
   139     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   140     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   141     mmio_region_PVR2_write( YUV_ADDR, 0 );
   142     mmio_region_PVR2_write( YUV_CFG, 0 );
   143     video_buffer_idx = 0;
   145     pvr2_ta_init();
   146     pvr2_render_init();
   147     texcache_flush();
   148 }
   150 static void pvr2_save_state( FILE *f )
   151 {
   152     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   153     pvr2_ta_save_state( f );
   154     pvr2_yuv_save_state( f );
   155 }
   157 static int pvr2_load_state( FILE *f )
   158 {
   159     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   160 	return 1;
   161     if( pvr2_ta_load_state(f) ) {
   162 	return 1;
   163     }
   164     return pvr2_yuv_load_state(f);
   165 }
   167 /**
   168  * Update the current raster position to the given number of nanoseconds,
   169  * relative to the last time slice. (ie the raster will be adjusted forward
   170  * by nanosecs - nanosecs_already_run_this_timeslice)
   171  */
   172 static void pvr2_update_raster_posn( uint32_t nanosecs )
   173 {
   174     uint32_t old_line_count = pvr2_state.line_count;
   175     if( pvr2_state.line_time_ns == 0 ) {
   176 	return; /* do nothing */
   177     }
   178     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   179     pvr2_state.cycles_run = nanosecs;
   180     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   181 	pvr2_state.line_count ++;
   182 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   183     }
   185     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   186 	pvr2_state.line_count -= pvr2_state.total_lines;
   187 	if( pvr2_state.interlaced ) {
   188 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   189 	}
   190     }
   191     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   192 	(old_line_count < pvr2_state.retrace_end_line ||
   193 	 old_line_count > pvr2_state.line_count) ) {
   194 	pvr2_display_frame();
   195     }
   196 }
   198 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   199 {
   200     pvr2_update_raster_posn( nanosecs );
   201     pvr2_state.cycles_run = 0;
   202     return nanosecs;
   203 }
   205 int pvr2_get_frame_count() 
   206 {
   207     return pvr2_state.frame_count;
   208 }
   210 gboolean pvr2_save_next_scene( const gchar *filename )
   211 {
   212     if( pvr2_state.save_next_render_filename != NULL ) {
   213 	g_free( pvr2_state.save_next_render_filename );
   214     } 
   215     pvr2_state.save_next_render_filename = g_strdup(filename);
   216     return TRUE;
   217 }
   221 /**
   222  * Display the next frame, copying the current contents of video ram to
   223  * the window. If the video configuration has changed, first recompute the
   224  * new frame size/depth.
   225  */
   226 void pvr2_display_frame( void )
   227 {
   228     uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   230     int dispsize = MMIO_READ( PVR2, DISP_SIZE );
   231     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   232     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   233     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   234     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   235     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   236     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   237     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   238     video_buffer_t buffer = &video_buffer[video_buffer_idx];
   239     video_buffer_idx = !video_buffer_idx;
   240     video_buffer_t last = &video_buffer[video_buffer_idx];
   241     buffer->rowstride = (vid_ppl + vid_stride) << 2;
   242     buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
   243     buffer->vres = vid_lpf;
   244     if( interlaced ) buffer->vres <<= 1;
   245     switch( (dispmode & DISPMODE_COL) >> 2 ) {
   246     case 0: 
   247 	buffer->colour_format = COLFMT_ARGB1555;
   248 	buffer->hres = vid_ppl << 1; 
   249 	break;
   250     case 1: 
   251 	buffer->colour_format = COLFMT_RGB565;
   252 	buffer->hres = vid_ppl << 1; 
   253 	break;
   254     case 2:
   255 	buffer->colour_format = COLFMT_RGB888;
   256 	buffer->hres = (vid_ppl << 2) / 3; 
   257 	break;
   258     case 3: 
   259 	buffer->colour_format = COLFMT_ARGB8888;
   260 	buffer->hres = vid_ppl; 
   261 	break;
   262     }
   264     if( buffer->hres <=8 )
   265 	buffer->hres = 640;
   266     if( buffer->vres <=8 )
   267 	buffer->vres = 480;
   268     if( display_driver != NULL ) {
   269 	if( buffer->hres != last->hres ||
   270 	    buffer->vres != last->vres ||
   271 	    buffer->colour_format != last->colour_format) {
   272 	    display_driver->set_display_format( buffer->hres, buffer->vres,
   273 						buffer->colour_format );
   274 	}
   275 	if( !bEnabled ) {
   276 	    display_driver->display_blank_frame( 0 );
   277 	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
   278 	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
   279 	    display_driver->display_blank_frame( colour );
   280 	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   281 	    display_driver->display_frame( buffer );
   282 	}
   283     }
   284     pvr2_state.frame_count++;
   285 }
   287 /**
   288  * This has to handle every single register individually as they all get masked 
   289  * off differently (and its easier to do it at write time)
   290  */
   291 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   292 {
   293     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   294         MMIO_WRITE( PVR2, reg, val );
   295         return;
   296     }
   298     switch(reg) {
   299     case PVRID:
   300     case PVRVER:
   301     case GUNPOS: /* Read only registers */
   302 	break;
   303     case PVRRESET:
   304 	val &= 0x00000007; /* Do stuff? */
   305 	MMIO_WRITE( PVR2, reg, val );
   306 	break;
   307     case RENDER_START: /* Don't really care what value */
   308 	if( pvr2_state.save_next_render_filename != NULL ) {
   309 	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
   310 		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
   311 	    }
   312 	    g_free( pvr2_state.save_next_render_filename );
   313 	    pvr2_state.save_next_render_filename = NULL;
   314 	}
   315 	pvr2_render_scene();
   316 	break;
   317     case RENDER_POLYBASE:
   318     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   319     	break;
   320     case RENDER_TSPCFG:
   321     	MMIO_WRITE( PVR2, reg, val&0x00010101 );
   322     	break;
   323     case DISP_BORDER:
   324     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   325     	break;
   326     case DISP_MODE:
   327     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   328     	break;
   329     case RENDER_MODE:
   330     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   331     	break;
   332     case RENDER_SIZE:
   333     	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   334     	break;
   335     case DISP_ADDR1:
   336 	val &= 0x00FFFFFC;
   337 	MMIO_WRITE( PVR2, reg, val );
   338 	pvr2_update_raster_posn(sh4r.slice_cycle);
   339 	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||
   340 	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {
   341 	    pvr2_display_frame();
   342 	}
   343 	break;
   344     case DISP_ADDR2:
   345     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   346     	break;
   347     case DISP_SIZE:
   348     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   349     	break;
   350     case RENDER_ADDR1:
   351     case RENDER_ADDR2:
   352     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   353     	break;
   354     case RENDER_HCLIP:
   355 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   356 	break;
   357     case RENDER_VCLIP:
   358 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   359 	break;
   360     case DISP_HPOSIRQ:
   361 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   362 	break;
   363     case DISP_VPOSIRQ:
   364 	val = val & 0x03FF03FF;
   365 	pvr2_state.irq_vpos1 = (val >> 16);
   366 	pvr2_state.irq_vpos2 = val & 0x03FF;
   367 	pvr2_update_raster_posn(sh4r.slice_cycle);
   368 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
   369 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
   370 	MMIO_WRITE( PVR2, reg, val );
   371 	break;
   372     case RENDER_NEARCLIP:
   373 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   374 	break;
   375     case RENDER_SHADOW:
   376 	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   377 	break;
   378     case RENDER_OBJCFG:
   379     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   380     	break;
   381     case RENDER_TSPCLIP:
   382     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   383     	break;
   384     case RENDER_FARCLIP:
   385 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   386 	break;
   387     case RENDER_BGPLANE:
   388     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   389     	break;
   390     case RENDER_ISPCFG:
   391     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   392     	break;
   393     case VRAM_CFG1:
   394 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   395 	break;
   396     case VRAM_CFG2:
   397 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   398 	break;
   399     case VRAM_CFG3:
   400 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   401 	break;
   402     case RENDER_FOGTBLCOL:
   403     case RENDER_FOGVRTCOL:
   404 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   405 	break;
   406     case RENDER_FOGCOEFF:
   407 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   408 	break;
   409     case RENDER_CLAMPHI:
   410     case RENDER_CLAMPLO:
   411 	MMIO_WRITE( PVR2, reg, val );
   412 	break;
   413     case RENDER_TEXSIZE:
   414 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   415 	break;
   416     case RENDER_PALETTE:
   417 	MMIO_WRITE( PVR2, reg, val&0x00000003 );
   418 	break;
   420 	/********** CRTC registers *************/
   421     case DISP_HBORDER:
   422     case DISP_VBORDER:
   423 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   424 	break;
   425     case DISP_TOTAL:
   426 	val = val & 0x03FF03FF;
   427 	MMIO_WRITE( PVR2, reg, val );
   428 	pvr2_update_raster_posn(sh4r.slice_cycle);
   429 	pvr2_state.total_lines = (val >> 16) + 1;
   430 	pvr2_state.line_size = (val & 0x03FF) + 1;
   431 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   432 	pvr2_state.retrace_end_line = 0x2A;
   433 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   434 	pvr2_schedule_line_event( EVENT_RETRACE, 0 );
   435 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 );
   436 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 );
   437 	break;
   438     case DISP_SYNCCFG:
   439 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   440 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   441 	break;
   442     case DISP_SYNCTIME:
   443 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   444 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   445 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   446 	break;
   447     case DISP_CFG2:
   448 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   449 	break;
   450     case DISP_HPOS:
   451 	val = val & 0x03FF;
   452 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   453 	MMIO_WRITE( PVR2, reg, val );
   454 	break;
   455     case DISP_VPOS:
   456 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   457 	break;
   459 	/*********** Tile accelerator registers ***********/
   460     case TA_POLYPOS:
   461     case TA_LISTPOS:
   462 	/* Readonly registers */
   463 	break;
   464     case TA_TILEBASE:
   465     case TA_LISTEND:
   466     case TA_LISTBASE:
   467 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   468 	break;
   469     case RENDER_TILEBASE:
   470     case TA_POLYBASE:
   471     case TA_POLYEND:
   472 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   473 	break;
   474     case TA_TILESIZE:
   475 	MMIO_WRITE( PVR2, reg, val&0x000F003F );
   476 	break;
   477     case TA_TILECFG:
   478 	MMIO_WRITE( PVR2, reg, val&0x00133333 );
   479 	break;
   480     case TA_INIT:
   481 	if( val & 0x80000000 )
   482 	    pvr2_ta_init();
   483 	break;
   484     case TA_REINIT:
   485 	break;
   486 	/**************** Scaler registers? ****************/
   487     case SCALERCFG:
   488 	/* KOS suggests bits as follows:
   489 	 *   0: enable vertical scaling
   490 	 *  10: ???
   491 	 *  16: enable FSAA
   492 	 */
   493 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   494 	break;
   496     case YUV_ADDR:
   497 	val = val & 0x00FFFFF8;
   498 	MMIO_WRITE( PVR2, reg, val );
   499 	pvr2_yuv_init( val );
   500 	break;
   501     case YUV_CFG:
   502 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   503 	pvr2_yuv_set_config(val);
   504 	break;
   506 	/**************** Unknowns ***************/
   507     case PVRUNK1:
   508     	MMIO_WRITE( PVR2, reg, val&0x000007FF );
   509     	break;
   510     case PVRUNK2:
   511 	MMIO_WRITE( PVR2, reg, val&0x00000007 );
   512 	break;
   513     case PVRUNK3:
   514 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   515 	break;
   516     case PVRUNK5:
   517 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   518 	break;
   519     case PVRUNK6:
   520 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   521 	break;
   522     case PVRUNK7:
   523 	MMIO_WRITE( PVR2, reg, val&0x00000001 );
   524 	break;
   525     }
   526 }
   528 /**
   529  * Calculate the current read value of the syncstat register, using
   530  * the current SH4 clock time as an offset from the last timeslice.
   531  * The register reads (LSB to MSB) as:
   532  *     0..9  Current scan line
   533  *     10    Odd/even field (1 = odd, 0 = even)
   534  *     11    Display active (including border and overscan)
   535  *     12    Horizontal sync off
   536  *     13    Vertical sync off
   537  * Note this method is probably incorrect for anything other than straight
   538  * interlaced PAL/NTSC, and needs further testing. 
   539  */
   540 uint32_t pvr2_get_sync_status()
   541 {
   542     pvr2_update_raster_posn(sh4r.slice_cycle);
   543     uint32_t result = pvr2_state.line_count;
   545     if( pvr2_state.odd_even_field ) {
   546 	result |= 0x0400;
   547     }
   548     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   549 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   550 	    result |= 0x1000; /* !HSYNC */
   551 	}
   552 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   553 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   554 		result |= 0x2800; /* Display active */
   555 	    } else {
   556 		result |= 0x2000; /* Front porch */
   557 	    }
   558 	}
   559     } else {
   560 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   561 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   562 		result |= 0x3800; /* Display active */
   563 	    } else {
   564 		result |= 0x3000;
   565 	    }
   566 	} else {
   567 	    result |= 0x1000; /* Back porch */
   568 	}
   569     }
   570     return result;
   571 }
   573 /**
   574  * Schedule an event for the start of the given line. If the line is actually
   575  * the current line, schedules it for the next field. 
   576  * The raster position should be updated before calling this method.
   577  */
   578 static void pvr2_schedule_line_event( int eventid, int line )
   579 {
   580     uint32_t time;
   581     if( line <= pvr2_state.line_count ) {
   582 	time = (pvr2_state.total_lines - pvr2_state.line_count + line) * pvr2_state.line_time_ns
   583 	    - pvr2_state.line_remainder;
   584     } else {
   585 	time = (line - pvr2_state.line_count) * pvr2_state.line_time_ns - pvr2_state.line_remainder;
   586     }
   588     if( line < pvr2_state.total_lines ) {
   589 	event_schedule( eventid, time );
   590     } else {
   591 	event_cancel( eventid );
   592     }
   593 }
   595 /**
   596  * Schedule a "scanline" event. This actually goes off at
   597  * 2 * line in even fields and 2 * line + 1 in odd fields.
   598  * Otherwise this behaves as per pvr2_schedule_line_event().
   599  * The raster position should be updated before calling this
   600  * method.
   601  */
   602 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines )
   603 {
   604     uint32_t field = pvr2_state.odd_even_field;
   605     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   606 	field = !field;
   607     }
   609     line <<= 1;
   610     if( field ) {
   611 	line += 1;
   612     }
   614     if( line < pvr2_state.total_lines ) {
   615 	uint32_t lines;
   616 	uint32_t time;
   617 	if( line <= pvr2_state.line_count ) {
   618 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   619 	} else {
   620 	    lines = (line - pvr2_state.line_count);
   621 	}
   622 	if( lines <= minimum_lines ) {
   623 	    lines += pvr2_state.total_lines;
   624 	}
   625 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder;
   626 	event_schedule( eventid, time );
   627     } else {
   628 	event_cancel( eventid );
   629     }
   630 }
   632 MMIO_REGION_READ_FN( PVR2, reg )
   633 {
   634     switch( reg ) {
   635         case DISP_SYNCSTAT:
   636             return pvr2_get_sync_status();
   637         default:
   638             return MMIO_READ( PVR2, reg );
   639     }
   640 }
   642 MMIO_REGION_DEFFNS( PVR2PAL )
   644 void pvr2_set_base_address( uint32_t base ) 
   645 {
   646     mmio_region_PVR2_write( DISP_ADDR1, base );
   647 }
   652 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   653 {
   654     return 0xFFFFFFFF;
   655 }
   657 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   658 {
   659     pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
   660 }
.