2 * $Id: sh4core.h,v 1.16 2007-01-06 04:06:36 nkeynes Exp $
4 * This file defines the internal functions exported/used by the SH4 core,
5 * except for disassembly functions defined in sh4dasm.h
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
23 #include <glib/gtypes.h>
36 * SH4 is running normally
38 #define SH4_STATE_RUNNING 1
40 * SH4 is not executing instructions but all peripheral modules are still
43 #define SH4_STATE_SLEEP 2
45 * SH4 is not executing instructions, DMAC is halted, but all other peripheral
46 * modules are still running
48 #define SH4_STATE_DEEP_SLEEP 3
50 * SH4 is not executing instructions and all peripheral modules are also
51 * stopped. As close as you can get to powered-off without actually being
54 #define SH4_STATE_STANDBY 4
57 #define PENDING_EVENT 2
59 struct sh4_registers {
61 uint32_t r_bank[8]; /* hidden banked registers */
62 uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
63 uint32_t pr, pc, fpscr;
66 uint32_t m, q, s, t; /* really boolean - 0 or 1 */
69 int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
71 uint32_t new_pc; /* Not a real register, but used to handle delay slots */
72 uint32_t icount; /* Also not a real register, instruction counter */
73 uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
74 when no events are pending */
75 uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
76 int in_delay_slot; /* flag to indicate the current instruction is in
77 * a delay slot (certain rules apply) */
78 uint32_t slice_cycle; /* Current cycle within the timeslice */
79 int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
82 extern struct sh4_registers sh4r;
84 /* Public functions */
86 void sh4_init( void );
87 void sh4_reset( void );
89 void sh4_runto( uint32_t pc, uint32_t count );
90 void sh4_runfor( uint32_t count );
91 int sh4_isrunning( void );
92 void sh4_stop( void );
93 void sh4_set_pc( int );
94 gboolean sh4_execute_instruction( void );
95 gboolean sh4_raise_exception( int );
96 gboolean sh4_raise_slot_exception( int, int );
97 gboolean sh4_raise_tlb_exception( int );
98 void sh4_set_breakpoint( uint32_t pc, int type );
99 gboolean sh4_clear_breakpoint( uint32_t pc, int type );
100 int sh4_get_breakpoint( uint32_t pc );
102 #define BREAK_ONESHOT 1
106 int32_t sh4_read_long( uint32_t addr );
107 int32_t sh4_read_word( uint32_t addr );
108 int32_t sh4_read_byte( uint32_t addr );
109 void sh4_write_long( uint32_t addr, uint32_t val );
110 void sh4_write_word( uint32_t addr, uint32_t val );
111 void sh4_write_byte( uint32_t addr, uint32_t val );
112 int32_t sh4_read_phys_word( uint32_t addr );
114 /* Peripheral functions */
115 void CPG_reset( void );
116 void TMU_run_slice( uint32_t );
117 void TMU_update_clocks( void );
118 void TMU_reset( void );
119 void TMU_save_state( FILE * );
120 int TMU_load_state( FILE * );
121 void DMAC_reset( void );
122 void DMAC_run_slice( uint32_t );
123 void DMAC_save_state( FILE * );
124 int DMAC_load_state( FILE * );
125 void SCIF_reset( void );
126 void SCIF_run_slice( uint32_t );
127 void SCIF_save_state( FILE *f );
128 int SCIF_load_state( FILE *f );
129 void INTC_reset( void );
130 void INTC_save_state( FILE *f );
131 int INTC_load_state( FILE *f );
133 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
134 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
135 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
136 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
137 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
138 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
140 /* Status Register (SR) bits */
141 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
142 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
143 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
144 #define SR_FD 0x00008000 /* FPU disable */
145 #define SR_M 0x00000200
146 #define SR_Q 0x00000100
147 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
148 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
149 #define SR_T 0x00000001 /* True/false or carry/borrow */
150 #define SR_MASK 0x700083F3
151 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
153 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
154 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
155 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
157 #define FPSCR_FR 0x00200000 /* FPU register bank */
158 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
159 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
160 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
161 #define FPSCR_CAUSE 0x0003F000
162 #define FPSCR_ENABLE 0x00000F80
163 #define FPSCR_FLAG 0x0000007C
164 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
166 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
167 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
168 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
170 #define FR(x) sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][(x)^1]
171 #define DR(x) ((double *)(sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]))[x]
172 #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
173 #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
174 #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
175 /* Exceptions (for use with sh4_raise_exception) */
177 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
178 #define EX_SLOT_ILLEGAL 0x1A0, 0x100
179 #define EX_TLB_MISS_READ 0x040, 0x400
180 #define EX_TLB_MISS_WRITE 0x060, 0x400
181 #define EX_INIT_PAGE_WRITE 0x080, 0x100
182 #define EX_TLB_PROT_READ 0x0A0, 0x100
183 #define EX_TLB_PROT_WRITE 0x0C0, 0x100
184 #define EX_DATA_ADDR_READ 0x0E0, 0x100
185 #define EX_DATA_ADDR_WRITE 0x100, 0x100
186 #define EX_FPU_EXCEPTION 0x120, 0x100
187 #define EX_TRAPA 0x160, 0x100
188 #define EX_BREAKPOINT 0x1E0, 0x100
189 #define EX_FPU_DISABLED 0x800, 0x100
190 #define EX_SLOT_FPU_DISABLED 0x820, 0x100
192 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
.