filename | src/sh4/sh4.c |
changeset | 905:4c17ebd9ef5e |
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author | nkeynes |
date | Sun Dec 14 07:50:48 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Setup a 'proper' stackframe in translated blocks. This doesn't affect performance noticeably, but does ensure that a) The stack is aligned correctly on OS X with no extra effort, and b) We can't mess up the stack and crash that way anymore. Replace all PUSH/POP instructions (outside of prologue/epilogue) with ESP-rel moves to stack local variables. Finally merge ia32mac and ia32abi together, since they're pretty much the same now anyway (and thereby simplifying maintenance a good deal) |
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1 /**
2 * $Id$
3 *
4 * SH4 parent module for all CPU modes and SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include <setjmp.h>
23 #include <assert.h>
24 #include "lxdream.h"
25 #include "dreamcast.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "eventq.h"
29 #include "syscall.h"
30 #include "sh4/intc.h"
31 #include "sh4/sh4core.h"
32 #include "sh4/sh4mmio.h"
33 #include "sh4/sh4stat.h"
34 #include "sh4/sh4trans.h"
35 #include "sh4/xltcache.h"
37 void sh4_init( void );
38 void sh4_xlat_init( void );
39 void sh4_reset( void );
40 void sh4_start( void );
41 void sh4_stop( void );
42 void sh4_save_state( FILE *f );
43 int sh4_load_state( FILE *f );
45 uint32_t sh4_run_slice( uint32_t );
46 uint32_t sh4_xlat_run_slice( uint32_t );
48 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
49 sh4_start, sh4_run_slice, sh4_stop,
50 sh4_save_state, sh4_load_state };
52 struct sh4_registers sh4r __attribute__((aligned(16)));
53 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
54 int sh4_breakpoint_count = 0;
55 sh4ptr_t sh4_main_ram;
56 gboolean sh4_starting = FALSE;
57 static gboolean sh4_use_translator = FALSE;
58 static jmp_buf sh4_exit_jmp_buf;
59 static gboolean sh4_running = FALSE;
60 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
62 void sh4_translate_set_enabled( gboolean use )
63 {
64 // No-op if the translator was not built
65 #ifdef SH4_TRANSLATOR
66 xlat_cache_init();
67 if( use ) {
68 sh4_translate_init();
69 }
70 sh4_use_translator = use;
71 #endif
72 }
74 gboolean sh4_translate_is_enabled()
75 {
76 return sh4_use_translator;
77 }
79 void sh4_init(void)
80 {
81 register_io_regions( mmio_list_sh4mmio );
82 sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
83 MMU_init();
84 TMU_init();
85 sh4_reset();
86 #ifdef ENABLE_SH4STATS
87 sh4_stats_reset();
88 #endif
89 }
91 void sh4_start(void)
92 {
93 sh4_starting = TRUE;
94 }
96 void sh4_reset(void)
97 {
98 if( sh4_use_translator ) {
99 xlat_flush_cache();
100 }
102 /* zero everything out, for the sake of having a consistent state. */
103 memset( &sh4r, 0, sizeof(sh4r) );
105 /* Resume running if we were halted */
106 sh4r.sh4_state = SH4_STATE_RUNNING;
108 sh4r.pc = 0xA0000000;
109 sh4r.new_pc= 0xA0000002;
110 sh4r.vbr = 0x00000000;
111 sh4r.fpscr = 0x00040001;
112 sh4r.sr = 0x700000F0;
114 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
115 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
117 /* Peripheral modules */
118 CPG_reset();
119 INTC_reset();
120 MMU_reset();
121 PMM_reset();
122 TMU_reset();
123 SCIF_reset();
125 #ifdef ENABLE_SH4STATS
126 sh4_stats_reset();
127 #endif
128 }
130 void sh4_stop(void)
131 {
132 if( sh4_use_translator ) {
133 /* If we were running with the translator, update new_pc and in_delay_slot */
134 sh4r.new_pc = sh4r.pc+2;
135 sh4r.in_delay_slot = FALSE;
136 }
138 }
140 /**
141 * Execute a timeslice using translated code only (ie translate/execute loop)
142 */
143 uint32_t sh4_run_slice( uint32_t nanosecs )
144 {
145 sh4r.slice_cycle = 0;
147 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
148 sh4_sleep_run_slice(nanosecs);
149 }
151 /* Setup for sudden vm exits */
152 switch( setjmp(sh4_exit_jmp_buf) ) {
153 case CORE_EXIT_BREAKPOINT:
154 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
155 /* fallthrough */
156 case CORE_EXIT_HALT:
157 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
158 TMU_run_slice( sh4r.slice_cycle );
159 SCIF_run_slice( sh4r.slice_cycle );
160 PMM_run_slice( sh4r.slice_cycle );
161 dreamcast_stop();
162 return sh4r.slice_cycle;
163 }
164 case CORE_EXIT_SYSRESET:
165 dreamcast_reset();
166 break;
167 case CORE_EXIT_SLEEP:
168 sh4_sleep_run_slice(nanosecs);
169 break;
170 case CORE_EXIT_FLUSH_ICACHE:
171 #ifdef SH4_TRANSLATOR
172 xlat_flush_cache();
173 #endif
174 break;
175 }
177 sh4_running = TRUE;
179 /* Execute the core's real slice */
180 #ifdef SH4_TRANSLATOR
181 if( sh4_use_translator ) {
182 sh4_translate_run_slice(nanosecs);
183 } else {
184 sh4_emulate_run_slice(nanosecs);
185 }
186 #else
187 sh4_emulate_run_slice(nanosecs);
188 #endif
190 /* And finish off the peripherals afterwards */
192 sh4_running = FALSE;
193 sh4_starting = FALSE;
194 sh4r.slice_cycle = nanosecs;
195 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
196 TMU_run_slice( nanosecs );
197 SCIF_run_slice( nanosecs );
198 PMM_run_slice( sh4r.slice_cycle );
199 }
200 return nanosecs;
201 }
203 void sh4_core_exit( int exit_code )
204 {
205 if( sh4_running ) {
206 #ifdef SH4_TRANSLATOR
207 if( sh4_use_translator ) {
208 sh4_translate_exit_recover();
209 }
210 #endif
211 // longjmp back into sh4_run_slice
212 sh4_running = FALSE;
213 longjmp(sh4_exit_jmp_buf, exit_code);
214 }
215 }
217 void sh4_flush_icache()
218 {
219 #ifdef SH4_TRANSLATOR
220 // FIXME: Special case needs to be generalized
221 if( sh4_use_translator ) {
222 if( sh4_translate_flush_cache() ) {
223 longjmp(sh4_exit_jmp_buf, CORE_EXIT_CONTINUE);
224 }
225 }
226 #endif
227 }
229 void sh4_save_state( FILE *f )
230 {
231 if( sh4_use_translator ) {
232 /* If we were running with the translator, update new_pc and in_delay_slot */
233 sh4r.new_pc = sh4r.pc+2;
234 sh4r.in_delay_slot = FALSE;
235 }
237 fwrite( &sh4r, sizeof(sh4r), 1, f );
238 MMU_save_state( f );
239 PMM_save_state( f );
240 INTC_save_state( f );
241 TMU_save_state( f );
242 SCIF_save_state( f );
243 }
245 int sh4_load_state( FILE * f )
246 {
247 if( sh4_use_translator ) {
248 xlat_flush_cache();
249 }
250 fread( &sh4r, sizeof(sh4r), 1, f );
251 MMU_load_state( f );
252 PMM_load_state( f );
253 INTC_load_state( f );
254 TMU_load_state( f );
255 return SCIF_load_state( f );
256 }
259 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
260 {
261 sh4_breakpoints[sh4_breakpoint_count].address = pc;
262 sh4_breakpoints[sh4_breakpoint_count].type = type;
263 if( sh4_use_translator ) {
264 xlat_invalidate_word( pc );
265 }
266 sh4_breakpoint_count++;
267 }
269 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
270 {
271 int i;
273 for( i=0; i<sh4_breakpoint_count; i++ ) {
274 if( sh4_breakpoints[i].address == pc &&
275 sh4_breakpoints[i].type == type ) {
276 while( ++i < sh4_breakpoint_count ) {
277 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
278 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
279 }
280 if( sh4_use_translator ) {
281 xlat_invalidate_word( pc );
282 }
283 sh4_breakpoint_count--;
284 return TRUE;
285 }
286 }
287 return FALSE;
288 }
290 int sh4_get_breakpoint( uint32_t pc )
291 {
292 int i;
293 for( i=0; i<sh4_breakpoint_count; i++ ) {
294 if( sh4_breakpoints[i].address == pc )
295 return sh4_breakpoints[i].type;
296 }
297 return 0;
298 }
300 void sh4_set_pc( int pc )
301 {
302 sh4r.pc = pc;
303 sh4r.new_pc = pc+2;
304 }
307 /******************************* Support methods ***************************/
309 static void sh4_switch_banks( )
310 {
311 uint32_t tmp[8];
313 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
314 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
315 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
316 }
318 void FASTCALL sh4_switch_fr_banks()
319 {
320 int i;
321 for( i=0; i<16; i++ ) {
322 float tmp = sh4r.fr[0][i];
323 sh4r.fr[0][i] = sh4r.fr[1][i];
324 sh4r.fr[1][i] = tmp;
325 }
326 }
328 void FASTCALL sh4_write_sr( uint32_t newval )
329 {
330 int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
331 int newbank = (newval&SR_MDRB) == SR_MDRB;
332 if( oldbank != newbank )
333 sh4_switch_banks();
334 sh4r.sr = newval & SR_MASK;
335 sh4r.t = (newval&SR_T) ? 1 : 0;
336 sh4r.s = (newval&SR_S) ? 1 : 0;
337 sh4r.m = (newval&SR_M) ? 1 : 0;
338 sh4r.q = (newval&SR_Q) ? 1 : 0;
339 intc_mask_changed();
340 }
342 void FASTCALL sh4_write_fpscr( uint32_t newval )
343 {
344 if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
345 sh4_switch_fr_banks();
346 }
347 sh4r.fpscr = newval & FPSCR_MASK;
348 }
350 uint32_t FASTCALL sh4_read_sr( void )
351 {
352 /* synchronize sh4r.sr with the various bitflags */
353 sh4r.sr &= SR_MQSTMASK;
354 if( sh4r.t ) sh4r.sr |= SR_T;
355 if( sh4r.s ) sh4r.sr |= SR_S;
356 if( sh4r.m ) sh4r.sr |= SR_M;
357 if( sh4r.q ) sh4r.sr |= SR_Q;
358 return sh4r.sr;
359 }
363 #define RAISE( x, v ) do{ \
364 if( sh4r.vbr == 0 ) { \
365 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
366 sh4_core_exit(CORE_EXIT_HALT); return FALSE; \
367 } else { \
368 sh4r.spc = sh4r.pc; \
369 sh4r.ssr = sh4_read_sr(); \
370 sh4r.sgr = sh4r.r[15]; \
371 MMIO_WRITE(MMU,EXPEVT,x); \
372 sh4r.pc = sh4r.vbr + v; \
373 sh4r.new_pc = sh4r.pc + 2; \
374 sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
375 if( sh4r.in_delay_slot ) { \
376 sh4r.in_delay_slot = 0; \
377 sh4r.spc -= 2; \
378 } \
379 } \
380 return TRUE; } while(0)
382 /**
383 * Raise a general CPU exception for the specified exception code.
384 * (NOT for TRAPA or TLB exceptions)
385 */
386 gboolean FASTCALL sh4_raise_exception( int code )
387 {
388 RAISE( code, EXV_EXCEPTION );
389 }
391 /**
392 * Raise a CPU reset exception with the specified exception code.
393 */
394 gboolean FASTCALL sh4_raise_reset( int code )
395 {
396 // FIXME: reset modules as per "manual reset"
397 sh4_reset();
398 MMIO_WRITE(MMU,EXPEVT,code);
399 sh4r.vbr = 0;
400 sh4r.pc = 0xA0000000;
401 sh4r.new_pc = sh4r.pc + 2;
402 sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
403 &(~SR_FD) );
404 return TRUE;
405 }
407 gboolean FASTCALL sh4_raise_trap( int trap )
408 {
409 MMIO_WRITE( MMU, TRA, trap<<2 );
410 RAISE( EXC_TRAP, EXV_EXCEPTION );
411 }
413 gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
414 if( sh4r.in_delay_slot ) {
415 return sh4_raise_exception(slot_code);
416 } else {
417 return sh4_raise_exception(normal_code);
418 }
419 }
421 gboolean FASTCALL sh4_raise_tlb_exception( int code )
422 {
423 RAISE( code, EXV_TLBMISS );
424 }
426 void FASTCALL sh4_accept_interrupt( void )
427 {
428 uint32_t code = intc_accept_interrupt();
429 sh4r.ssr = sh4_read_sr();
430 sh4r.spc = sh4r.pc;
431 sh4r.sgr = sh4r.r[15];
432 sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
433 MMIO_WRITE( MMU, INTEVT, code );
434 sh4r.pc = sh4r.vbr + 0x600;
435 sh4r.new_pc = sh4r.pc + 2;
436 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
437 }
439 void FASTCALL signsat48( void )
440 {
441 if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
442 sh4r.mac = 0xFFFF800000000000LL;
443 else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
444 sh4r.mac = 0x00007FFFFFFFFFFFLL;
445 }
447 void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
448 {
449 float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
450 *fr++ = cosf(angle);
451 *fr = sinf(angle);
452 }
454 /**
455 * Enter sleep mode (eg by executing a SLEEP instruction).
456 * Sets sh4_state appropriately and ensures any stopping peripheral modules
457 * are up to date.
458 */
459 void FASTCALL sh4_sleep(void)
460 {
461 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
462 sh4r.sh4_state = SH4_STATE_STANDBY;
463 /* Bring all running peripheral modules up to date, and then halt them. */
464 TMU_run_slice( sh4r.slice_cycle );
465 SCIF_run_slice( sh4r.slice_cycle );
466 PMM_run_slice( sh4r.slice_cycle );
467 } else {
468 if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
469 sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
470 /* Halt DMAC but other peripherals still running */
472 } else {
473 sh4r.sh4_state = SH4_STATE_SLEEP;
474 }
475 }
476 sh4_core_exit( CORE_EXIT_SLEEP );
477 }
479 /**
480 * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
481 * and restarts any peripheral devices that were stopped.
482 */
483 void sh4_wakeup(void)
484 {
485 switch( sh4r.sh4_state ) {
486 case SH4_STATE_STANDBY:
487 break;
488 case SH4_STATE_DEEP_SLEEP:
489 break;
490 case SH4_STATE_SLEEP:
491 break;
492 }
493 sh4r.sh4_state = SH4_STATE_RUNNING;
494 }
496 /**
497 * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
498 * Returns when either the SH4 wakes up (interrupt received) or the end of
499 * the slice is reached. Updates sh4.slice_cycle with the exit time and
500 * returns the same value.
501 */
502 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
503 {
504 int sleep_state = sh4r.sh4_state;
505 assert( sleep_state != SH4_STATE_RUNNING );
507 while( sh4r.event_pending < nanosecs ) {
508 sh4r.slice_cycle = sh4r.event_pending;
509 if( sh4r.event_types & PENDING_EVENT ) {
510 event_execute();
511 }
512 if( sh4r.event_types & PENDING_IRQ ) {
513 sh4_wakeup();
514 return sh4r.slice_cycle;
515 }
516 }
517 sh4r.slice_cycle = nanosecs;
518 return sh4r.slice_cycle;
519 }
522 /**
523 * Compute the matrix tranform of fv given the matrix xf.
524 * Both fv and xf are word-swapped as per the sh4r.fr banks
525 */
526 void FASTCALL sh4_ftrv( float *target )
527 {
528 float fv[4] = { target[1], target[0], target[3], target[2] };
529 target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
530 sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
531 target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
532 sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
533 target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
534 sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
535 target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
536 sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
537 }
539 gboolean sh4_has_page( sh4vma_t vma )
540 {
541 sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
542 return addr != MMU_VMA_ERROR && mem_has_page(addr);
543 }
.